TWI409972B - Method for fabricating a coarse surface of semiconductor - Google Patents

Abstract

The invention provides a semiconductor surface roughening method, which comprises the following steps: providing a substrate; forming a first type doped semiconductor layer and a light-emitting layer on the substrate sequentially; adjusting the air pressure range within 300 to 700 mbar; setting the predetermined temperature range to be 850 to 1200 degrees; and forming a second type doped semiconductor layer on the light-emitting surface. Then etching gas and passivation gas are introduced into the surface of the second type doped semiconductor layer for 10 to 120 minutes within the predetermined air pressure range and the predetermined temperature range, so that the surface concavo-convex structure of the second type doped semiconductor layer is realized.

Description

Semiconductor surface roughening method

The present invention relates to a semiconductor surface roughening method, and more particularly to a semiconductor surface roughening method that increases internal quantum efficiency.

Because the light-emitting diode has absolute advantages compared with the traditional light bulb, such as small size, long life, low voltage/current drive, not easy to break, no significant heat problem when emitting light, no mercury (no pollution problem), good luminous efficiency. (Power saving) and other characteristics, and in recent years, the luminous efficiency of LEDs has been increasing, so LEDs have gradually replaced fluorescent lamps and incandescent bulbs in some fields.

FIG. 1 is a schematic cross-sectional view of a conventional light emitting diode. The n-type semiconductor doping layer 104, the light emitting layer 106, and the p-type semiconductor doping layer 108 are sequentially formed on the substrate 102. In order to improve the light extraction efficiency of the light emitting diode, the p-type semiconductor is generally doped. Layer 108 is roughened to avoid internal total reflection. The conventional p-type semiconductor doped layer 108 is roughened by forming a concavo-convex structure 110 on the surface of the p-type semiconductor doped layer 108 under low temperature and low pressure conditions, but unfortunately, under such conditions, the p-type semiconductor is formed. The doped layer 108 is poor in quality and defects 112 occur, resulting in a decrease in internal quantum efficiency, which in turn reduces the overall external quantum efficiency of the light-emitting diode.

In view of the above, it is an object of the present invention to provide a semiconductor surface roughening method which can increase internal quantum efficiency.

The invention provides a manufacturing method for roughening a semiconductor surface, firstly providing a substrate, forming a first type doped semiconductor layer on the substrate, and forming a light emitting layer on the surface of the first type doped semiconductor layer, followed by a predetermined pressure range and predetermined Within the temperature range, A second type doped semiconductor layer is deposited on the surface of the light emitting layer. Thereafter, continuing to the predetermined gas pressure range and the predetermined temperature range, the etching gas and the passivation gas are introduced to the surface of the second-type doped semiconductor layer for a predetermined time to complete the uneven structure of the surface of the second-type doped semiconductor layer.

In an embodiment of the invention, the substrate may be a sapphire substrate or a tantalum carbide substrate.

In an embodiment of the invention, the first type doped semiconductor layer may be an n-type doped semiconductor layer, and the second type doped layer may be a p-type doped semiconductor layer.

In an embodiment of the invention, the first type doped semiconductor layer may be a p-type doped semiconductor layer, and the second type doped layer may be an n-type doped semiconductor layer.

In an embodiment of the invention, the luminescent layer may be a multi-quantum well structural layer.

In an embodiment of the invention, the doped semiconductor layers may be an n-type doped gallium nitride (GaN) layer and a p-type doped gallium nitride (GaN) layer, respectively, and the predetermined gas pressure ranges from 300 to 700 millimeters. Bar (mbar), the predetermined temperature range is 850 to 1200 degrees Celsius.

In an embodiment of the invention, the etching gas may be hydrogen (H ₂ ), and the passivating gas may be ammonia (NH ₃ ) or nitrogen (N ₂ ) for a predetermined time ranging from 10 to 120 minutes.

In an embodiment of the invention, the semiconductor surface roughening method may further comprise the steps of: after the predetermined time is over, the repair gas is introduced, and the repair gas may be trimethylgallium (TMGa) gas or triethyl gallium. (TEGa) or trimethylindium (TMIn).

In an embodiment of the invention, the concavo-convex structure may be a triangular pyramid-shaped concavo-convex structure having a height difference of 200 to 800 nm.

In an embodiment of the invention, the second type doped semiconductor layer may be formed by vapor deposition.

In the semiconductor surface roughening process of the present invention, the conditions of high temperature and high pressure are utilized, so that the density of the second type doped semiconductor layer is formed at a lower temperature and low pressure to improve the internal quantum efficiency. After forming the second type doped semiconductor layer, the etching gas is further introduced The row etching roughens the surface to form a textured structure on the surface of the second type doped semiconductor layer to increase the light extraction efficiency.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

2A and 2B are schematic cross-sectional views showing a semiconductor surface roughening process in an embodiment of the present invention. Referring to FIG. 2A, a substrate 208 is first provided, a first type doped semiconductor layer 210 is formed on the substrate 208, a light emitting layer 212 is formed on the first type doped semiconductor layer 210, and then, in a gas phase under high temperature and high pressure conditions. A deposition method deposits a second type doped semiconductor layer 214 on the surface of the light emitting layer 212. In the present embodiment, the predetermined pressure range in the reaction chamber is adjusted to be about 300 to 700 mbar, and the predetermined temperature range is controlled to be about 850 to 1200 degrees Celsius, thereby achieving an environment of high temperature and high pressure. In detail, the second type doped semiconductor layer 214 formed under the high temperature and high pressure condition has a conventional second type doped semiconductor layer formed under low temperature and low pressure conditions, thereby improving defects caused by the light emitting layer 212. The problem of the density reduction of the second type doped semiconductor layer is conventional. In the present case, the surface of the second type doped semiconductor layer 214 is reduced in nanometer level compared with the conventional second type doped semiconductor layer. The number of holes makes the current distribution relatively uniform, thereby improving the internal quantum efficiency of the second type doped semiconductor layer 214 of the present invention.

In the embodiment of the present invention, the material of the substrate 208 may be a sapphire substrate or a tantalum carbide substrate, the first type doped semiconductor layer 210 may be an n-type doped semiconductor layer, and the second type doped semiconductor layer 214 may be a p-type doped layer. A hetero semiconductor layer, but the invention is not limited thereto. In other embodiments, the first type doped semiconductor layer 210 may also be a p-type doped semiconductor layer, and the second type doped layer 214 may be an n-type doped semiconductor layer. In addition, the first type doped semiconductor layer 210, the light emitting layer 212, and the second type doped semiconductor layer 214 It can be composed of a III-V compound semiconductor material. Generally, the material of the first type doped semiconductor layer 210 may be n-type doped gallium nitride, and the material of the light emitting layer 212 may be a quantum well structure mainly composed of a group III-V element, such as gallium nitride (GaN). GaAs, GaAs, GaP, GaAsP, AlN, InN, ternary Indium Gallium Ni Aluminum gallium nitride (AlGaN), or quaternary composition of indium gallium arsenide (GaInAsN) and indium gallium phosphide (GaInPN), etc., and the material of the second type doped semiconductor layer 214 may be p-type doped Gallium nitride. For convenience of description, the second type semiconductor doped layer 214 is exemplified by a p-type gallium nitride doped semiconductor layer.

Referring again to FIG. 2B, in the same high temperature (850 to 1200 degrees Celsius) high voltage (300 to 700 mbar), the process continues on the surface of the p-type gallium nitride doped semiconductor layer 214 in the reaction chamber. After the etching gas 202 and the passivation gas 204 are introduced to reach the reaction for a predetermined time period of 10 to 120 minutes, the surface of the p-type gallium nitride doped semiconductor layer 214 is roughened by etching to form a plurality of concavo-convex structures 216. The purpose of roughening the surface of the p-type gallium nitride doped semiconductor layer 214 is to reduce the probability of total reflection from light when it is emitted, thereby improving the light extraction efficiency of the semiconductor. The purpose of the passivation gas 204 is that the etching gas 202 does not selectively etch the p-type gallium nitride doped semiconductor layer 214, that is, the lattice stable surface and the unstable surface of the p-type gallium nitride doped semiconductor layer 214. All of them will be eroded, and the passivation gas 204 can prevent the stable surface of the p-type gallium nitride doped semiconductor layer 214 from being etched, so that the uneven structure 216 formed on the surface to be etched can be relatively regular and not disordered. In the present embodiment, the etching gas 202 may be hydrogen (H ₂ ), and the passivating gas 204 may be ammonia (NH ₃ ) or nitrogen (N ₂ ). In addition, after the predetermined time period of the reaction is reached for 10 to 120 minutes, the above gas is turned off, and then the repair gas 206 is introduced, and the repair gas 206 is, for example, trimethylgallium (TMGa) gas or triethylgallium (TEGa). Or trimethyl indium (TMIn) or the like, which functions to fill in defects of nitrogen atom loss caused by the p-type gallium nitride doped semiconductor layer 214 during the vapor deposition process and the etching process. At this time, the roughened surface of the p-type gallium nitride doped semiconductor layer 214 has formed a plurality of triangular pyramidal concavo-convex structures having a height difference of 200 to 800 nm.

In the semiconductor surface roughening process of the present invention, the second type semiconductor doped layer is formed by using high temperature and high pressure conditions, and thereafter, the second type semiconductor is doped by introducing an etching gas, a passivation gas, and a repair gas under the same conditions. The roughening of the layer surface produces a triangular pyramidal concavo-convex structure, which reduces the probability of light being emitted from the second type semiconductor doped layer to cause total reflection, thereby increasing the light extraction efficiency of the element. In this way, the high-temperature and high-pressure process can also be etched to achieve the purpose of roughening the second-type semiconductor doping layer, and also makes the second-type semiconductor doped layer have a lower density and a lower temperature and low-pressure process, and relatively enhances the light-emitting diode. Quantum efficiency and overall external quantum efficiency.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

102, 208‧‧‧ substrate

104‧‧‧n-type semiconductor doped layer

106, 212‧‧‧Lighting layer

108‧‧‧p-type semiconductor doped layer

110, 216‧‧‧ concave and convex structure

112‧‧‧ Defects

202‧‧‧etching gas

204‧‧‧ Passivation gas

206‧‧‧ repair gas

210‧‧‧First type doped semiconductor layer

214‧‧‧Second type doped semiconductor layer

FIG. 1 is a schematic cross-sectional view of a conventional light emitting diode.

2A and 2B are schematic cross-sectional views showing a semiconductor surface roughening process in an embodiment of the present invention.

202‧‧‧etching gas

204‧‧‧ Passivation gas

206‧‧‧ repair gas

208‧‧‧Substrate

210‧‧‧First type doped semiconductor layer

212‧‧‧Lighting layer

214‧‧‧Second type doped semiconductor layer

216‧‧‧ concave and convex structure

Claims (8)

A semiconductor surface roughening method, comprising the steps of: providing a substrate; forming a first type doped semiconductor layer on the substrate; forming a light emitting layer on the surface of the first type doped semiconductor layer; And forming a second type doped semiconductor layer on the surface of the light emitting layer in a range and a predetermined temperature range, wherein the doped semiconductor layers are respectively an n-type doped gallium nitride (GaN) layer and a p-type doping a gallium nitride (GaN) layer, the predetermined gas pressure range being 300 to 700 mbar, the predetermined temperature range being 850 to 1200 degrees Celsius; and an etching is performed in the predetermined gas pressure range and the predetermined temperature range And a passivating gas is applied to the surface of the second type doped semiconductor layer for a predetermined time, and after the predetermined time is over, a repair gas is introduced, and the repair gas may be trimethylgallium (TMGa) gas or three Ethylene gallium (TEGa) or trimethyl indium (TMIn) to complete at least one relief structure of the surface of the second type doped semiconductor layer. The semiconductor surface roughening method according to claim 1, wherein the substrate is a sapphire substrate or a tantalum carbide substrate. The semiconductor surface roughening method according to claim 1, wherein the first type doped semiconductor layer is an n-type doped semiconductor layer, and the second type doped layer is a p-type doping Semiconductor layer. The semiconductor surface roughening method according to claim 1, wherein the first type doped semiconductor layer is a p-type doped semiconductor layer, and the second type doped layer is an n-type doping Semiconductor layer. The method of roughening a semiconductor surface according to claim 1, wherein the luminescent layer is a multi-quantum well structure layer. The semiconductor surface roughening method according to claim 1, wherein the etching gas is hydrogen (H ₂ ), and the passivating gas is ammonia (NH ₃ ) or nitrogen (N ₂ ), and the predetermined time range is 10 to 120 minutes. The semiconductor surface roughening method according to claim 1, wherein each of the uneven structures is a triangular pyramidal uneven structure having a height difference of as low as 200 to 800 nm. The semiconductor surface roughening method according to claim 1, wherein the second type doped semiconductor layer is formed by vapor deposition.