TWI408959B - Wireless communication receiver, tv receiver, and related method of sharing data storage module between deinterleaver and other circuit - Google Patents

Abstract

A wireless communication receiver includes a plurality of signal processing circuits, a data storage module, and a deinterleaver. The signal processing circuits includes a first signal processing circuit and a second signal processing circuit. The first signal processing circuit receives a wireless communication signal and then performs a first signal processing to generate a first output data according to the wireless communication signal. The deinterleaver stores the first output data into the data storage module, and retrieves a deinterleaved data corresponding to the first output signal from the data storage module. The second signal processing circuit performs a second signal processing to generate a second output data according to the deinterleaved data. The data storage module is shared by the deinterleaver and at least one of the signal processing circuits for data storage.

Description

Deinterleaver and other circuits share the data communication module wireless communication receiver, electricity View receiver and related methods

The present invention relates to wireless communication, and more particularly to a wireless communication receiver having a data storage module (such as a memory) shared by a deinterleaver and a signal processing circuit (such as an MPEG decoder, an H.264 decoder, or an AVS decoder). (eg digital television receivers) and related methods.

In recent years, orthogonal frequency division multiplexing (OFDM) technology has been widely used in wireless communication systems, such as digital television systems. Generally speaking, a digital television system is a television system that converts a television signal from a currently used analog signal into a digital signal. In other words, the digital television system processes digital signals and sounds after digital conversion and compression. , into a series of data streams, and these data streams are broadcast in the form of wireless communication, for the user side, through the digital television receiver for wireless signal reception and through appropriate signal processing (such as demodulation, deinterlacing And decoding, etc.) to extract the image and sound signals, and finally broadcast the channel content selected by the user via an output device (such as a television screen and a speaker).

The digital TV specifications currently used in the world vary by region. For example, the People's Republic of China currently has a custom digital TV specification. Regardless of which digital TV specification is used, digital television receivers are required to receive digital television signals. Please refer to FIG. 1 , which is a functional diagram of a conventional digital television receiver 100 . Block diagram. The digital television receiver 100 includes an antenna 102, a tuner 104, a demodulator 106, a backend decoder 108, and a plurality of memories 110, 112. The antenna 102 receives the digital television signal (which is an RF signal), and then the tuner 104 performs down-conversion and channel selection, and the demodulator 106 demodulates the output of the tuner 104 to extract the digital television signal. The transmitted bit stream, and finally, the back bit decoder 108 decodes the bit stream output by the demodulator 106 (eg, MPEG decoding, H.264 decoding, or AVS decoding) to generate an image/audio signal to subsequent Output devices (such as TV screens and speakers) play the channel content selected by the user. In general, the backend decoder 108 and the demodulator 106 are individually designed, and therefore are often disposed in different chips. Therefore, the demodulator 106 itself is configured with a dedicated memory 110. Similarly, the back end The decoder 108 itself will also be configured with a dedicated memory 112.

Generally, before transmitting the wireless communication signal, the transmitting end can break the original data through interleaving to reduce the influence of channel fading. Therefore, for digital television broadcasting, when the transmitting end has interleaving In the case of an interleaver, the digital television receiver 100 at the receiving end needs to have a corresponding deinterleave circuit. For example, for the digital television specification specified by the People's Republic of China, the interlace is used. Processed to break up the original data, but compared to other digital television specifications (such as DVB-T), for a convolutional interleaving circuit that meets the digital television specifications set by the People's Republic of China, all of the multiple interleaved branches The amount of data temporary storage of the shift register is large, which means that the deinterleaving circuit in the demodulator 106 needs a large storage space to complete Interleaved processing, so the memory space (such as memory 110) outside the wafer is often provided to provide the required storage space. Since memory 110 is only used by demodulator 106 (e.g., only for deinterleaving circuitry in demodulator 106) and memory 112 is only used by backend decoder 108, such a hardware configuration will result in memory being The flexibility in use is not good, and the production cost is limited by the configuration of the exclusive memory 110, 112 and cannot be effectively reduced.

Accordingly, it is an object of the present invention to provide a wireless communication receiver having a data storage module (eg, memory) shared by a deinterleaver and a signal processing circuit (eg, an MPEG decoder, an H.264 decoder, or an AVS decoder) (eg digital television receivers) and related methods.

In accordance with an embodiment of the present invention, a wireless communication receiver is disclosed. The wireless communication receiver comprises: a plurality of signal processing circuits, a data storage module and a deinterleaver. The plurality of signal processing circuits includes a first signal processing circuit and a second signal processing circuit. The first signal processing circuit receives a wireless communication signal and performs a first signal processing according to the wireless communication signal to generate a first output data. The deinterlacer is coupled to the first signal processing circuit and the data storage module for storing the first output data to the data storage module, and extracting the corresponding first from the data storage module One of the output data deinterlaces the data. The second signal processing circuit performs a second signal processing on the deinterleaved data to generate a second output data. At least one of the deinterleaver and the plurality of signal processing circuits The data storage module is shared to store data.

According to another embodiment of the present invention, a wireless communication receiving method is disclosed. The wireless communication receiving method includes: performing a first signal processing to receive a wireless communication signal, and generating a first output data according to the wireless communication signal; performing a deinterleaving process to store the first output data And a data storage module, and extracting, from the data storage module, a de-interlaced data corresponding to one of the first output data; and performing a second signal processing on the de-interlaced data to generate a second output data. The deinterlacing process shares the data storage module with at least one of the first and second signal processing to store data.

In accordance with another embodiment of the present invention, a wireless communication receiver is disclosed. The wireless communication receiver comprises: a data storage module, a memory bus, a deinterleaver and a plurality of signal processing circuits. The memory bus is connected to the data storage module. The deinterleaver is coupled to the data storage module for storing a first output data to the data storage module, and extracting, from the data storage module, a deinterlacing data corresponding to one of the first output data. The plurality of signal processing circuits include a first signal processing circuit and a second signal processing circuit, wherein the first signal processing circuit is coupled to the deinterleaver for receiving a wireless communication signal and based on the wireless communication signal Performing a first signal processing to generate the first output data, and the second signal processing circuit is coupled to the deinterleaver for performing a second signal processing according to the deinterleaved data to generate a second output data. And the at least one of the deinterleaver and the plurality of signal processing circuits are accessed through the memory bus Data storage module.

In accordance with another embodiment of the present invention, a television receiver is disclosed. The television receiver comprises: a data storage module, a demodulator and a back end decoder. The demodulator receives and demodulates a digital television signal to generate a bit stream, and includes: a first signal processing circuit for performing a first signal processing according to the digital television signal to generate a first output data a de-interlacer coupled to the first signal processing circuit and the data storage module for storing the first output data to the data storage module and extracting corresponding data from the data storage module One of the output data is deinterleaved; and an error correction decoding module is coupled to the deinterleaver for performing an error correction decoding process to generate the bit stream according to the deinterleaved data. The back end decoder is coupled to the demodulator for receiving and decoding the bit stream. The deinterleaver and the backend decoder share the data storage module to store data.

2 is a schematic diagram of a generalized architecture of a wireless communication receiver of the present invention. The wireless communication receiver 200 includes, but is not limited to, a first signal processing circuit 202, a deinterleaver 204, a second signal processing circuit 206, and a data storage module 208. As shown, the deinterleaver 204 The same data storage module 208 is shared with the second signal processing circuit 206 to store data. That is, the data storage module 208 is not a dedicated storage component of the deinterleaver 204, nor is it a dedicated storage of the second signal processing circuit 206. element. The first signal processing circuit 202 receives the wireless communication signal RF, and performs a first signal processing according to the wireless communication signal RF to generate the first output data D1 to Deinterleaver 204, then deinterleaver 204 stores the first output data D1 to the data storage module 208, and extracts the deinterlaced data DD corresponding to the first output data D1 from the data storage module 208, and finally, The second signal processing circuit 206 receives the deinterleaved data DD from the deinterleaver 204 and performs a second signal processing on the deinterleaved data DD to generate a second output data D2 to subsequent circuit elements (not shown). In an embodiment of the present invention, the wireless communication receiver 100 is a digital television receiver for receiving digital television signals transmitted by orthogonal frequency division multiplexing (OFDM) (for example, The digital communication standard (RF) of the digital television standard set by the People's Republic of China, and extracting the digital TV channel content (ie, the second output data D2) from the received digital television signal for subsequent output devices (such as a screen) And/or speaker) to play the channel content.

Please note that in the circuit architecture shown in FIG. 2, the deinterleaver 204 and the second signal processing circuit 206 (which is the back end circuit of the deinterleaver 204) share the same data storage module 208 to store data. However, this is for illustrative purposes only, and is not intended to limit the scope of the present invention. For example, without departing from the spirit of the shared data storage device 208 of the present invention, in other embodiments of the present invention, the deinterleaver 204 may also be used. The data storage module 208 is shared with the first signal processing circuit 202 (which is the front end circuit of the deinterleaver 204). This design change is also within the scope of the present invention.

2 is only a generalized architecture of the wireless communication receiver of the present invention, which is used to roughly explain the data storage module used by the deinterleaver for deinterleaving. Other circuit components are used in the wireless communication receiver, and in order to more clearly disclose the technical features of the present invention, a plurality of examples will be described below.

Please refer to FIG. 3, which is a functional block diagram of an embodiment of a wireless communication receiver of the present invention. In this embodiment, the wireless communication receiver 300 includes an antenna 302, a tuner 304, a demodulator 306, a back end decoder 308, a memory controller 310, and a memory 312. The wireless communication receiver 300 is an embodiment of the circuit architecture shown in FIG. 2. The antenna 302 is configured to receive a digital television signal, and then the tuner 304 performs down-conversion and channel selection, that is, the antenna 302 and the tuner. The 304 is used as a signal receiving circuit 305 for receiving a wireless communication signal (digital television signal), and generates a receiving signal to the demodulator 306. Then, the demodulator 306 demodulates the output of the tuner 304. The bit stream transmitted by the digital television signal is taken out, and finally, the bit stream output by the demodulator 306 is decoded by the back end decoder 308 (for example, MPEG decoding, H.264 decoding or AVS decoding) to generate an image/sound. The signal is sent to a subsequent output device (such as a screen and/or a speaker) to play the content of the digital TV channel selected by the user. In this embodiment, the data storage module 208 shown in FIG. 2 is implemented by the memory 312, and the deinterleaver 204 shown in FIG. 2 is represented by the deinterleaver in the demodulator 306 (not shown in the first 3, but will be described in detail later. In addition, as can be clearly seen from Fig. 2 and Fig. 3, antenna 302, tuner 304 and a part of demodulator 306 are clearly understood. The circuit (without deinterleaver) corresponds to the first signal processing module 202 shown in FIG. 2, and another portion of the circuit (without deinterleaver) and backend decoder 308 in the demodulator 306. Then, it corresponds to the second signal processing module 206 shown in FIG. In this embodiment, the solution The deinterleaver in the 306 and the backend decoder 308 share a memory 312, such as a dynamic random access memory (DRAM) or a synchronous dynamic random access memory (SDRAM), and when the solution in the demodulator 306 When the interleaver and backend decoder 308 issues a memory write request or a memory read request via the local bus 314, 315, respectively, the memory controller 310 arbitrates the deinterleaving in the demodulator 306. Or the backend decoder 308 obtains the access rights of the memory 312, and then the memory controller 310 writes the corresponding data to the memory 312 according to the memory write request or the memory read request. The read operation, while the memory controller 310 and the memory 312 transfer the memory address and data via a memory bus 316, in other words, the deinterleaver in the demodulator 306 The end decoder 308 shares the memory 312 through the same memory bus 316.

Please refer to FIG. 3 and FIG. 4 at the same time. FIG. 4 is a schematic diagram of the first embodiment of the demodulator 306 shown in FIG. In this embodiment, the demodulator 306-1 includes, but is not limited to, a signal conversion circuit 402, a carrier/timing synchronization circuit 404, a channel estimation/etc. Channel estimation/equalization circuit 406, an error vector generation & demapping circuit 408, a channel state information generation circuit 410, a multiplier 412, and a channel A deinterleaver 414, an error correction decoding module 415, and a descrambler 420. The tuner 304 shown in FIG. 3 generates a receiving signal S1 according to the wireless communication signal (ie, the digital television signal) received by the antenna 302, and the receiving signal S1 can be an intermediate frequency signal or The baseband signal, if the received signal S1 is an intermediate frequency signal, the demodulator 306 needs to additionally provide a frequency down circuit (not shown) to further down-convert the intermediate frequency signal into a baseband signal and input the signal to the signal conversion circuit. 402, for analog to digital conversion, on the other hand, if the received signal S1 is already a baseband signal, the received signal S1 generated by the tuner 304 is directly input to the signal conversion circuit 402 for analog to digital conversion. The carrier/timing synchronization circuit 404 synchronizes the receiving end with the transmitting end to correctly process the OFDM symbol transmitted via the wireless communication signal, and then the channel estimation/equalization circuit 406 performs channel estimation/etc. At this time, according to the output of the channel estimation/equalization circuit 406, the error vector generation and demapping circuit 408 generates an error measurement result EV to the channel state information generation circuit 410, and generates a demapping output S2 to A multiplier 412, wherein the demapping output S2 is a soft decision output having a plurality of soft decision bits. The channel state information generating circuit 410 can estimate the quality of the received symbol or bit by referring to the output of the channel estimation/equalization circuit 406 and/or the error measurement result EV, and accordingly generate a channel state information S3. The multiplier 412 generates the first output data D1 to the deinterleaver 414 according to the demapping output S2 and the channel state information S3. Note that the first output data D1 is still a soft decision output rather than a hard decision output. The deinterleaver 414 uses the memory 312 in FIG. 3 as the storage space required for performing the deinterleaving process. Therefore, the deinterleaver 414 accesses the memory 312 via the area bus 314. In this embodiment, The deinterleaver 414 stores the first output data D1 to the memory 312 via the area bus 314 and the memory controller 310 in FIG. 3, and then extracts one of the corresponding first output data D1 from the memory 312. Deinterlace data DD. Then the deinterlaced data DD needs to be performed. The error correction decoding process is used in the present embodiment to perform error correction decoding because the LDPC code is used as the inner code and the BCH code is used as the outer code. The processed error correction decoding module 415 includes an LDPC decoder 416 and a BCH decoder 418, wherein the deinterleaved data DD performs an inner code decoding process on the deinterleaved data DD via the LDPC decoder 416 to generate an LDPC decoded output DOUT_1. The LDPC decoding output DOUT_1 then performs a BCH decoding process via the BCH decoder 418 to generate a BCH decoding output DOUT_2. In general, the transmitting end uses a scrambler to perform a scrambling process on the data to avoid a long string of "0" or "1". Therefore, for the receiving end, in this implementation In the example, the demodulator 306-1 is provided with a corresponding descrambler 420 to perform a descrambling process on the BCH decoding output DOUT_2 output by the BCH decoder 418. Finally, the descrambler 420 outputs a The bit stream DOUT_3 is passed to a subsequent processing circuit (e.g., the rear end decoder 308 shown in FIG. 3).

In the embodiment shown in FIG. 4, the deinterleaver 414 deinterleaves the product of the demapping output S2 and the channel state information S3. However, the present invention is not limited thereto. Please refer to FIG. 5. FIG. 5 is a schematic diagram of a second embodiment of the demodulator 306 shown in FIG. In this embodiment, the demodulator 306-2 includes, but is not limited to, a signal conversion circuit 502, a carrier/timing synchronization circuit 504, a channel estimation/equalization circuit 506, an error vector generation circuit 508, and a Channel state information generating circuit 510, a deinterleaver 512, a demapping circuit 514, a multiplier 516, an error correction decoding module 517, and a descrambler 522, wherein the error correction decoding module 517 includes an LDPC decoding. And a BCH decoder 520. Figures 5 and 4 The main difference is that the channel estimation/equalization output S4 generated by the channel estimation/equalization circuit 506 and the channel state data S3 generated by the channel state data generation circuit 510 are individually input to the deinterleaver 512 for solution. Interleaving, at this time, the deinterleaver 512 stores the channel estimation/equalization output S4 and the channel state information S3 to the memory 312 via the area bus 314 and the memory controller 310 in FIG. 3, respectively. The de-interlaced data DD_1 and DD_2 corresponding to the channel estimation/equalization output S4 and the channel state information S3 are respectively extracted from the memory 312, that is, the first input data received by the deinterleaver 512 in this embodiment. The channel estimation/equalization output S4 and the channel state data S3 are included, and the deinterleaved data corresponding to the first input data output by the deinterleaver 512 includes the deinterleaved data DD1 and the deinterleaved data DD_2. As shown in FIG. 5, the deinterleaved data DD_1 is again processed by the demapping circuit 514 to produce a demapping output S2. The multiplier 516 then generates an output according to the de-mapping output S2 and the deinterleaved data DD_2 of the corresponding channel state information S3, and then sequentially corrects the output of the multiplier 516 via the LDPC decoder 518 and the BCH decoder 520. After the decoding process, and the descrambling process of the output of the BCH decoder 520 via the descrambler 522, output from the demodulator 306-2 to the subsequent circuit (e.g., the rear end decoder 308 shown in FIG. 3) The bit stream. Since the elements of the same name in FIG. 5 and FIG. 4 have the same or similar functions and operations, those skilled in the art should readily understand FIG. 5 after reading the above description of the embodiment shown in FIG. The operation and function of each component are not described here.

In the above embodiment, deinterleaver 414 (512) in demodulator 306-1 (306-2) The same memory 312 is shared with the backend decoder 308. Therefore, the present invention further provides a mechanism for elastically adjusting the storage space configuration in the memory 312. As previously mentioned, for the embodiment illustrated in Figure 4, the demapping output S2 is a soft decision output and includes a plurality of soft decision bits, as is known to those skilled in the art, each soft The decision bit itself is composed of a plurality of bits. Similarly, for the embodiment shown in FIG. 5, the channel estimation/equalization output S4 also includes a plurality of soft decision bits, in other words, this The deinterleaver 414, 512 disclosed by the invention mainly processes the soft decision output instead of the hard decision output, so that when the deinterleaver 414, 512 stores each soft decision bit to the memory 312, it can be selectively reduced. Each soft decision bit is stored in the number of bits of the memory 312, that is, by reducing the bit width of the soft decision bit written to the memory 312, thereby achieving a reduced solution. The interleaver 414, 512 is required for the storage space required for the deinterleaving process, so that the available storage space allocated to the backend decoder 308 in the memory 312 can be equivalently increased under the limited storage capacity of the memory 312. .

Fig. 6 is a schematic diagram showing the different memory space configurations corresponding to the memory 312 shown in Fig. 3. Assuming that under the first memory space configuration, the backend decoder 308 only needs to use the storage space B, and the storage space A configured to the deinterleaver 414, 512 can allow the deinterleaver 414, 512 to make each soft decision. The bits are completely stored in memory 312, however, when backend decoder 308 needs to use a larger storage space for some reason (e.g., backend decoder 308 adds additional functionality due to a change in design, Therefore, additional storage space is required, or the backend decoder 308 may need additional storage space temporarily during the execution of a specific decoding operation, and at this time, it is not changed. Under the total capacity of the memory 312, the second memory space configuration is enabled. As shown, the storage space A' is smaller than the storage space A, and the storage space B' is larger than the storage space B due to the memory. The storage space available to the deinterlacers 414, 512 in the volume 312 is reduced. Therefore, when the deinterleaver 414, 512 stores each soft decision bit to the memory 312, each soft decision bit is reduced. The number of bits into memory 312. For example, the data store operation of deinterleaver 414, 512 discards one bit in each soft decision bit, and for subsequent LDPC decoders 416, 518, each soft decision due to deinterlacing The bits are all missing one bit. Therefore, the present invention fills the vacant bits with "0" so that the LDPC decoder can perform the LDPC decoding operation. In other words, the present invention slightly sacrifices the receiver performance or hardly affects it. In the case of receiver performance, the bit width of the data written to the memory 312 is dynamically adjusted to optimize the use of the limited storage capacity of the memory 312, that is, the memory 312 can be compared to the prior art. Has greater flexibility in use.

In order to achieve the purpose of adjusting the bit width of the data written to the memory 312, the present invention uses a data buffer module coupled between the memory 312 and the deinterleaver 414, 512. Please refer to FIG. 7. FIG. 7 is a schematic diagram of a third embodiment of the demodulator 306 shown in FIG. The embodiment shown in FIG. 7 is similar to the embodiment shown in FIG. 4, but the main difference is that an additional buffer 702 is provided in the demodulator 306-4 of the embodiment. Between the deinterleaver 414 and the area bus 314, please note that the area buffer 702 and the deinterleaver 414 are disposed inside the same chip (ie, the demodulator chip), and the memory shown in FIG. Body 312 is disposed outside of the wafer. If the bit width of the first output data D1 (which is still a soft decision output) is M, and when the second memory configuration shown in FIG. 6 is enabled, the data storage operation of the deinterleaver 414 discards each N bits in a soft decision bit, that is, when each soft decision bit in the first output data D1 (having a total of M bits) is to be temporarily stored in the region buffer 702, only (MN A bit is written to the region buffer 702, after which the region buffer 702 outputs and writes to each of the soft decision bits having (MN) bits that are temporarily stored via the area bus 314. External memory 312.

In addition, the area buffer 702 can further perform a function of transport format conversion, that is, if the bit width of each soft decision bit in the first output data D1 is different from the bus width of the memory 312, the area buffer 702. Each soft decision bit in the first output data D1 is temporarily stored, and then the temporary data in the area buffer 702 is transferred to the memory 312 according to the bus width of the memory 312, in other words, the first output data. Each piece of data (ie, soft decision bit) in D1 has a first bit width, and each time between the area buffer 702 and the memory 312 is based on a second bit different from the first bit width. Width to pass data. Similarly, when the deinterleaver 414 wants to read the deinterleaved data from the memory 312, the memory 312 temporarily stores the deinterleaved data according to its bus width to the area buffer 702, and then the deinterleaver 414 re Each de-interlaced soft decision bit is read out in buffer 702.

Moreover, by the application of the area buffer 702, the number of reading and writing of the memory 312 can be reduced to improve the overall system performance. Please refer to Figure 8, Figure 8 shows Figure 7. A schematic diagram of one embodiment of a region buffer. In this embodiment, the area buffer 702 includes an input buffer 802 and an output buffer 804, wherein the input buffer 802 and the output buffer 804 respectively include a plurality of buffer units 806, and each buffer unit 806 has The same storage capacity, for example, the storage capacity of each buffer unit 806, can temporarily store 16 OFDM symbols. Since the deinterleaver 414 performs the wraparound deinterlacing, a plurality of deinterleaving branches 808 are applied to complete the wraparound deinterlacing. As shown in the figure, if there are Y deinterlacing branches, then (Y-1) A data buffer block 810 having a different buffer length is provided on the deinterleaving branch, which operates similarly to a shift register. For the input buffer 802, a buffer unit 806 is disposed on each deinterleaving branch 808. Similarly, for the output buffer 804, a buffer unit 806 is also disposed on each deinterleaving branch 808. When the data amount of the first output data D1 temporarily stored by the buffer unit 806 in the input buffer 802 reaches a predetermined value (for example, when the buffer unit 806 is full of data), the buffer unit 806 passes the corresponding deinterleaving branch. 808 continuously writes the temporarily stored data to the memory 312. In other words, when the data to be written into the memory 312 accumulated in the input buffer 802 reaches a certain amount of data, the memory 312 is performed. A data write operation. For the output buffer 804, the memory 312 continuously outputs the data to the corresponding buffer unit 806 of the output buffer 804 via the deinterleaving branch 808 until the amount of data temporarily stored by the buffer unit 806 reaches a predetermined value (for example, The buffer unit 806 has been filled with data. Thereafter, the deinterleaver 414 reads the deinterleaved data DD from the output buffer 804. In other words, in one data reading operation, the memory 312 continuously outputs data to the output. The buffer 804 until the data accumulated in the output buffer 804 to be output to the deinterleaver 414 reaches a certain amount of data. stop.

In general, the deinterleaving process requires frequent data reading and writing to the memory 312. However, the memory 312 is used by the backend decoder 308 in addition to being used by the deinterleaver 414, therefore, The frequent access of the deinterleaver 414 to the memory 312 affects the operation of the backend decoder 308. Furthermore, frequent access to the memory 312 can also cause overall system performance to be ineffective, so the present invention uses input. The arrangement of the buffer 802 and the output buffer 804 can greatly reduce the number of reading and writing of the memory 312, thereby reducing the impact of the memory access operation of the deinterleaver 414 on the operation of the backend decoder 308. The overall system performance can also be greatly improved.

In addition, for an LDPC decoder, it is decoded in units of blocks, for example, a block may contain a data amount of 7488 bits. Therefore, for each deinterleaved branch, the present invention is further used in a memory shared by a backend decoder (such as an MPEG decoder, an H.264 decoder, or an AVS decoder) and a deinterleaver in the demodulator. Understand the LDPC decoder in the modulator and configure additional buffer space so that the deinterleaver can input a large amount of deinterleaved data (even the amount of data corresponding to an entire block) to the memory when reading the data to the memory. The LDPC decoder, as shown in FIG. 9, the memory 312 includes a plurality of data buffer blocks 910 corresponding to the plurality of deinterleaved branches 808, respectively, compared to the memory 312 shown in FIG. In one embodiment, each deinterlacing branch 808 is additionally configured with a buffer space (as indicated by the slashed area in FIG. 9, please note that the additional configuration shown in FIG. 9 The size of the buffer space is only used as an example. In fact, the size of the buffer space for additional configuration can be adjusted according to different design requirements. Therefore, the buffer length of the plurality of data buffer blocks 910 in the memory 312 is greater than the plurality of solutions. The minimum buffer length required for the interleaving branch 808 to perform the wraparound deinterleaving process (i.e., the buffer length of the plurality of data buffer blocks 810 in FIG. 8). On the other hand, the conventional deinterleaver needs to write one symbol immediately after reading one symbol when accessing the memory. However, compared to the prior art, each deinterleaving branch 808 Each of the buffer spaces is configured. Therefore, when accessing the memory 312, it is not limited to write N symbols after reading N symbols, that is, the deinterleaver of the present invention operates. The admiral is more flexible.

Please note that in the embodiment shown in FIG. 9, the deinterleaver 414 is operated together with the memory 312 having an additional buffer space and the previously mentioned area buffer 702, and has the above operational advantages. However, this is for illustrative purposes only, and is not a limitation of the present invention. That is, in other embodiments, the deinterleaver 414 may also operate only with the memory 312 having additional buffer space in FIG. This is also within the scope of the invention.

Similarly, the area buffer can also be applied to the embodiment shown in FIG. 5, please refer to FIG. 10, and FIG. 10 is a schematic diagram of the fourth embodiment of the demodulator shown in FIG. The embodiment shown in FIG. 10 is similar to the embodiment shown in FIG. 5, but the main difference is that an area buffer 1002 is additionally provided in the demodulator 306-4 of the embodiment. Note that the area buffer The device 1002 and the deinterleaver 512 are disposed in the same crystal The memory 312 shown in FIG. 3 is disposed outside the chip, that is, inside the chip (ie, the demodulator chip). The functions and applications of the area buffer 1002 are as shown in the eighth and ninth embodiments. Since the related art is described in detail above, it will not be further described herein.

In summary, the wireless communication receiving method adopted by the wireless communication receiving receiver of the present invention can be summarized as follows. The wireless communication receiving method of the present invention comprises: performing a first signal processing to receive a wireless communication signal, and generating a first output data according to the wireless communication signal; performing a deinterleaving process to the first output data And storing a data storage module, and extracting, from the data storage module, one of the first output data to deinterleave the data; and performing a second signal processing on the deinterleaved data to generate a second output data. The deinterlacing process shares the data storage module with at least one of the first and second signal processing to store data. The wireless communication receiving method of the present invention can be applied to a digital television receiver (for example, a receiver conforming to the digital television specification prescribed by the People's Republic of China), and in addition, any digital television receiver uses the wireless communication receiving method of the present invention to deinterleaver It is within the scope of the present invention to share the same data storage module with other signal processing circuits for storing data.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100‧‧‧Digital television receiver

102, 302‧‧‧ antenna

104, 304‧‧‧ Tuner

106, 306, 306-1, 306-2, 306-3, 306-4‧‧ ‧ demodulator

108, 308‧‧‧ Backend decoder

110, 112, 312‧‧‧ memory

200, 300‧‧‧ wireless communication receiver

202‧‧‧First signal processing circuit

204, 414, 512‧‧ deinterlacer

206‧‧‧second signal processing circuit

208‧‧‧Data storage module

310‧‧‧ memory controller

314, 315‧‧‧ regional busbars

316‧‧‧ memory bus

402, 502‧‧‧ signal conversion circuit

404, 504‧‧‧ Carrier/Sequence Synchronization Circuit

406, 506‧‧‧ channel estimation/equalization circuits

408‧‧‧Error vector generation and demapping circuit

410, 510‧‧‧ channel status information generating circuit

412, 516‧‧‧ multiplier

416, 518‧‧‧LDPC decoder

418, 520‧‧‧BCH decoder

508‧‧‧ error vector generation circuit

702, 1002‧‧‧ area buffer

802‧‧‧ input buffer

804‧‧‧Output buffer

806‧‧‧buffer unit

808‧‧·Deinterlacing branches

810, 910‧‧‧ data buffer block

305‧‧‧Signal receiving circuit

415, 517‧‧‧ error correction decoding module

420, 522‧‧ ‧ descrambler

Figure 1 is a functional block diagram of a conventional digital television receiver.

2 is a schematic diagram of a generalized architecture of a wireless communication receiver of the present invention.

FIG. 3 is a functional block diagram of an embodiment of a wireless communication receiver of the present invention.

Figure 4 is a schematic diagram of a first embodiment of the demodulator shown in Figure 3.

Fig. 5 is a schematic view showing a second embodiment of the demodulator shown in Fig. 3.

Fig. 6 is a schematic diagram showing the different memory space configurations corresponding to the memory shown in Fig. 3.

Fig. 7 is a schematic view showing a third embodiment of the demodulator shown in Fig. 3.

Figure 8 is a schematic illustration of one embodiment of the area buffer shown in Figure 7.

Figure 9 is a schematic diagram of each of the de-interlacing branches additionally arranging a buffer space in the memory.

Fig. 10 is a view showing a fourth embodiment of the demodulator shown in Fig. 3.

300‧‧‧Wireless communication receiver

302‧‧‧Antenna

304‧‧‧Tuner

306‧‧‧ Demodulator

308‧‧‧Backend decoder

310‧‧‧ memory controller

312‧‧‧ memory

314, 315‧‧‧ regional busbars

316‧‧‧ memory bus

305‧‧‧Signal receiving circuit

Claims (33)

A wireless communication receiver includes: a data storage module; a deinterlacer coupled to the data storage module for storing a first output data to the data storage module and storing the data from the data storage module The module extracts one of the first output data to deinterleave the data, the first output data is a soft decision output; and the plurality of signal processing circuits include: a first signal processing circuit coupled to the solution The interleaver is configured to receive a wireless communication signal, and perform a first signal processing according to the wireless communication signal to generate the first output data; and a second signal processing circuit coupled to the deinterleaver for Deinterlacing the data to perform a second signal processing to generate a second output data; wherein the deinterleaver and the plurality of signal processing circuits share the data storage module to store data, and when the second When the output data needs to increase the storage space, the deinterleaver selectively reduces each of the soft decision bits in the first output data to the data storage module. Soft decision bits the number of bits stored in the data storage module. The wireless communication receiver of claim 1, wherein the wireless communication signal is an orthogonal frequency division multiplexing signal. The wireless communication receiver of claim 1, wherein the wireless communication signal is a digital television signal. The wireless communication receiver of claim 3, wherein the digital television signal conforms to the digital television specification set by the People's Republic of China. The wireless communication receiver of claim 1, wherein the deinterleaver and the second signal processing circuit share the data storage module, and the first signal processing circuit comprises: a signal receiving circuit, The channel is configured to receive a channel; And the demapping circuit, the channel state information generating circuit, and the deinterleaver, configured to generate the first output data to the deinterleaver according to the demapping output and the channel state information. The wireless communication receiver of claim 1, wherein the deinterleaver and the second signal processing circuit share the data storage module; the first signal processing circuit comprises: a signal receiving circuit, Receiving the wireless communication signal to generate a received signal, a channel estimation/equalization circuit for performing a channel estimation/equalization process according to the received signal to generate a channel estimation/equalization output, and a channel a status information generating circuit for generating a channel status information, wherein the first output signal includes the channel estimated/equalized output and the channel status information And the de-interlacer is coupled to the channel estimation/equalization circuit and the channel state information generation circuit for storing the channel estimation/equalization output and the channel state information to the data storage mode respectively And de-interlacing data corresponding to the channel estimation/equalization output and the channel status information respectively from the data storage module. The wireless communication receiver of claim 1, further comprising: a data buffer module coupled between the data storage module and the deinterleaver for buffering the temporary storage of the data storage module The data transmitted between the group and the deinterleaver; wherein the data buffer module and the deinterleaver are disposed in a chip, and the data storage module is disposed outside the chip. The wireless communication receiver of claim 7, wherein the data buffer module comprises: an input buffer, configured to store the temporarily stored data when the amount of temporarily stored data reaches a predetermined value. Continuously writing to the data storage module; and an output buffer for continuously storing data read from the data storage module until the amount of temporarily stored data reaches a predetermined value. The wireless communication receiver of claim 7, wherein the first output data corresponds to a first bit width, and the data buffer module and the data storage module are based on a second bit. The meta-width is used to pass the data, and the first bit width is different from the second bit width. The wireless communication receiver of claim 9, wherein the data corresponding to the first output data temporarily stored in the data buffer module has a third bit width, and the third bit width The system is smaller than the first bit width. The wireless communication receiver of claim 1, wherein the deinterleaver performs a cyclotron deinterleaving process; the data storage module includes a plurality of plurality of deinterlacing branches respectively corresponding to the plurality of deinterlacing branches The data buffer block; and the buffer length of the plurality of data buffer blocks is greater than a minimum buffer length required by the plurality of de-interlaced branches to perform the cyclotron de-interlacing process. A wireless communication receiving method includes: performing a first signal processing to receive a wireless communication signal, and generating a first output data according to the wireless communication signal, wherein the first output data is a soft decision output; a deinterlacing process for storing the first output data to a data storage module, and extracting, from the data storage module, a deinterlacing data corresponding to one of the first output data; and performing a The second signal processing is performed to generate a second output data; wherein the deinterleaving process shares the data storage module with at least one of the first and second signal processing to store data, and when the second output data needs to be increased When storing the space, each soft decision bit in the first output data is stored to the data During the storage module process, the number of bits of each soft decision bit stored in the data storage module is selectively reduced. The wireless communication receiving method according to claim 12, wherein the wireless communication signal is an orthogonal frequency division multiplexing signal. The wireless communication receiving method according to claim 12, wherein the wireless communication signal is a digital television signal. The method for receiving wireless communication according to claim 14, wherein the digital television signal conforms to the digital television specification set by the People's Republic of China. The wireless communication receiving method of claim 12, wherein the deinterlacing process shares the data storage module with the second signal processing, and the first signal processing includes: receiving the wireless communication signal to generate Receiving a signal; generating a demapping output according to the received signal; generating a channel status information; and generating the first output data according to a product of the demapping output and the channel status information. The wireless communication receiving method according to claim 12, wherein the deinterlacing processing system shares the data storage module with the second signal processing, and the The signal processing includes: receiving the wireless communication signal to generate a received signal, generating a channel status information, and performing channel estimation/equalization according to the received signal to generate a channel estimation/equalization output; the first output signal The channel estimation/equalization output and the channel status information are included; and the deinterlacing process stores the channel estimation/equalization output and the channel status information to the data storage module, respectively, and stores the data from the data storage module The module extracts the deinterlaced data corresponding to the channel estimation/equalization output and the channel status information. The wireless communication receiving method of claim 12, further comprising: providing a data buffer module, and using the data buffer module to buffer the temporary storage of the deinterlacing processing output to the data storage module The first output data and the deinterlaced data read from the data storage module; wherein the first output data corresponds to a first bit width, and the data buffer module and the data storage module are based on A second bit width is used to pass the data, and the first bit width is different from the second bit width. The wireless communication receiving method of claim 18, wherein the data corresponding to the first output data temporarily stored in the data buffer module has a third bit width, and the third bit width The system is smaller than the first bit width. The method for receiving wireless communication according to claim 12, wherein the deinterleaving process is a cyclotron deinterlacing process; the data storage module includes a plurality of data buffers corresponding to the plurality of deinterleaved branches respectively. Block; and the complex The buffer length of the plurality of data buffer blocks is greater than the minimum buffer length required for the complex de-interlacing branches to perform the cyclotron de-interlacing process. A wireless communication receiver includes: a data storage module; a memory bus bar connected to the data storage module; and a deinterleaver coupled to the data storage module for using a first output And storing data from the data storage module, and extracting, from the data storage module, one of the first output data, the first output data is a soft decision output; and the plurality of signal processing circuits, including The first signal processing circuit is coupled to the deinterleaver for receiving a wireless communication signal, and performing a first signal processing according to the wireless communication signal to generate the first output data; and a second signal The processing circuit is coupled to the deinterleaver for performing a second signal processing according to the deinterleaved data to generate a second output data, wherein at least one of the deinterleaver and the plurality of signal processing circuits Accessing the data storage module through the memory bus, and when the second output data needs to increase storage space, the deinterleaver stores each of the first output data Soft decision bits to the data storage module during each selectively reduce the number of bits of soft decision bits stored in the data storage module. The wireless communication receiver of claim 21, further comprising a memory controller for arbitrating at least one of the deinterleaver and the plurality of signal processing circuits to the memory bus Access rights. The wireless communication receiver of claim 21, further comprising: a data buffer module coupled between the data storage module and the deinterleaver for buffering the temporary storage of the data storage module Data transmitted between the group and the deinterleaver; wherein the first output data corresponds to a first bit width, the memory bus bar has a second bit width, and the first bit width is different In the second bit width. The wireless communication receiver of claim 23, wherein the data corresponding to the first output data temporarily stored in the data buffer module has a third bit width, and the third bit width The system is smaller than the first bit width. A television receiver includes: a data storage module; a demodulator for receiving and demodulating a digital television signal to generate a bit stream, the demodulator comprising: a first signal processing circuit, And performing a first signal processing according to the digital television signal to generate a first output data, where the first output data is a soft decision output; a de-interlacer coupled to the first signal processing circuit and the data storage module for storing the first output data to the data storage module and extracting the first corresponding data from the data storage module One of the output data is deinterleaved; an error correction decoding module is coupled to the deinterleaver for performing an error correction decoding process according to the deinterleaved data; and a descrambler coupled to the error correction a decoding module, configured to perform a descrambling process according to an output of the error correction decoding module to generate the bit stream; and a back end decoder coupled to the demodulator for receiving and decoding the bit a metadata stream; wherein the deinterleaver and the backend decoder share the data storage module to store data, and when the second output data needs to increase storage space, the deinterleaver stores the first output data Each of the soft decision bits to the data storage module process selectively reduces the number of bits of each soft decision bit stored in the data storage module. The television receiver of claim 25, wherein the first signal processing circuit comprises: a signal receiving circuit for receiving the digital television signal to generate a receiving signal; and a demapping circuit for Receiving a signal to generate a demapping output; a channel state information generating circuit for generating a channel state information; and a multiplier coupled to the demapping circuit, the channel state information generating circuit, and the deinterleaver, For outputting the channel status information according to the demapping The first output data is generated to the deinterleaver. The television receiver of claim 25, wherein the first signal processing circuit comprises: a signal receiving circuit for receiving the digital television signal to generate a received signal, a channel estimation/equalization circuit And performing a channel estimation/equalization process according to the received signal to generate a channel estimation/equalization output, and a channel state information generating circuit for generating a channel state information, wherein the first output signal includes Having the channel estimation/equalization output and the channel status information; and the deinterleaver is coupled to the channel estimation/equalization circuit and the channel state information generation circuit for estimating/equalizing the channel The output and the channel status information are respectively stored in the data storage module, and the de-interlaced data corresponding to the channel estimation/equalization output and the channel status information are extracted from the data storage module. The television receiver of claim 25, wherein the error correction decoding module comprises: an LDPC decoder coupled to the deinterleaver for performing an inner code decoding process according to the deinterleaved data; An LDPC decoding output is generated; and a BCH decoder is coupled to the LDPC decoder for performing a BCH decoding process according to the LDPC decoding output to generate a BCH decoding output, wherein the descrambler is the BCH The decoded output is subjected to the descrambling process to generate the bit stream. A television receiver according to claim 25, wherein the digital television The signal is in compliance with the digital television specifications set by the People's Republic of China. The television receiver of claim 25, further comprising: a data buffering module coupled between the data storage module and the deinterleaver for buffering the temporary storage of the data storage module And the data transmitted between the deinterleaver and the deinterleaver; wherein the data buffer module and the deinterleaver are disposed in a chip, and the data storage module is disposed outside the chip. The television receiver of claim 30, wherein the data buffer module comprises: an input buffer for continuously storing the temporarily stored data when the amount of temporarily stored data reaches a predetermined value; Writing to the data storage module; and an output buffer for continuously storing data read from the data storage module until the amount of temporarily stored data reaches a predetermined value. The television receiver of claim 30, wherein the first output data corresponds to a first bit width, and the data buffer module and the data storage module are based on a second bit The width is passed to the data, and the first bit width is different from the second bit width. The television receiver according to claim 30, wherein the data stored in the data buffer module corresponding to the first output data has a third bit Width, and the third bit width is less than the first bit width.