TWI408753B - Fabricating method of thin film transistor - Google Patents

Abstract

A fabricating method of thin film transistor including: forming a gate on a substrate; sequentially forming a gate insulator, an oxide semiconductor layer and an ultraviolet shielding material layer for covering the gate; forming a first patterned photoresist layer on the ultraviolet shielding material layer; patterning the oxide semiconductor layer and the ultraviolet shielding material layer to form an oxide channel layer by using the first patterned photoresist layer as a mask; forming a second photoresist layer by removing parts of the first photoresist layer, wherein parts of the ultraviolet shielding material layer is exposed by the second photoresist layer; patterning the ultraviolet shielding material layer to form an ultraviolet shielding pattern by using the second patterned photoresist layer as a mask; removing the second patterned photoresist layer; and forming a source and a drain electrically insulated from one another.

Description

Method for manufacturing thin film transistor

The present invention relates to a method of fabricating a thin film transistor, and more particularly to a method of fabricating a thin film transistor having an oxide channel layer and an ultraviolet light shielding pattern.

Recently, environmental awareness has risen, and flat display panels with low power consumption, good space utilization efficiency, no radiation, and high image quality have become mainstream in the market. Common flat panel displays include liquid crystal displays, plasma displays, electroluminescent displays, and the like. Taking the most popular liquid crystal display as an example, it is mainly composed of a thin film transistor array substrate, a color filter substrate, and a liquid crystal layer sandwiched therebetween. On a conventional thin film transistor array substrate, an amorphous germanium ( a- Si) thin film transistor or a low temperature polycrystalline germanium thin film transistor is often used as a switching element of each sub-pixel. In recent years, studies have shown that oxide semiconductor thin film transistors have higher carrier mobility than amorphous germanium thin film transistors, while oxide semiconductor thin films are lower than low temperature. The polycrystalline germanium film transistor has a better threshold hold voltage (Vth) uniformity. Therefore, oxide semiconductor thin film transistors have the potential to become key components of next-generation flat panel displays.

In a conventional oxide semiconductor thin film transistor, the threshold voltage (Vth) of the oxide channel layer is deflected by ultraviolet light (for example, a cleaning process), thereby affecting electrical characteristics of the oxide semiconductor thin film transistor. Therefore, it has been proposed in the prior art to use titanium oxide (TiOx) having an ultraviolet light shielding effect as a material of a gate insulating layer or a protective layer to avoid the problem of a threshold voltage shift of the oxide channel layer. The gate insulating layer or the protective layer is entirely covered on the thin film transistor array substrate. However, in a general polymer stabilization alignment (PSA) liquid crystal display panel, ultraviolet light is usually used to illuminate liquid crystal molecules to complete a liquid crystal alignment process, and the foregoing uses titanium oxide (TiOx) as a gate insulating layer or The design of the protective layer may cause the ultraviolet light used in the alignment process to not penetrate the thin film transistor array substrate, so that the monomer in the liquid crystal molecule cannot be polymerized into a high molecular polymer by ultraviolet light irradiation, resulting in a liquid crystal alignment process. failure.

The present invention provides a method of manufacturing a thin film transistor to produce a thin film transistor having an ultraviolet light shielding pattern.

The invention provides a method for manufacturing a thin film transistor, comprising: forming a gate on a substrate; sequentially forming a gate insulating layer, an oxide semiconductor layer and an ultraviolet shielding material layer on the substrate to cover the gate; above the gate Forming a first patterned photoresist layer on the ultraviolet shielding material layer; using the first patterned photoresist layer as a mask, patterning the oxide semiconductor layer and the ultraviolet shielding material layer to form under the ultraviolet shielding material layer An oxide channel layer; removing a portion of the first patterned photoresist layer to form a second patterned photoresist layer, wherein the second patterned photoresist layer exposes a portion of the ultraviolet light shielding material layer; and the second patterned photoresist layer The layer is a mask, and the ultraviolet light shielding material layer is patterned to form an ultraviolet light shielding pattern on a portion of the oxide channel layer; the second patterned photoresist layer is removed; and the oxide channel layer and the ultraviolet light shielding pattern are The source and the drain are electrically insulated from each other.

In an embodiment of the invention, the first patterned photoresist layer comprises a first portion and a second portion, the thickness of the first portion being greater than the thickness of the second portion, and the method of forming the second patterned photoresist layer comprises moving Except for the first portion and the second portion, until the second portion is completely removed, and the first portion that is not completely removed constitutes the second patterned photoresist layer.

In an embodiment of the invention, after forming the ultraviolet light shielding pattern and before removing the second patterned photoresist layer, further comprising processing the oxide channel layer not covered by the second patterned photoresist layer to The oxide channel layer not covered by the second patterned photoresist layer has the property of an ohmic contact layer.

In an embodiment of the invention, the method of removing a portion of the first patterned photoresist layer includes ashing.

In an embodiment of the invention, the material of the ultraviolet shielding material layer comprises titanium oxide (TiOx) or cerium-rich cerium oxide (Si-rich SiOx).

The present invention further provides a method for fabricating a thin film transistor, comprising: forming a gate on a substrate; sequentially forming a gate insulating layer, a first ultraviolet light shielding material layer, an oxide semiconductor layer, and a second ultraviolet light shielding material on the substrate; a layer to cover the gate; forming a first patterned photoresist layer on the second ultraviolet shielding material layer above the gate; patterning the second ultraviolet shielding material layer with the first patterned photoresist layer as a mask And an oxide semiconductor layer and a first ultraviolet light shielding material layer to form an oxide channel layer and a first ultraviolet light shielding pattern under the second ultraviolet light shielding material layer; and removing a portion of the first patterned photoresist layer to Forming a second patterned photoresist layer, wherein the second patterned photoresist layer exposes a portion of the second ultraviolet light shielding material layer; and the second patterned photoresist layer is used as a mask to pattern the second ultraviolet light shielding material layer, Forming a second ultraviolet light shielding pattern on a portion of the oxide channel layer; removing the second patterned photoresist layer; and forming mutual electricity on the oxide channel layer and the second ultraviolet light shielding pattern Source and drain insulation to the extreme poles.

In an embodiment of the invention, the first patterned photoresist layer comprises a first portion and a second portion, the thickness of the first portion being greater than the thickness of the second portion, and the method of forming the second patterned photoresist layer comprises moving Except for the first portion and the second portion, until the second portion is completely removed, and the first portion that is not completely removed constitutes the second patterned photoresist layer.

In an embodiment of the invention, after forming the second ultraviolet light shielding pattern and before removing the second patterned photoresist layer, further comprising processing the oxide channel layer not covered by the second patterned photoresist layer So that the oxide channel layer not covered by the second patterned photoresist layer has the characteristics of an ohmic contact layer.

In an embodiment of the invention, the method of removing a portion of the first patterned photoresist layer includes ashing.

In an embodiment of the invention, the material of the first ultraviolet shielding material layer comprises titanium oxide (TiOx) or cerium-rich cerium oxide (Si-rich SiOx).

In an embodiment of the invention, the material of the second ultraviolet shielding material layer comprises titanium oxide (TiOx) or cerium-rich cerium oxide (Si-rich SiOx).

The invention further provides a method for manufacturing a thin film transistor, comprising: forming a gate on a substrate; sequentially forming a gate insulating layer, an ultraviolet light shielding material layer, an oxide semiconductor layer and a conductive layer on the substrate to cover the gate; Forming a conductive layer, an oxide semiconductor layer, and an ultraviolet light shielding material layer to form an oxide channel layer and a first ultraviolet light shielding pattern under the conductive layer; forming a partial region of the conductive layer and a partial region of the gate insulating layer a source and a drain electrically insulated from each other; and a conductive layer not covered by the source and the drain to convert the conductive layer not covered by the source and the drain into an insulating second ultraviolet light shielding pattern .

In an embodiment of the invention, the aforementioned conductive layer comprises titanium (Ti), Zn, Sn or Zr.

In an embodiment of the invention, the material of the second ultraviolet light shielding pattern comprises titanium oxide (TiOx), ZnOx, SnOx or ZrOx.

In an embodiment of the invention, the material of the ultraviolet shielding material layer comprises titanium oxide (TiOx) or cerium-rich cerium oxide (Si-rich SiOx).

In one embodiment of the invention, a method of converting a conductive layer into an insulated second ultraviolet light shielding pattern comprises plasma oxidation or thermal oxidation.

The invention further provides a method for manufacturing a thin film transistor, comprising: forming a gate on a substrate; sequentially forming a gate insulating layer, an oxide semiconductor layer and a conductive layer on the substrate to cover the gate; patterning the conductive layer and oxidizing a semiconductor layer for forming an oxide channel layer under the conductive layer; forming a source and a drain electrically insulated from each other on a partial region of the conductive layer and a portion of the gate insulating layer; and a pair of sources and regions The highly covered conductive layer is processed to convert the conductive layer not covered by the source and the drain into an insulating ultraviolet light shielding pattern.

In an embodiment of the invention, the aforementioned conductive layer comprises titanium (Ti), Zn, Sn or Zr.

In an embodiment of the invention, the material of the ultraviolet light shielding pattern comprises titanium oxide (TiOx), ZnOx, SnOx or ZrOx.

In one embodiment of the invention, a method of converting a conductive layer into an insulating ultraviolet light shielding pattern includes plasma oxidation or thermal oxidation.

The invention forms an ultraviolet light shielding pattern above or below the oxide channel layer. Since the ultraviolet light shielding pattern is not completely covered on the substrate, the ultraviolet light shielding pattern does not cause the ultraviolet light to completely fail to penetrate the substrate.

The above described features and advantages of the present invention will be more apparent from the following description.

[First Embodiment]

1A to 1F are schematic views showing a manufacturing process of a thin film transistor according to a first embodiment of the present invention. Referring to FIG. 1A, first, a gate G is formed on the substrate 100. The material of the gate G is, for example, a metal or other conductive material. Next, a gate insulating layer GI, an oxide semiconductor layer 110, and an ultraviolet light shielding material layer 120 are sequentially formed on the substrate 100 to cover the gate G. In the present embodiment, the material of the gate insulating layer GI is, for example, a dielectric material such as yttrium oxide (SiOx), tantalum nitride (SiNx) or yttrium oxynitride (SiOxNy), and the material of the oxide semiconductor layer 110 is, for example, indium gallium oxide. A material such as zinc (Indium Gallium Zinc Oxide, IGZO), zinc oxide (ZnO), tin oxide (SnO) or tin dioxide (SnO 2 ), and the material of the ultraviolet shielding material layer 120 is, for example, titanium oxide (TiOx) or ruthenium. Cerium oxide (Si-rich SiOx). Since titanium oxide (TiOx) has good ultraviolet light shielding ability, those skilled in the art can appropriately change the refractive index and thickness of titanium oxide (TiOx) according to actual design requirements to obtain appropriate ultraviolet light shielding. effect. In the present embodiment, when the material of the ultraviolet shielding material layer 120 is Si-rich SiOx, we can also select an appropriate refractive index and thickness to make the cerium-rich cerium oxide (Si-rich SiOx). ) has an ultraviolet light shielding effect. For example, the refractive index of Si-rich SiOx is preferably from 1.5 to 2.9, and the thickness of Si-rich SiOx is preferably from 1000 angstroms to 3,000 angstroms.

It should be noted that in this embodiment, the ultraviolet shielding material layer 120 can be fabricated by using other materials having an ultraviolet shielding effect. The embodiment does not limit the material to be titanium oxide (TiOx) or cerium-rich cerium oxide (Si-rich). SiOx).

Referring to FIG. 1B, a first patterned photoresist layer 130 is formed on the ultraviolet shielding material layer 120 above the gate G. In the present embodiment, the first patterned photoresist layer 130 includes a first portion 132 and a second portion 134. The thickness of the first portion 132 is greater than the thickness of the second portion 134. The first patterned photoresist layer 130 is formed, for example, by a half-tone mask, a gray-tone mask, and a general exposure process. As can be seen from FIG. 1B, the first patterned photoresist layer 130 is located directly above the gate G, and the second portion 134 having a smaller thickness is distributed on both sides of the first portion 132 having a larger thickness, and the second portion 134 is A portion 132 is connected.

Referring to FIG. 1C, the first patterned photoresist layer 130 is used as a mask to pattern the oxide semiconductor layer 110 and the ultraviolet light shielding material layer 120 to form an oxide channel under the patterned ultraviolet light shielding material layer 120a. Layer 110a. As shown in FIG. 1C, the oxide semiconductor layer 110 and the ultraviolet light shielding material layer 120 not covered by the first patterned photoresist layer 130 are completely removed until the gate insulating layer GI is exposed. In the present embodiment, the manner of patterning the oxide semiconductor layer 110 and the ultraviolet light shielding material layer 120 is, for example, dry etching.

Referring to FIG. 1D, a portion of the first patterned photoresist layer 130 is removed to form a second patterned photoresist layer 140, wherein the second patterned photoresist layer 140 exposes a portion of the ultraviolet light shielding material layer 120a. In this embodiment, the method of forming the second patterned photoresist layer 140 is, for example, using an oxygen plasma ashing process to remove a portion of the first patterned photoresist layer 130 until the second portion 134 is The first portion 132 that is completely removed without being completely removed constitutes the second patterned photoresist layer 140.

Referring to FIG. 1E, the second patterned photoresist layer 140 is used as a mask to pattern the ultraviolet shielding material layer 120a to form an ultraviolet light shielding pattern 120b on a partial region of the oxide channel layer 110a. After forming the ultraviolet light shielding pattern 120b, the present embodiment can selectively process the oxide channel layer 110a not covered by the second patterned photoresist layer 140 so that the second patterned photoresist layer 140 is not patterned. The covered oxide channel layer 110a (marked at the slanted line) has the characteristics of an ohmic contact layer. For example, in this embodiment, the oxide channel layer 110a not covered by the second patterned photoresist layer 140 may be surface-treated with hydrogen plasma (H2 plasma) or argon plasma (Ar plasma) so that The oxide channel layer 110a covered by the second patterned photoresist layer 140 has the characteristics of an ohmic contact layer.

Referring to FIG. 1F, after the ultraviolet light shielding pattern 120b is completed, the second patterned photoresist layer 140 is removed. Thereafter, a source 150S and a drain 150D electrically insulated from each other are formed on the oxide channel layer 110a and the ultraviolet shielding pattern 120b. In this embodiment, the patterning process of the source 150S and the drain 150D is, for example, a wet etching process. As can be seen from FIG. 1F, since the source 150S, the drain 150D, and the ultraviolet shielding pattern 120b do not allow the oxide channel layer. 110a is exposed, so that the etchant used in the patterning process of the source 150S and the drain 150D does not damage the oxide channel layer 110a, so the electrical characteristics of the oxide channel layer 110a are more stable.

In the present embodiment, although the ultraviolet light shielding pattern 120b described above cannot completely shield the ultraviolet light incident on the oxide channel layer 110a, the ultraviolet light shielding pattern 120b can reduce the probability of ultraviolet light incident on the oxide channel layer 110a. Therefore, the ultraviolet light shielding pattern 120b still has a certain degree of help for the threshold voltage shift phenomenon of the oxide channel layer 110a.

[Second embodiment]

2A to 2F are schematic views showing a manufacturing process of a thin film transistor according to a second embodiment of the present invention. Referring to FIG. 2A, first, a gate G is formed on the substrate 100. The material of the gate G is, for example, a metal or other conductive material. Next, a gate insulating layer GI, an oxide semiconductor layer 110, and an ultraviolet light shielding material layer 120 are sequentially formed on the substrate 100 to cover the gate G. In the present embodiment, the material of the gate insulating layer GI is, for example, a dielectric material such as yttrium oxide (SiOx), tantalum nitride (SiNx) or yttrium oxynitride (SiOxNy), and the material of the oxide semiconductor layer 110 is, for example, indium gallium oxide. A material such as zinc (Indium Gallium Zinc Oxide, IGZO), zinc oxide (ZnO), tin oxide (SnO) or tin dioxide (SnO 2 ), and the material of the ultraviolet shielding material layer 120 is, for example, titanium oxide (TiOx) or ruthenium. Cerium oxide (Si-rich SiOx). Since titanium oxide (TiOx) has good ultraviolet light shielding ability, those skilled in the art can appropriately change the refractive index and thickness of titanium oxide (TiOx) according to actual design requirements to obtain appropriate ultraviolet light shielding. effect. In the present embodiment, when the material of the ultraviolet shielding material layer 120 is Si-rich SiOx, we can also select an appropriate refractive index and thickness to make the cerium-rich cerium oxide (Si-rich SiOx). ) has an ultraviolet light shielding effect. For example, the refractive index of Si-rich SiOx is preferably from 1.5 to 2.9, and the thickness of Si-rich SiOx is preferably from 1000 angstroms to 3,000 angstroms.

It should be noted that in this embodiment, the ultraviolet shielding material layer 120 can be fabricated by using other materials having an ultraviolet shielding effect. The embodiment does not limit the material to be titanium oxide (TiOx) or cerium-rich cerium oxide (Si-rich). SiOx).

Referring to FIG. 2B and FIG. 2C, a first patterned photoresist layer 130' is formed on the ultraviolet shielding material layer 120 above the gate G, as shown in FIG. 2B. Next, the first patterned photoresist layer 130' is used as a mask to pattern the oxide semiconductor layer 110 and the ultraviolet light shielding material layer 120 to form an oxide channel layer 110a under the patterned ultraviolet light shielding material layer 120a. . As shown in FIG. 2C, the oxide semiconductor layer 110 and the ultraviolet light shielding material layer 120 not covered by the first patterned photoresist layer 130 are completely removed until the gate insulating layer GI is exposed. In the present embodiment, the manner of patterning the oxide semiconductor layer 110 and the ultraviolet light shielding material layer 120 is, for example, dry etching.

Referring to FIG. 2D, a portion of the first patterned photoresist layer 130' is isotropically removed to form a second patterned photoresist layer 140, wherein the second patterned photoresist layer 140 exposes a portion of the ultraviolet light shielding material. Layer 120a. In this embodiment, the method of forming the second patterned photoresist layer 140 is, for example, reducing the thickness, length and width of the first patterned photoresist layer 130 ′ by using an oxygen plasma ashing process until a part of the ultraviolet light shielding material Layer 120a is exposed.

Referring to FIG. 2E, the second patterned photoresist layer 140 is used as a mask to pattern the ultraviolet shielding material layer 120a to form an ultraviolet light shielding pattern 120b on a partial region of the oxide channel layer 110a. After forming the ultraviolet light shielding pattern 120b, the present embodiment can selectively process the oxide channel layer 110a not covered by the second patterned photoresist layer 140 so that the second patterned photoresist layer 140 is not patterned. The covered oxide channel layer 110a (marked at the slanted line) has the characteristics of an ohmic contact layer. For example, in this embodiment, the oxide channel layer 110a not covered by the second patterned photoresist layer 140 may be surface-treated with hydrogen plasma or argon plasma so that the second patterned photoresist layer is not patterned. The oxide channel layer 110a covered by 140 has the characteristics of an ohmic contact layer.

Referring to FIG. 2F, after the ultraviolet light shielding pattern 120b is completed, the second patterned photoresist layer 140 is removed. Thereafter, a source 150S and a drain 150D electrically insulated from each other are formed on the oxide channel layer 110a and the ultraviolet shielding pattern 120b. In the present embodiment, the patterning process of the source 150S and the drain 150D is, for example, a wet etching process. As can be seen from FIG. 2F, since the source 150S, the drain 150D, and the ultraviolet shielding pattern 120b do not allow the oxide channel layer. Since 110a is exposed, the etchant used in the patterning process of the source 150S and the drain 150D does not damage the oxide channel layer 110a, so the electrical characteristics of the oxide channel layer 110a are more stable.

[Third embodiment]

3A to 3F are schematic views showing a manufacturing process of a thin film transistor according to a third embodiment of the present invention. Referring to FIG. 3A, first, a gate G is formed on the substrate 100, and the material of the gate G is, for example, metal. Next, a gate insulating layer GI, a first ultraviolet light shielding material layer 120', an oxide semiconductor layer 110, and a second ultraviolet light shielding material layer 120 are sequentially formed on the substrate 100. In the present embodiment, the material of the gate insulating layer GI is, for example, a dielectric material such as yttrium oxide (SiOx), tantalum nitride (SiNx) or yttrium oxynitride (SiOxNy), and the material of the oxide semiconductor layer 110 is, for example, indium gallium oxide. A material such as zinc (Indium Gallium Zinc Oxide, IGZO), zinc oxide (ZnO), tin oxide (SnO) or tin dioxide (SnO 2 ), and the material of the ultraviolet shielding material layer 120 is, for example, titanium oxide (TiOx) or ruthenium. Cerium oxide (Si-rich SiOx). Since titanium oxide (TiOx) has good ultraviolet light shielding ability, those skilled in the art can appropriately change the refractive index and thickness of titanium oxide (TiOx) according to actual design requirements to obtain appropriate ultraviolet light shielding. effect. In this embodiment, when the material of the first ultraviolet shielding material layer 120' and the second ultraviolet shielding material layer 120 is Si-rich SiOx, we can also select an appropriate refractive index and thickness. In order to make the cerium-rich cerium oxide (Si-rich SiOx) have an ultraviolet light shielding effect. For example, the refractive index of Si-rich SiOx is preferably from 1.5 to 2.9, and the thickness of Si-rich SiOx is preferably from 1000 angstroms to 3,000 angstroms.

It should be noted that, in this embodiment, the first ultraviolet light shielding material layer 120 ′ and the second ultraviolet light shielding material layer 120 may be fabricated by using other materials having an ultraviolet light shielding effect, and the material of the embodiment is not limited to titanium oxide. (TiOx) or yttrium-rich yttrium oxide (Si-rich SiOx).

Referring to FIG. 3B, a first patterned photoresist layer 130 is formed on the second ultraviolet shielding material layer 120 above the gate G. In the present embodiment, the first patterned photoresist layer 130 includes a first portion 132 and a second portion 134 having a thickness greater than a thickness of the second portion 134. The first patterned photoresist layer 130 is formed, for example, by a half-tone mask, a gray-tone mask, and a general exposure process. As can be seen from FIG. 1B, the first patterned photoresist layer 130 is located directly above the gate G, and the second portion 134 having a smaller thickness is distributed on both sides of the first portion 132 having a larger thickness, and the second portion 134 is A portion 132 is connected.

Referring to FIG. 3C, the first patterned photoresist layer 130 is used as a mask to pattern the first ultraviolet shielding material layer 120', the oxide semiconductor layer 110, and the second ultraviolet shielding material layer 120 to be patterned. An oxide channel layer 110a and an ultraviolet light shielding pattern 120a' are formed under the ultraviolet light shielding material layer 120a. As shown in FIG. 3C, the first ultraviolet light shielding material layer 120', the oxide semiconductor layer 110, and the second ultraviolet light shielding material layer 120 not covered by the first patterned photoresist layer 130 are completely removed until The gate insulating layer GI is exposed. In the present embodiment, the manner of patterning the first ultraviolet light shielding material layer 120', the oxide semiconductor layer 110, and the second ultraviolet light shielding material layer 120 is, for example, dry etching.

Referring to FIG. 3D, a portion of the first patterned photoresist layer 130 is removed to form a second patterned photoresist layer 140, wherein the second patterned photoresist layer 140 exposes a portion of the ultraviolet light shielding material layer 120a. In this embodiment, the method of forming the second patterned photoresist layer 140 is, for example, using the oxygen plasma ashing process to remove a portion of the first patterned photoresist layer 130 until the second portion 134 is completely removed. The first portion 132 that is not completely removed then constitutes the second patterned photoresist layer 140.

Referring to FIG. 3E, the second patterned photoresist layer 140 is used as a mask to pattern the ultraviolet shielding material layer 120a to form an ultraviolet light shielding pattern 120b on a partial region of the oxide channel layer 110a. After forming the ultraviolet light shielding pattern 120b, the present embodiment can selectively process the oxide channel layer 110a not covered by the second patterned photoresist layer 140 so that the second patterned photoresist layer 140 is not patterned. The covered oxide channel layer 110a (marked at the slanted line) has the characteristics of an ohmic contact layer. For example, in this embodiment, the oxide channel layer 110a not covered by the second patterned photoresist layer 140 may be surface-treated with hydrogen plasma (H2 plasma) or argon plasma (Ar plasma) so that The oxide channel layer 110a covered by the second patterned photoresist layer 140 has the characteristics of an ohmic contact layer.

Referring to FIG. 3F, after the ultraviolet light shielding pattern 120b is completed, the second patterned photoresist layer 140 is removed. Thereafter, a source 150S and a drain 150D electrically insulated from each other are formed on the oxide channel layer 110a and the ultraviolet shielding pattern 120b. In the present embodiment, the patterning process of the source 150S and the drain 150D is, for example, a wet etching process. As can be seen from FIG. 3F, since the source 150S, the drain 150D, and the ultraviolet shielding pattern 120b do not allow the oxide channel layer. Since 110a is exposed, the etchant used in the patterning process of the source 150S and the drain 150D does not damage the oxide channel layer 110a, so the electrical characteristics of the oxide channel layer 110a are more stable.

In the embodiment, the ultraviolet light shielding pattern 120b and the ultraviolet light shielding pattern 120a' cannot completely shield the ultraviolet light incident on the oxide channel layer 110a, but the ultraviolet light shielding pattern 120b and the ultraviolet light shielding pattern 120a' can be reduced. The probability of ultraviolet light incident on the oxide channel layer 110a. Therefore, the ultraviolet light shielding pattern 120b and the ultraviolet light shielding pattern 120a' still have a certain degree of help for the threshold voltage shift phenomenon of the oxide channel layer 110a.

Fourth Embodiment

4A to 4F are schematic views showing a manufacturing process of a thin film transistor according to a fourth embodiment of the present invention. Referring to FIG. 4A to FIG. 4F, the manufacturing method of the thin film transistor of the present embodiment is similar to that of the third embodiment, but the main difference between the two is that the first patterned photoresist layer 130 and the second pattern of this embodiment are different. The structure and manufacturing method (Figs. 4B to 4D) of the photoresist layer 140 are the same as those of the second embodiment (Figs. 2B to 2D).

[Fifth Embodiment]

5A to 5D are schematic views showing a manufacturing process of a thin film transistor according to a fifth embodiment of the present invention. Referring to FIG. 5A, first, a gate G is formed on the substrate 100, and the material of the gate G is, for example, metal. Next, a gate insulating layer GI, an ultraviolet light shielding material layer 120, an oxide semiconductor layer 110, and a conductive layer C are sequentially formed on the substrate 100 to cover the gate G. In the present embodiment, the material of the gate insulating layer GI is, for example, a dielectric material such as yttrium oxide (SiOx), tantalum nitride (SiNx) or yttrium oxynitride (SiOxNy), and the material of the oxide semiconductor layer 110 is, for example, indium gallium oxide. A material such as zinc (Indium Gallium Zinc Oxide, IGZO), zinc oxide (ZnO), tin oxide (SnO) or tin dioxide (SnO 2 ), and the material of the ultraviolet shielding material layer 120 is, for example, titanium oxide (TiOx) or ruthenium. Cerium oxide (Si-rich SiOx). Since titanium oxide (TiOx) has good ultraviolet light shielding ability, those skilled in the art can appropriately change the refractive index and thickness of titanium oxide (TiOx) according to actual design requirements to obtain appropriate ultraviolet light shielding. effect. In the present embodiment, when the material of the ultraviolet shielding material layer 120 is Si-rich SiOx, we can also select an appropriate refractive index and thickness to make the cerium-rich cerium oxide (Si-rich SiOx). ) has an ultraviolet light shielding effect. For example, the refractive index of Si-rich SiOx is preferably from 1.5 to 2.9, and the thickness of Si-rich SiOx is preferably from 1000 angstroms to 3,000 angstroms.

It should be noted that in this embodiment, the ultraviolet shielding material layer 120 can be fabricated by using other materials having an ultraviolet shielding effect. The embodiment does not limit the material to be titanium oxide (TiOx) or cerium-rich cerium oxide (Si-rich). SiOx).

Referring to FIG. 5B, the conductive layer C, the oxide semiconductor layer 110, and the ultraviolet shielding material layer 120 are patterned to form an oxide channel layer 110a and a first ultraviolet light shielding pattern under the patterned conductive layer C. 120b.

Referring to FIG. 5C, after the oxide channel layer 110a and the ultraviolet light shielding pattern 120b are completed, the source 150S and the drain 150D electrically insulated from each other are formed on a partial region of the conductive layer C and a partial region of the gate insulating layer GI. In the present embodiment, the patterning process of the source 150S and the drain 150D is, for example, a wet etching process. As can be seen from FIG. 5C, since the source 150S, the drain 150D, and the conductive layer C do not expose the oxide channel layer 110a. Therefore, the etchant used in the patterning process of the source 150S and the drain 150D does not damage the oxide channel layer 110a, so the electrical characteristics of the oxide channel layer 110a are more stable.

Next, referring to FIG. 5D, the conductive layer C not covered by the source 150S and the drain 150D is processed to convert the conductive layer C not covered by the source 150S and the drain 150D into an insulating property. Two ultraviolet light shielding patterns 120a'. In the present embodiment, the method of converting the conductive layer C into the insulating second ultraviolet light shielding pattern 120a' includes plasma oxidation or thermal oxidation. Further, the material of the conductive layer C is, for example, titanium (Ti), Zn, Sn or Zr. It should be noted that, in this embodiment, the material of the conductive layer C used in the foregoing embodiment is not limited to titanium (Ti), Zn, Sn or Zr, and other conductive materials which are converted into an insulating material and have an ultraviolet shielding effect after being properly treated. Materials can be used in this embodiment.

[Sixth embodiment]

6A to 6D are schematic views showing a manufacturing process of a thin film transistor according to a sixth embodiment of the present invention. Referring to FIG. 6A to FIG. 6D , this embodiment is similar to the fifth embodiment, but the main difference between the two is that the manufacturing method of the thin film transistor of the embodiment omits the ultraviolet shielding material layer 120 and the first ultraviolet light. The production of the mask pattern 120b.

Since the foregoing embodiment of the present invention integrates the fabrication of the ultraviolet light shielding pattern into the fabrication process of the oxide channel layer, the process proposed by the present invention is compatible with the existing process without causing an excessive cost burden. In addition, the foregoing embodiments of the present invention can produce a patterned ultraviolet light shielding pattern to moderately shield ultraviolet light, and the distribution of the ultraviolet light shielding pattern does not cause ultraviolet light to completely penetrate the substrate.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100. . . Substrate

GI. . . Brake insulation

110. . . Oxide semiconductor layer

110a. . . Oxide channel layer

120, 120a, 120’. . . UV shielding material layer

120b, 120a’. . . UV shielding pattern

130, 130’. . . First patterned photoresist layer

132. . . first part

134. . . the second part

140. . . Second patterned photoresist layer

150S. . . Source

150D. . . Bungee

C. . . Conductive layer

1A to 1F are schematic views showing a manufacturing process of a thin film transistor according to a first embodiment of the present invention.

2A to 2F are schematic views showing a manufacturing process of a thin film transistor according to a second embodiment of the present invention.

3A to 3F are schematic views showing a manufacturing process of a thin film transistor according to a third embodiment of the present invention.

4A to 4F are schematic views showing a manufacturing process of a thin film transistor according to a fourth embodiment of the present invention.

5A to 5D are schematic views showing a manufacturing process of a thin film transistor according to a fifth embodiment of the present invention.

6A to 6D are schematic views showing a manufacturing process of a thin film transistor according to a sixth embodiment of the present invention.

100. . . Substrate

GI. . . Brake insulation

110a. . . Oxide channel layer

120b. . . UV shielding pattern

150S. . . Source

150D. . . Bungee

Claims (21)

A method for manufacturing a thin film transistor, comprising: forming a gate on a substrate; forming a gate insulating layer, an oxide semiconductor layer and an ultraviolet shielding material layer on the substrate to cover the gate; Forming a first patterned photoresist layer on the ultraviolet shielding material layer above the gate; patterning the oxide semiconductor layer and the ultraviolet shielding material layer by using the first patterned photoresist layer as a mask Forming an oxide channel layer under the ultraviolet shielding material layer; removing a portion of the first patterned photoresist layer to form a second patterned photoresist layer, wherein the second patterned photoresist layer is exposed Forming a portion of the ultraviolet light shielding material layer; using the second patterned photoresist layer as a mask, patterning the ultraviolet light shielding material layer to form an ultraviolet light shielding pattern on a portion of the oxide channel layer, and The ultraviolet light shielding pattern corresponds to the center of the gate electrode; the second patterned photoresist layer is removed; and one source and one of the electrical insulation layers are electrically formed on the oxide channel layer and the ultraviolet light shielding pattern pole. The method for fabricating a thin film transistor according to claim 1, wherein the first patterned photoresist layer comprises a first portion and a second portion, the first portion having a thickness greater than a thickness of the second portion, and The method of forming the second patterned photoresist layer includes removing the first portion and the second portion until the second portion is completely removed, and the first portion not completely removed constitutes the second patterned light Resistance layer. The method for fabricating a thin film transistor according to claim 1, wherein after the ultraviolet light shielding pattern is formed and before the second patterned photoresist layer is removed, the second patterned light is further included The oxide channel layer covered by the resist layer is processed such that the oxide channel layer not covered by the second patterned photoresist layer has the characteristics of an ohmic contact layer. The method of manufacturing a thin film transistor according to claim 1, wherein the method of removing a portion of the first patterned photoresist layer comprises ashing. The method for producing a thin film transistor according to claim 1, wherein the material of the ultraviolet shielding material layer comprises titanium oxide (TiOx) or cerium-rich cerium oxide (Si-rich SiOx). A method for manufacturing a thin film transistor includes: forming a gate on a substrate; sequentially forming a gate insulating layer, a first ultraviolet light shielding material layer, an oxide semiconductor layer, and a second ultraviolet light on the substrate a layer of light shielding material to cover the gate; forming a first patterned photoresist layer on the second ultraviolet shielding material layer above the gate; using the first patterned photoresist layer as a mask, a pattern The second ultraviolet light shielding material layer, the oxide semiconductor layer and the first ultraviolet light shielding material layer are formed to form an oxide channel layer and a first ultraviolet light shielding layer under the second ultraviolet light shielding material layer a portion of the first patterned photoresist layer to form a second patterned photoresist layer, wherein the second patterned photoresist layer exposes a portion of the second ultraviolet light shielding material layer; Using the second patterned photoresist layer as a mask, patterning the second ultraviolet shielding material layer to form a second ultraviolet light shielding pattern on a portion of the oxide channel layer; removing the second pattern Forming a photoresist layer; and forming a source and a drain electrically insulated from each other on the oxide channel layer and the second ultraviolet light shielding pattern. The method of manufacturing a thin film transistor according to claim 6, wherein the first patterned photoresist layer comprises a first portion and a second portion, the first portion having a thickness greater than a thickness of the second portion, and The method of forming the second patterned photoresist layer includes removing the first portion and the second portion until the second portion is completely removed, and the first portion not completely removed constitutes the second patterned light Resistance layer. The method of manufacturing a thin film transistor according to claim 6, wherein after the forming the second ultraviolet light shielding pattern and before removing the second patterned photoresist layer, the pair is further included in the second pattern The oxide channel layer covered by the photoresist layer is processed such that the oxide channel layer not covered by the second patterned photoresist layer has the characteristics of an ohmic contact layer. The method of manufacturing a thin film transistor according to claim 6, wherein the method of removing a portion of the first patterned photoresist layer comprises ashing. The method for manufacturing a thin film transistor according to claim 6, wherein the material of the first ultraviolet shielding material layer comprises titanium oxide (TiOx) or cerium-rich cerium oxide (Si-rich SiOx). The method for manufacturing a thin film transistor according to claim 6, wherein the material of the second ultraviolet shielding material layer comprises titanium oxide. (TiOx) or yttrium-rich yttrium oxide (Si-rich SiOx). A method for manufacturing a thin film transistor includes: forming a gate on a substrate; sequentially forming a gate insulating layer, an ultraviolet light shielding material layer, an oxide semiconductor layer, and a conductive layer on the substrate to cover Forming the conductive layer, the oxide semiconductor layer and the ultraviolet shielding material layer to form an oxide channel layer and a first ultraviolet light shielding pattern under the conductive layer; a portion of the region and a portion of the gate insulating layer are electrically insulated from one source and one drain; and the conductive layer not covered by the source and the drain is processed so as not to be The conductive layer covered by the pole and the drain is converted into one of the second ultraviolet light shielding patterns. The method of producing a thin film transistor according to claim 12, wherein the conductive layer comprises titanium (Ti), Zn, Sn or Zr. The method for manufacturing a thin film transistor according to claim 13, wherein the material of the second ultraviolet light shielding pattern comprises titanium oxide (TiOx), ZnOx, SnOx or ZrOx. The method for producing a thin film transistor according to claim 12, wherein the material of the ultraviolet shielding material layer comprises titanium oxide (TiOx) or cerium-rich cerium oxide (Si-rich SiOx). The method of manufacturing a thin film transistor according to claim 12, wherein the method of converting the conductive layer into the insulating second ultraviolet light shielding pattern comprises plasma oxidation or thermal oxidation. A method of manufacturing a thin film transistor, comprising: Forming a gate on a substrate; sequentially forming a gate insulating layer, an oxide semiconductor layer and a conductive layer on the substrate to cover the gate; patterning the conductive layer and the oxide semiconductor layer to Forming an oxide channel layer under the conductive layer; forming a source and a drain electrically insulated from each other on a portion of the conductive layer and a portion of the gate insulating layer; and not being the source The conductive layer covered with the drain is processed to convert the conductive layer not covered by the source and the drain into an insulating ultraviolet shielding pattern. The method of producing a thin film transistor according to claim 17, wherein the conductive layer comprises titanium (Ti), Zn, Sn or Zr. The method for producing a thin film transistor according to claim 17, wherein the material of the ultraviolet light shielding pattern comprises titanium oxide (TiOx), ZnOx, SnOx or ZrOx. The method of manufacturing a thin film transistor according to claim 17, wherein the method of converting the conductive layer into the insulating ultraviolet light shielding pattern comprises plasma oxidation or thermal oxidation. A method for manufacturing a thin film transistor, comprising: forming a gate on a substrate; forming a gate insulating layer, an oxide semiconductor layer and an ultraviolet shielding material layer on the substrate to cover the gate; Forming a first patterned photoresist layer on the ultraviolet shielding material layer above the gate, wherein the first patterned photoresist layer comprises a first portion and a second portion, the first portion having a thickness greater than the first portion Two parts thick And the second portion is distributed on both sides of the first portion; the first patterned photoresist layer is used as a mask, and the oxide semiconductor layer and the ultraviolet shielding material layer are patterned to shield the ultraviolet light Forming an oxide channel layer under the material layer; removing a portion of the first patterned photoresist layer to form a second patterned photoresist layer, and the method of forming the second patterned photoresist layer includes removing the first a portion and the second portion until the second portion is completely removed, and the first portion not completely removed constitutes the second patterned photoresist layer, wherein the second patterned photoresist layer exposes a portion a layer of the ultraviolet shielding material; the second patterned photoresist layer is used as a mask, and the ultraviolet shielding material layer is patterned to form an ultraviolet shielding pattern on a portion of the oxide channel layer, and the ultraviolet light The shielding pattern corresponds to a center of the gate; removing the second patterned photoresist layer; and forming a source and a drain electrically insulated from each other on the oxide channel layer and the ultraviolet shielding pattern.