TWI407549B - Phase change memory - Google Patents

Abstract

A phase change memory is provided, which includes a semiconductor substrate having a first conductive type, buried word lines having a second conductive type, doped semiconductor layers having the first conductive type, memory cells, metal silicide layers, and bit lines. The buried word lines are disposed in the semiconductor substrate. Each buried word line includes a line-shaped main portion extended along a first direction and protrusion portions. Each protrusion portion is connected to one long side of the line-shaped main portion. Each doped semiconductor layer is disposed on one protrusion portion. Each memory cell includes a phase change material layer and is disposed on and electrically connected to one of the doped semiconductor layers. Each metal silicide layer is disposed on one of the line-shaped main portions. Each bit line is connected to memory cells disposed on the word lines in a second direction substantially perpendicular to the first direction.

Description

Phase change memory

The present invention relates to a memory, and more particularly to a phase change memory.

As semiconductor technology continues to evolve and evolve, the process of memory components is also moving toward physical limits. Among them, phase change memory (PCM) has the advantages of small size, low power consumption, fast reading and writing speed and high capacity density, and is one of the most popular non-volatile memory components.

In general, phase change memory is a chalcogen compound (Ge-Sb-Te) as a storage medium. The chalcogenide compound has a change in the amorphous phase and the crystalline phase under different annealing temperatures, and the two crystal phases have different resistance values, so The high-resistance amorphous phase and the low-resistance crystalline phase can be used as a memory to store digital data of "0" and "1". In particular, the change in the two crystal phases of the chalcogen compound is reversible, so that the phase change memory can be repeatedly programmed, read, erased, and the like.

In a conventional diode phase change memory, a plurality of memory cells are disposed on a buried word line, and a deuterated metal layer is formed on a buried word line between the memory cell and the memory cell. In other words, the deuterated metal layer on the word line is discontinuous. Therefore, when a current flows from a memory cell to a signal transmission contact point, the transmission path includes the passed through the deuterated metal layer. a substrate below the plurality of memory cells. Since the resistance of the deuterated metal layer is much smaller than the resistance of the substrate, the impedance difference between the transmission paths between the memory cells on the same word line and the signal transmission contact point is large, resulting in reading of individual memory cells on the same word line. When writing, a large current and voltage difference is generated due to the difference in impedance of the transmission path, so that the information written in the individual memory cells is incorrect, or the information in the individual memory cells is misjudged.

The invention provides a phase change memory capable of reducing a current-voltage difference between a memory cell and a memory cell on a same word line.

The invention provides a phase change memory comprising a semiconductor substrate, a plurality of embedded word lines, a plurality of doped semiconductor layers, a plurality of memory cells, a plurality of first deuterated metal layers, and a plurality of bit lines. The semiconductor substrate has a first conductivity type. A plurality of embedded word lines are disposed in the semiconductor substrate and have a second conductivity type. The embedded word line includes a strip body and a plurality of protrusions. The strip body extends in the first direction. The protruding portion is connected to one of the long sides of the strip body. The doped semiconductor layer is disposed on the protruding portion and has a first conductivity type. The memory cell includes a phase change material layer, and the memory cell is disposed on the doped semiconductor layer and electrically connected to the doped semiconductor layer. The first deuterated metal layer is disposed on the strip body. The bit line connections are distributed over a plurality of memory cells on a plurality of word lines substantially perpendicular to the first direction.

In an embodiment of the invention, the protruding portion is located on the same long side of the strip-shaped body.

In an embodiment of the invention, the protruding portion includes a plurality of first protruding portions and a plurality of second protruding portions, and the first protruding portion is located at one of the strip-shaped main bodies On the long side, the second protrusion is located on the other long side of the strip body.

In an embodiment of the invention, the first conductivity type is an N type, and the second conductivity type is a P type.

In an embodiment of the invention, the first conductivity type is a P type, and the second conductivity type is an N type.

In an embodiment of the invention, the material of the phase change material layer comprises a chalcogen compound.

In an embodiment of the invention, the phase change memory further includes a spacer, and the spacer is disposed on a sidewall of the doped semiconductor layer.

In an embodiment of the invention, the material of the spacer is made of tantalum oxide or tantalum nitride.

In an embodiment of the invention, the phase change memory further includes a second deuterated metal layer disposed between the doped semiconductor layer and the memory cell.

In an embodiment of the invention, the memory cell further includes a first electrode, and the first electrode is disposed between the doped semiconductor layer and the phase change material layer.

In an embodiment of the invention, the material of the first electrode comprises a metal or a metal nitride.

In an embodiment of the invention, the memory cell further includes a second electrode disposed between the phase change material layer and the bit line.

In an embodiment of the invention, the material of the second electrode comprises a metal or a metal nitride.

In an embodiment of the invention, the material of the doped semiconductor layer comprises doped polysilicon, doped single crystal germanium or doped epitaxial germanium.

In the phase change memory of the present invention, the embedded word line includes a strip-shaped body and a plurality of protrusions connected to the strip-shaped body, the memory cells are disposed on the protrusions, and the deuterated metal layer is disposed on the strip-shaped body. That is, a continuous deuterated metal layer connects each of the memory cells on the same word line. In this way, the voltage difference between the memory cell and the memory cell on the same word line can be reduced.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

1A is a top plan view of a phase change memory according to an embodiment of the present invention, and FIG. 1B is a cross-sectional view taken along line I-I' of FIG. 1A. It is to be noted that for the sake of clarity, only the word line 110, the first deuterated metal layer 140, and the bit line 150 are illustrated in FIG. 1A, and the arrangement of the word line 110 and the bit line 150 is omitted. The semiconductor layer 120, the spacers 122, the second deuterated metal layer 124, the memory cells 130, and the plugs 152 are doped.

Referring to FIG. 1A and FIG. 1B simultaneously, the phase change memory 10 includes a semiconductor substrate 100, a plurality of embedded word lines 110, a plurality of doped semiconductor layers 120, a plurality of memory cells 130, and a plurality of first deuterated metal layers. 140 and a plurality of bit lines 150. In this embodiment, the phase change memory 10 further includes a dielectric layer 160, such as yttrium oxide, tantalum nitride, tantalum carbide, hafnium oxynitride, low dielectric material, porous dielectric material, and other suitable materials. Dielectric material or a combination of the above.

In the present embodiment, the semiconductor substrate 100 has a first conductivity type, For example, it is a base. The semiconductor substrate 100 includes an isolation structure 102 and a buried word line 110. The isolation structure 102 is disposed between the embedded word lines 110 and is made of, for example, hafnium oxide, tantalum nitride or other suitable dielectric material. The buried word line 110 is formed of a semiconductor substrate 100 ion-implanted or doped with a second conductivity type dopant, so that the buried word line 110 has a second conductivity type. The embedded word line 110 includes a strip body 112 and a plurality of protrusions 114a, 114b. The strip body 112 extends in the first direction. The protruding portions 114a and 114b are connected to one of the long sides of the strip main body 112. In the present embodiment, the protruding portion 114a is located, for example, on one long side of the strip-shaped main body 112, and the protruding portion 114b is located on the other long side of the strip-shaped main body 112, for example. Further, the protruding portion 114a and the protruding portion 114b are, for example, arranged in a staggered manner. Of course, in other embodiments, as shown in FIGS. 2 to 4, the protrusions may have other configurations. It is to be noted that, for clarity of the drawing, only the word line 110, the first deuterated metal layer 140, and the bit line 150 are shown in FIGS. 2, 3, and 4, and the word line 110 and the bit are omitted. The doped semiconductor layer 120, the spacers 122, the second deuterated metal layer 124, the memory cells 130, and the plugs 152 are between the lines 150. Referring to FIG. 2, in the phase change memory 10a, the protruding portion 114a and the protruding portion 114b may not be connected to the strip body 112 in an arbitrary arrangement unlike the staggered configuration illustrated in FIG. 1A. In addition, referring to FIG. 3 and FIG. 4, in the phase change memory 10b, 10c, the protruding portion 114 of the one-character line 110 may be located on the same long side of the strip-shaped body 112. In other words, in the phase change memory of the present invention, the configuration of each word line may be different or the same, that is, it is well known to those skilled in the art that the number, size, and arrangement of the protrusions of the word line are Can be The design needs are adjusted to be different.

1A and 1B, the doped semiconductor layer 120 is disposed on the protruding portions 114a, 114b. The doped semiconductor layer 120 has a first conductivity type, the material of which is, for example, ion implanted or doped with a polycrystalline germanium, single crystal germanium or epitaxial germanium. In the present embodiment, the phase change memory 10 further includes a plurality of spacers 122. The spacers 122 are disposed on sidewalls of the doped semiconductor layer 120 to insulate the doped semiconductor layer 120 from the first deuterated metal layer 140. The material of the spacers 122 is, for example, tantalum oxide, tantalum nitride or other suitable dielectric material. In addition, in the embodiment, the doped semiconductor layer 120 is further provided with a second deuterated metal layer 124. The material of the second deuterated metal layer 124 is, for example, titanium telluride (TiSi ₂ ), cobalt telluride (CoSi ₂ ), tungsten germanium (WSi ₂ ), nickel germanium (NiSi ₂ ) or other suitable metal telluride material.

In the present embodiment, the substrate 100 is P-type, the buried word line 110 is N-type, and the doped semiconductor layer 120 is P-type. Of course, in another embodiment, the substrate 100 is N-type, the buried word line 110 is P-type, and the doped semiconductor layer 120 is N-type. Therefore, the substrate 100, the buried word line 110 located in the substrate 100, and the doped semiconductor layer 120 on the buried word line 110 together form a vertical bi-carrier-connected transistor, which can increase the device density. Helps to form high-density memory.

Referring to FIG. 1A and FIG. 1B , the memory cell 130 is disposed on the doped semiconductor layer 120 and electrically connected to the doped semiconductor layer 120 . The memory cell 130 includes a first electrode 132, a phase change material layer 134, and a second electrode 136. The material of the first electrode 132 is a material that does not react with the phase change material layer 134, such as tungsten, titanium nitride, titanium aluminum nitride, other metals or metal nitride or other suitable conductive material. The first electrode 132 is here a heater for the phase change material layer 134, but in other embodiments (not shown), the first electrode 132 may be different in size and shape and the first electrode 132 and the phase change material layer A heater composed of a conductive material may be disposed between 134 to heat the phase change material layer 134. Moreover, since the contact area between the heater and the phase change material layer 134 affects the heating efficiency, a spacer may be provided above the heater or a spacer may be provided around the heater to reduce the contact of the phase change material layer 134 with the heater. Area (not shown). The material of the phase change material layer 134 is, for example, a chalcogenide. The chalcogenide compound may be a binary material layer, a ternary material layer or a multi-material material layer. Wherein the binary material layer material, for example indium antimonide (the InSb), gallium antimonide (GaSb), indium selenide (an InSe), antimony telluride (Sb ₂ Te _3), antimony or germanium (of GeTe); three yuan The material of the material layer is, for example, germanium telluride (Ge ₂ Sb ₂ Te ₅ ), germanium indium telluride (InSbTe), germanium gallium telluride (GaSbTe), germanium telluride (SnSbTe ₄ ) or germanium telluride (InSbGe). The material of the multi-material layer is, for example, AgInSbTe, (Ge, Sn) SbTe, GeSb (SeTe) or Te ₈₁ Ge ₁₅ Sb ₂ S ₂ . The material of the second electrode 136 is a material that does not react with the phase change material layer 134, such as titanium nitride, titanium aluminum nitride, metal nitride or other suitable conductive material. It should be noted that the memory cell structure of this embodiment is only one of a plurality of phase change memory cells, and is mainly for explaining the phase change memory of the present invention in detail, so that the person skilled in the art can implement the method. However, it is not intended to limit the scope of the invention, in other words, the memory cell can be any phase change memory cell known to those of ordinary skill in the art. Moreover, since the phase change memory of the present invention may be integrated into the manufacturing process of logic elements (such as resistors, capacitors, transistors, etc.), as long as the purpose of heating the phase change material layer 134 is achieved, Other material layers not shown in the drawings may exist on the upper or lower side or the upper and lower sides of one electrode 132 and the second electrode 136.

In the embodiment, the first deuterated metal layer 140 is disposed on the strip body 112. In other words, on the buried word line 110, the first deuterated metal layer 140 is disposed except for the portion where the doped semiconductor layer 120 and the spacer 122 are disposed. That is, the first deuterated metal layer 140 is continuously formed on the strip-shaped body 112 of the embedded word line 110. In this way, when a current flows from a memory cell 130 to a signal transmission contact point (not shown), the transmission path may be a continuous first deuterated metal layer 140. Therefore, the difference in impedance between the memory cells 130 on the same word line 110 and the signal transmission contact point is small to reduce the current-voltage difference between the memory cell 130 and the memory cell 130. The material of the first vaporized metal layer 140 is, for example, titanium telluride (TiSi ₂ ), cobalt telluride (CoSi ₂ ), tungsten germanium (WSi ₂ ), nickel germanium (NiSi ₂ ) or other suitable metal halide material. In addition, in an embodiment, the first deuterated metal layer may also be disposed on the strip body and the protrusion according to the arrangement of the doped semiconductor layer.

A plurality of bit lines 150 are disposed on the plurality of memory cells 130 to connect the memory cells 130 in a second direction substantially perpendicular to the first direction. In the present embodiment, the bit line 150 is connected to the memory cell 130 by, for example, the plug 152. In the present embodiment, the material of the bit line is, for example, polysilicon, metal, metallization or other suitable conductive material, and the material of the plug 152 is, for example, copper, tungsten, metal nitride or a combination thereof.

In summary, in the phase change memory of the present invention, the embedded word line includes a strip-shaped body and a plurality of protrusions connected to the strip-shaped body, the memory cells are disposed on the protrusions, and the deuterated metal layer is disposed on the protrusions On the strip body. That is, a continuous deuterated metal layer connects each of the memory cells on the same word line. In this way, the difference in impedance between the memory cells on the same word line and the signal transmission contact point is small to reduce the voltage difference between the memory cell and the memory cell.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope is subject to the definition of the scope of the patent application attached.

10, 10a, 10b, 10c‧‧‧ phase change memory

100‧‧‧Base

102‧‧‧Isolation structure

110‧‧‧ character line

112‧‧‧Article body

114, 114a, 114b‧‧‧ protruding parts

120‧‧‧Doped semiconductor layer

122‧‧‧ spacer

124‧‧‧Deuterated metal layer

130‧‧‧ memory cells

132‧‧‧First electrode

134‧‧‧ phase change material layer

136‧‧‧second electrode

140‧‧‧Chemical metal layer

150‧‧‧ bit line

152‧‧‧ plug

160‧‧‧ dielectric layer

1A is a top plan view of a phase change memory in accordance with an embodiment of the present invention.

Fig. 1B is a schematic cross-sectional view taken along line I-I' of Fig. 1A.

2 is a top plan view of a phase change memory in accordance with another embodiment of the present invention.

3 is a top plan view of a phase change memory in accordance with still another embodiment of the present invention.

4 is a top plan view of a phase change memory in accordance with still another embodiment of the present invention.

10‧‧‧ phase change memory

100‧‧‧Base

102‧‧‧Isolation structure

110‧‧‧ character line

112‧‧‧Article body

114a‧‧‧Protruding

120‧‧‧Doped semiconductor layer

122‧‧‧ spacer

124‧‧‧Deuterated metal layer

130‧‧‧ memory cells

132‧‧‧First electrode

134‧‧‧ phase change material layer

136‧‧‧second electrode

140‧‧‧Chemical metal layer

150‧‧‧ bit line

152‧‧‧ plug

160‧‧‧ dielectric layer

Claims (14)

A phase change memory comprising: a semiconductor substrate having a first conductivity type; a plurality of embedded word lines disposed in the semiconductor substrate, having a second conductivity type, and each of the buried word lines includes a strip-shaped body extending in a first direction; and a plurality of protrusions, wherein each of the protrusions is connected to one of the long sides of the strip-shaped body; a plurality of doped semiconductor layers, wherein each of the doped semiconductor layers is disposed On a protrusion, having a first conductivity type; a plurality of memory cells, wherein each of the memory cells comprises a phase change material layer, and each of the memory cells is disposed on a doped semiconductor layer and electrically connected to the doped semiconductor layer a plurality of first deuterated metal layers, wherein each of the first deuterated metal layers is disposed on the strip body; and a plurality of bit lines, wherein each of the bit line connections are substantially perpendicular to the first direction The memory cells on the word lines in the second direction. The phase change memory of claim 1, wherein the protrusions are located on the same long side of the strip body. The phase change memory of claim 1, wherein the protrusions comprise a plurality of first protrusions and a plurality of second protrusions, the first protrusions being located on a long side of the strip body On the side, the second protrusions are located on the other long side of the strip body. The phase change memory of claim 1, wherein the phase change memory of claim 1 The first conductivity type is an N type, and the second conductivity type is a P type. The phase change memory of claim 1, wherein the first conductivity type is a P type, and the second conductivity type is an N type. The phase change memory of claim 1, wherein the material of the phase change material layer comprises a chalcogen compound. The phase change memory of claim 1, further comprising a plurality of spacers, each of the spacers being disposed on a sidewall of the doped semiconductor layer. The phase change memory of claim 7, wherein the material of each of the spacers comprises ruthenium oxide or tantalum nitride. The phase change memory of claim 1, further comprising a plurality of second deuterated metal layers, each of the second deuterated metal layers being disposed between the doped semiconductor layer and the memory cell. The phase change memory of claim 1, wherein each of the memory cells further comprises a first electrode disposed between the doped semiconductor layer and the phase change material layer. The phase change memory of claim 10, wherein the material of the first electrode comprises a metal or a metal nitride. The phase change memory of claim 10, wherein each of the memory cells further comprises a second electrode disposed between the phase change material layer and the bit line. The phase change memory of claim 12, wherein the material of the second electrode comprises a metal or a metal nitride. The phase change memory of claim 1, wherein the material of the doped semiconductor layer comprises doped polysilicon, doped single crystal germanium or doped epitaxial germanium.