TWI405992B - Test equipment, test method, computer program and electronic component for self-diagnosis of open circuit test or short circuit test related to functional test of test element - Google Patents

Abstract

The topic of the present invention is to carry out the open-circuit test by using less constitution. It is to provide a testing apparatus used to test the element to be tested, and which includes: power source portion, which is to supply the power source voltage to the power-source input terminal of the element to be tested; the signal supply portion, which is to supply the test signal to the signal terminal of element to be tested; the detection portion, which is to detect the electric current flowing from the signal supply portion through the protection diode in the element to be tested towards the power-source input terminal under the state in which the power-source voltage lower than the voltage supplied to the signal terminal is supplied to the power-source input terminal, wherein the protection diode of the element to be tested is used to make the over-voltage inputted to the signal terminal flow towards the power-source input terminal; and the open-circuit judging portion, which is to judge that the open circuit between the signal supply portion and the signal terminal is not on under the occasion of detecting the electric current flowing from the signal terminal towards the power-source input terminal.

Description

Test device, test method, computer program product, and electronic component for self-diagnosis for performing open circuit test or short circuit test related to functional test of test element

The present invention relates to a test device, a test method, a computer program product, and an electronic component for performing self-diagnosis for performing an open circuit test or a short circuit test related to a functional test of a device to be tested.

A simple memory tester is known which uses a general-purpose interface circuit for a memory controller as a driver comparator. In such a simple memory tester, the voltage level of the driver and the comparison level of the comparator are fixed, and although the accuracy and function are limited, the cost can be reduced.

Preferably, however, the memory tester performs a test on whether the wiring between the device under test and the memory tester becomes an open circuit (open circuit test) and the component under test before performing the functional test. Whether the wiring between the memory tester and the memory tester is short-circuited to a power supply or grounding test (short-circuit test). However, in order to carry out the open circuit test and the short circuit test, the memory tester must additionally have a DC test unit and a relay for connection switching, which causes a cost increase.

In order to solve the above problems, in one aspect of the present invention, a test apparatus for testing a component to be tested is provided, comprising: a power supply unit that supplies a power supply voltage to a power input terminal of the device under test a signal supply unit that supplies a test signal to a signal terminal of the device under test, and a detection unit that supplies a power supply voltage lower than a voltage supplied to the signal terminal to the power supply input terminal And detecting a current flowing from the signal supply unit through the protective diode in the device under test to the power input terminal, and the protective diode in the device to be tested is used to input the The overvoltage of the signal terminal flows toward the power supply input terminal. Further, test methods, programs, and interface circuits associated with such test devices are provided.

Further, the above summary of the invention does not recite all of the essential features of the invention. Moreover, sub-combinations of these feature groups can also be an invention.

Hereinafter, the present invention will be described by way of embodiments of the invention, but the following embodiments are not intended to limit the scope of the invention. Moreover, not all combinations of features described in the embodiments are necessary means for the invention.

Fig. 1 is a view showing the configuration of the test apparatus 10 of the present embodiment and the member to be tested 20. The test device 10 is used to test the component under test 20.

More specifically, the test apparatus 10 performs a functional test of the member to be tested 20. Further, before the functional test, the test apparatus 10 is first subjected to a test (open circuit test) between the test device 10 and the signal terminal 24 of the device under test 20, and a signal terminal of the device under test 20 24 Is it shorted to the test of power supply, grounding, or other terminals (short circuit test). Further, the signal terminal 24 of the device under test 20 may be either an input terminal, an output terminal, or an input/output terminal.

The test apparatus 10 includes a power supply unit 32, a pattern generation unit 34, a signal supply unit 36, a signal reception unit 38, a signal acquisition unit 40, a switching unit 42, a logic comparison unit 44, a detection unit 46, an open circuit determination unit 52, and a short circuit. The determination unit 54 and the function test unit 56.

The power supply unit 32 supplies a power supply voltage to the power supply input terminal 22 of the device under test 20 . The pattern generating unit 34 generates a logical value of a test signal to be supplied to the device under test 20. Further, the pattern generating unit 34 generates an expected value of an output signal to be output from the device under test 20.

The signal supply unit 36 generates a test signal corresponding to the voltage of the logic value generated by the pattern generating unit 34. Then, the signal supply unit 36 supplies a test signal to the signal terminal 24 of the device under test 20. The signal supply unit 36 may be a driver as an example.

The signal receiving unit 38 receives an output signal output from the signal terminal 24 of the device under test 20 from the wiring between the signal supply unit 36 and the signal terminal 24. The signal receiving unit 38 may be a level comparator as an example.

The signal acquisition unit 40 acquires the logical value of the output signal output by the signal receiving unit 38 at the acquisition timing specified for the output signal. The signal acquisition unit 40 may be a flip-flop as an example.

When the device under test 20 is a source synchronous device, the signal acquisition unit 40 acquires a logical value at a timing synchronized with the clock signal output from the device under test 20. Further, when the device under test is to output a clock embedded signal, the signal acquisition unit 40 acquires a logical value at a timing synchronized with the clock signal reproduced by the output signal.

The switching unit 42 switches the logic value obtained by the signal acquisition unit 40 to the logic comparison unit 44, or bypasses the signal acquisition unit 40 to give the logic value output by the signal reception unit 38 to the logic. Comparison unit 44. In the function test, the switching unit 42 supplies the logical value acquired by the signal acquisition unit 40 to the logical comparison unit 44. In the short-circuit test, the switching unit 42 bypasses the signal acquisition unit 40 and supplies the logical value of the output signal output from the signal reception unit 38 to the logic comparison unit 44.

In the function test, the logic comparison unit 44 compares the logical value of the output signal obtained by the signal acquisition unit 40 at the acquisition timing with the expected value generated by the pattern generation unit 34. Then, the logical comparison unit 44 gives the comparison result to the function test unit 56 realized by the control unit 50.

Further, in the short-circuit test, the logical value of the test signal output from the signal supply unit 36 is taken as an expected value, and is supplied to the logical comparison unit 44. In the short-circuit test, the logic comparison unit 44 compares the logical value of the test signal outputted by the signal supply unit 36 with the logical value output by the signal receiving unit 38 which is bypassed by the signal acquisition unit 40. . Then, the logical comparison unit 44 gives the comparison result to the short-circuit determination unit 54 realized by the control unit 50.

In the open circuit test, the detection unit 46 detects that the power supply voltage lower than the voltage supplied to the signal terminal 24 is supplied to the power supply input terminal 22, and the detection can be performed from the signal supply unit 36. The protective diode in the device 20 flows toward the power input terminal 22, and the protective diode in the device under test 20 is used to make the overvoltage input to the signal terminal 24 toward the power input terminal 22. flow.

As an example, the detection unit 46 detects that the power source voltage lower than the voltage supplied to the signal terminal 24 is supplied to the power source input terminal 22, and detects that it can flow from the power source input terminal 22 toward the power source unit 32. Current. Thereby, the detecting unit 46 can detect the current that can flow from the signal supply unit 36 toward the power supply input terminal 22. Then, the detection unit 46 gives the detection result to the open circuit determination unit 52 realized by the control unit 50.

The control unit 50 is, for example, a processor for controlling the test device. The control unit 50 functions as the open circuit determination unit 52 by executing the program for the open circuit test. Further, the control unit 50 functions as the short-circuit determination unit 54 by executing a program for the short-circuit test. Further, the control unit 50 functions as the function determining unit 56 by executing a program for the function test.

In the open circuit test, the open circuit determination unit 52 realized by the control unit 50 controls the pattern generation unit 34 and the power supply unit 32 to supply a power supply voltage lower than the voltage supplied to the signal terminal 24 to the power supply input terminal. State of 22. Then, the open circuit determination unit 52 receives the detection result from the detection unit 46, and determines the signal supply unit 36 and the signal terminal 24 when detecting a current that can flow from the signal terminal 24 toward the power supply input terminal 22. It is not an open circuit. Further, when the current that can flow from the signal terminal 24 toward the power supply input terminal 22 is not detected, the open circuit determination unit 52 determines that the signal supply unit 36 and the signal terminal 24 are open.

In the short-circuit test, the short-circuit determination unit 54 implemented by the control unit 50 controls the power supply unit 32, the pattern generation unit 34, and the switching unit 42, and does not output the output signal from the device under test 20, A test signal of a predetermined logical value is output from the signal supply unit 36. Further, the short circuit determination unit 54 bypasses the signal acquisition unit 40 and supplies the logic value output from the signal reception unit 38 to the logic comparison unit 44, and signals the signal between the signal supply unit 36 and the signal terminal 24. The logical value and the logical value of the test signal output from the signal supply unit 36 are compared.

Then, the short-circuit determination unit 54 is based on the logical value of the signal between the signal supply unit 36 and the signal terminal 24 received by the signal receiving unit 38 in a state where the output signal is not output from the device under test 20, and The result of the comparison of the logical values of the test signals outputted from the signal supply unit 36 determines whether or not the wiring between the signal supply unit 36 and the signal terminal 24 is short-circuited to other wiring.

The short-circuit determination unit 54 determines that the logical value of the signal between the signal supply unit 36 and the signal terminal 24 and the logical value of the test signal output by the signal supply unit 36 match each other as an example. . Further, as an example, when the logical value of the signal between the signal supply unit 36 and the signal terminal 24 and the logical value of the test signal outputted by the signal supply unit 36 do not match, the short-circuit determination unit 54 determines that Short circuit.

Further, as an example, the short-circuit determination unit 54 can output a test signal whose logic value is changed from the signal supply unit 36 to the signal terminal 24 at a predetermined timing. In this case, the short circuit determination unit 54 compares the logical value of the signal between the signal supply unit 36 and the signal terminal 24 and the output by the signal supply unit 36 before and after the predetermined timing in the logic comparison unit 44. The logical value of the test signal. Then, the short circuit determination unit 54 determines the signal supply unit 36 based on the comparison between the logical value of the signal between the signal supply unit 36 and the signal terminal 24 and the logical value of the test signal output from the signal supply unit 36. The connection state of the wiring between the signal terminal 24 and the signal terminal 24.

In the function test, the function test unit 56 realized by the control unit 50 controls the pattern generating unit 34, and outputs a test signal for operating the signal terminal 24 from the signal supply unit 36 to the signal terminal 24. Further, the function test unit 56 acquires the logical value of the output signal of the test element 20 that is output from the signal terminal 24 in response to the test signal at the acquisition timing of the output signal. Then, the function test unit 56 compares the logical value of the output signal obtained by the signal acquisition unit 40 with the expected value, and determines the test based on the comparison result of the logical comparison unit 44. The quality of component 20 is good.

In the test apparatus 10 configured as described above, the function test, the open circuit test, and the short circuit test of the device under test 20 can be performed. As an example, such a test apparatus 10 may be a circuit formed in an IC chip or in a module. Further, the signal supply unit 36, the signal receiving unit 38, and the signal acquisition unit 40 can be realized by an intellectual property core (IP core) for connecting a common interface of the test element 20.

Fig. 2 is a view showing an example of the configuration of the device under test 20. The device under test 20 is connected to an external circuit via a signal terminal 24.

The test element 20 includes, as an example, an internal circuit 60, a transfer buffer 62, a reception buffer 64, a first protective diode 66-1, and a second protective diode 66-2. The internal circuit 60 generates a transmission signal to be applied to an external circuit to which the signal terminal 24 is connected. The internal circuit 60 operates in response to a received signal from an external circuit to which the signal terminal 24 is connected.

The transfer buffer 62 is transmitted to the external circuit via the signal terminal 24 by the transfer signal generated by the internal circuit 60. The receiving buffer 64 receives and transmits a received signal given by an external circuit to the internal circuit 60 via the signal terminal 24.

The first protective diode 66-1 connects its anode to ground and its cathode to signal terminal 24. The second protective diode 66-2 has its anode connected to the signal terminal 24 and its cathode connected to the supply voltage (Vdd).

When such an overvoltage is applied to the signal terminal 24, the current to be injected from the signal terminal 24 can flow out from the power supply voltage or the ground voltage. Thereby, the device under test 20 can protect the transmission buffer 62 and the reception buffer 64 from overvoltage. Therefore, when such a test element 20 is supplied from the external circuit to the signal terminal 24 at a potential higher than the power supply potential, the current is passed from the signal terminal 24 to the second protective diode 66-2 toward the power supply. The voltage flows out.

Fig. 3 is a flow chart showing the processing of the test apparatus 10 of the present embodiment. First, in the test apparatus 10, an open circuit test is performed (S11). When the test device 10 determines that the signal supply unit 36 and the signal terminal 24 are open between the results of the open circuit test, the test device 10 is separated from the flow and the reconnection of the test element 20 is performed.

Next, the test apparatus 10 performs a short-circuit test (S12). When the test device 10 determines that the wiring between the signal supply unit 36 and the signal terminal 24 is short-circuited to another wiring as a result of the short-circuit test, the test device 10 is separated from the flow and the reconnection of the test element 20 is performed.

Next, in the test apparatus 10, it is determined that the wiring between the signal supply unit 36 and the signal terminal 24 is not open, and the wiring between the signal supply unit 36 and the signal terminal 24 is determined not to be short-circuited to other wirings. To perform a functional test (S13).

In the function test, the signal supply unit 36 supplies a test signal for operating the device under test 20 to the signal terminal 24. The signal acquisition unit 40 acquires the logical value of the output signal output from the signal terminal 24 corresponding to the test signal by the test element 20 at the acquisition timing defined for the output signal. The logic comparison unit 44 compares the logical value of the output signal obtained by the signal acquisition unit 40 with the expected value. Then, the function test unit 56 determines whether or not the device under test 20 is a good product based on the comparison result of the logical comparison unit 44.

Fig. 4 is a flow chart showing the processing of the open circuit test in step S11 of Fig. 3. In the open circuit test, first, the power supply unit 32 supplies a power supply voltage lower than the voltage supplied to the signal terminal 24 to the power supply input terminal 22 (S21). As an example, the power supply unit 32 supplies a ground voltage to the power supply input terminal 22.

Next, the signal supply unit 36 supplies a test signal of a power supply voltage higher than the voltage supplied from the power supply unit 32 to the power supply input terminal 22 to the signal terminal 24 (S22). As an example, the signal supply unit 36 supplies a voltage larger than a voltage corresponding to a high logic (high voltage) to the power supply input terminal 22.

Next, the detecting unit 46 detects a current that can flow from the signal terminal 24 toward the power supply input terminal 22 (S23). As an example, the detecting unit 46 detects whether or not there is a current that can flow from the power input terminal 22 toward the power supply unit 32 and has a predetermined value or more.

Next, the open circuit determination unit 52 determines whether or not the signal supply unit 36 and the signal terminal 24 are open based on the detection result of the detection unit 46 (S24).

Here, in the open circuit test, the voltage applied to the signal terminal 24 is brought to a higher state than the voltage applied to the power supply input terminal 22. Therefore, the protective diode system provided between the signal terminal 24 and the power input terminal 22 is turned on.

Therefore, when the signal supply unit 36 and the signal terminal 24 are not open (i.e., when connected), the protective diode can be placed between the signal terminal 24 and the power supply input terminal 22 to cause current. The signal terminal 24 flows toward the power input terminal 22. Conversely, when the signal supply unit 36 and the signal terminal 24 are open, the current cannot flow from the signal terminal 24 toward the power supply input terminal 22.

Therefore, when the current that can flow from the signal terminal 24 toward the power supply input terminal 22 is detected (YES in S24), the open circuit determination unit 52 determines that the signal supply unit 36 and the signal terminal 24 are not open. Further, when the current that can flow from the signal terminal 24 toward the power supply input terminal 22 is not detected (NO in S24), the open circuit determination unit 52 determines that the signal supply unit 36 and the signal terminal 24 are open.

According to the test apparatus 10 as described above, the open test can be performed without separately providing the DC test unit and the relay for connection switching. Thereby, according to the test apparatus 10, an open circuit test can be performed with a small structure.

Fig. 5 is a flow chart showing the processing of the short-circuit test in step S12 of Fig. 4. In the short-circuit test, first, the power supply unit 32 supplies a normal power supply voltage that can operate the device under test 20 to the power supply input terminal 22 (S31). Next, the switching unit 42 bypasses the signal acquisition unit 40 and connects the output end of the signal receiving unit 38 to the input terminal of the logic comparison unit 44 (S32).

Next, the signal supply unit 36 outputs a test signal whose logic value is changed at a predetermined timing without outputting the output signal from the device under test 20, and outputs the signal to the signal terminal 24 (S33). Further, the logic comparison unit 44 compares the logical value of the signal between the signal supply unit 36 and the signal terminal 24 and the logical value of the test signal outputted by the signal supply unit 36 before and after the predetermined timing. (S34).

Next, the short circuit determination unit 54 determines whether or not the wiring between the signal supply unit 36 and the signal terminal 24 is short-circuited to another wiring based on the comparison result of the logic comparison unit 44 (S35).

Here, when the wiring between the signal supply unit 36 and the signal terminal 24 is short-circuited to the power source, the test signal output from the signal supply unit 36 is not used, and the wiring between the signal supply unit 36 and the signal terminal 24 is not provided. The voltage is fixed at the supply voltage. Further, when the wiring between the signal supply unit 36 and the signal terminal 24 is short-circuited to the ground, the wiring between the signal supply unit 36 and the signal terminal 24 is fixed to the ground voltage. When the wiring between the signal supply unit 36 and the signal terminal 24 is short-circuited to another wiring, the voltage of the wiring between the signal supply unit 36 and the signal terminal 24 becomes the voltage of the other wiring that has been short-circuited. The voltage of influence.

Therefore, the short-circuit determination unit 54 is consistent with the logical value of the signal between the signal supply unit 36 and the signal terminal 24 and the logical value of the test signal outputted by the signal supply unit 36 before and after the predetermined timing. In the case (Yes in S35), it is determined that the wiring between the signal supply unit 36 and the signal terminal 24 is not short-circuited to other wiring. Further, the short-circuit determination unit 54 is a logical value of a signal between the signal supply unit 36 and the signal terminal 24 and a logical value of a test signal output by the signal supply unit 36, either before or after a predetermined timing. If they match (NO in S35), it is determined that the wiring between the signal supply unit 36 and the signal terminal 24 is short-circuited to other wiring.

According to the test apparatus 10 as described above, the short-circuit test can be performed without separately providing the DC test unit and the relay for connection switching. Thereby, according to the test apparatus 10, the short-circuit test can be performed with a small configuration.

Fig. 6 is a view showing the configuration of the test apparatus 10 and the member to be tested 20 according to the first modification of the embodiment. The test apparatus 10 of the present modification is configured to have substantially the same configuration and function as the test apparatus 10 shown in Fig. 1, and therefore the same reference numerals are given to the test apparatus 10 shown in Fig. 1 . The components have approximately the same configuration and functional components, and the descriptions other than the following differences are omitted.

In the test apparatus 10 of the present modification, the test element 20 having a plurality of signal terminals 24 is tested. The test apparatus 10 includes a power supply unit 32, a plurality of pattern generation units 34, a plurality of signal supply units 36, a plurality of signal reception units 38, a plurality of signal acquisition units 40, a plurality of switching units 42, and a plurality of logic comparison units 44. The detection unit 46 and the control unit 50.

The plurality of pattern generating portions 34 are provided corresponding to the plurality of signal terminals 24, respectively. Each of the pattern generating portions 34 generates a logical value of a test signal to be supplied to the corresponding signal terminal 24. Further, each of the pattern generating units 34 generates an expected value of an output signal output from the corresponding signal terminal 24.

The plurality of signal supply units 36 are provided corresponding to the plurality of signal terminals 24, respectively. Each of the signal supply units 36 supplies a test signal corresponding to the voltage of the logical value generated from the pattern generating unit 34 to the corresponding signal terminal 24.

The plurality of signal receiving units 38 are provided corresponding to the plurality of signal terminals 24, respectively. Each of the signal receiving units 38 receives an output signal output from the corresponding signal terminal 24 from the wiring between the corresponding signal supply unit 36 and the corresponding signal terminal 24, and outputs a logical value of the received output signal.

The plurality of signal acquisition units 40 are provided corresponding to the plurality of signal terminals 24, respectively. Each of the signal acquisition units 40 acquires a logical value of an output signal output from the corresponding signal receiving unit 38.

The plurality of switching sections 42 are provided corresponding to the plurality of signal terminals 24, respectively. Each of the switching units 42 switches to give the logical value obtained by the corresponding signal acquisition unit 40 to the corresponding logical comparison unit 44, or bypasses the signal acquisition unit 40 and the corresponding signal receiving unit 38 The output logical value is given to the corresponding logical comparison portion 44.

The plurality of logic comparison sections 44 are provided corresponding to the plurality of signal terminals 24, respectively. In the function test, each of the logical comparison units 44 compares the logical value of the output signal obtained by the corresponding signal acquisition unit 40 with the expected value generated by the predetermined pattern generation unit 34. Further, in the short-circuit test, each of the logic comparing units 44 is provided by the corresponding signal receiving unit 38 by the logical value of the test signal output from the corresponding signal supply unit 36 and by the signal acquisition unit 40 being bypassed. The logical values of the outputs are compared.

Fig. 7 is a flowchart showing the processing of the test apparatus 10 according to the first modification of the embodiment. The test apparatus 10 individually selects a plurality of signal terminals 24 as objects of an open circuit test, and tests whether the signal terminal 24 and the corresponding signal supply unit 36 are between one selected signal terminal 24. Open circuit (S41 to S43).

Here, when an open circuit test is performed on one selected signal terminal 24, the power supply unit 32 supplies a ground voltage to the power supply input terminal 22. Further, the signal supply unit 36 supplies a high voltage to one of the plurality of signal terminals 24, which is the target of the open-circuit test, and supplies the low voltage to the other signal terminals 24. Thereby, the current is not applied, and the signal terminal 24 which is not the target of the open circuit test flows toward the power supply input terminal 22, and the open circuit test can be performed only for the signal terminal 24 which is the target of the open circuit test.

Further, when an open circuit test is performed on one of the selected signal terminals 24, the detecting unit 46 detects that a current that can flow from the power supply input terminal 22 toward the power supply unit 32 can be detected as an open circuit. The signal terminal 24 of the test object flows from the signal supply unit 36 toward the power supply input terminal 22. The open circuit determination unit 52 determines whether or not the signal terminal 24 of the test element 20 to be the target of the open circuit test and the corresponding signal supply unit 36 are open based on the detection result of the detection unit 46. The open circuit determination unit 52 specifies the signal terminal 24 that is open between the signal supply unit 36 based on the individual determination results of the plurality of signal terminals 24.

Once all the terminals have completed the open circuit test, the test device 10 then individually selects the plurality of signal terminals 24 as the object of the short circuit test, and tests the signal supply portion 36 for a selected signal terminal 24. Whether the wiring between the signal terminal 24 and the signal terminal 24 is short-circuited to other wirings (S44 to S46).

When the short-circuit test is performed on one of the selected signal terminals 24, the plurality of signal supply units 36 are supplied with a logic value different from the other signal terminals 24 for the signal terminal 24 to be subjected to the short-circuit test. signal. By the acquisition of the logical value of the signal of the wiring between the signal terminal 24 and the corresponding signal supply unit 36, which is the target of the short-circuit test, the plurality of signal supply units 36 are targeted for the short-circuit test. The wiring between the signal terminal 24 and the corresponding signal supply unit 36 determines whether or not the short circuit is made.

When the short-circuit test is performed on one of the selected signal terminals 24, the logic comparator 44 corresponding to the signal terminal 24 that is the target of the short-circuit test is the signal terminal 24 and the signal supply unit that are the targets of the short-circuit test. The logical value of the signal between 36 and the logical value of the test signal from the corresponding signal supply unit 36 are compared. Then, the short-circuit determination unit 54 is a logical value of a signal between the signal terminal 24 and the signal supply unit 36 that is a target of the short-circuit test, and a logical value of the test signal that is output from the corresponding signal supply unit 36. In the case of coincidence, it is determined that the wiring between the signal supply portion 36 and the signal terminal 24 is not short-circuited to other wiring. The short-circuit determination unit 54 specifies the signal terminal 24 that is short-circuited to the other wiring by the wiring between the signal supply unit 36 based on the determination results of the plurality of signal terminals 24 .

Next, in the test apparatus 10, it is determined that the plurality of signal terminals 24 and the respective signal supply units 36 corresponding to each of the signal terminals 24 are not open, and that between the plurality of signal terminals 24 and the signal supply portions 36 corresponding thereto are respectively It is determined that the wiring is not short-circuited to other wirings, and as a necessary condition, the test signals are applied to the plurality of signal terminals 24 in parallel, and the function test of the device under test 20 is performed (S46). By the above processing, the test apparatus 10 can determine whether the test element 20 having the plurality of signal terminals 24 is good or bad.

Further, the test apparatus 10 can also integrate a plurality of signal terminals 24 and perform an open circuit test before performing steps S41 to S43. When a plurality of signal terminals 24 are integrated and an open circuit test is performed, the signal supply unit 36 supplies a high voltage to all of the plurality of signal terminals 24. Further, in this case, the power supply unit 32 supplies the ground voltage to the power supply input terminal 22. Next, the detecting unit 46 detects the magnitude of the current that can flow from the power input terminal 22 toward the power supply unit 32. Then, the open circuit determination unit 52 determines that none of the plurality of signal terminals 24 is open, in response to the detection unit 46 having a current of a magnitude larger than the detection reference.

When the test device 10 determines that any one of the plurality of signal terminals 24 is open, the processing of steps S41 to S43 is performed, and then the signal is specified based on the respective detection results of the plurality of signal terminals 24. The supply unit 36 is at least one signal terminal that is open.

Further, when the test apparatus 10 determines that none of the plurality of signal terminals 24 is open, the processing of steps S41 to S43 is omitted. As a result, when the test apparatus 10 determines that none of the plurality of signal terminals 24 is open, the open circuit test for each of the signal terminals 24 can be omitted.

Fig. 8 is a view showing a test apparatus 10 and a member to be tested 20 according to a second modification of the embodiment. The test apparatus 10 of the present modification is configured to have substantially the same configuration and function as the test apparatus 10 shown in Fig. 1, and therefore the same reference numerals are given to the test apparatus 10 shown in Fig. 1 . The components have approximately the same configuration and functional components, and the descriptions other than the following differences are omitted.

The test apparatus 10 of the present modification includes a timing switching unit 70 instead of the switching unit 42. The timing switching unit 70 switches a signal indicating the timing of obtaining the output signal and a signal indicating the timing of the test signal output from the signal supply unit 36, and supplies the signal to the signal acquisition unit 40. In the function test, the timing switching unit 70 selects a signal indicating the acquisition timing of the output signal, and supplies it to the signal acquisition unit 40. Further, in the short-circuit test, the timing switching unit 70 selects a signal indicating the timing of the test signal and supplies it to the signal acquisition unit 40.

The timing switching unit 70 supplies the acquired signal to the signal acquisition unit 40 regardless of either the functional test or the short-circuit test. Therefore, in the short-circuit test, the test apparatus 10 of the present modification can bypass the signal acquisition unit 40 and can compare the logical value of the test signal outputted by the signal supply unit 36 and the signal supply. The logical value of the signal of the wiring between the portion 36 and the signal terminal 24.

Fig. 9 is a view showing the configuration of an electronic component 200 according to a third modification of the embodiment. The electronic component 200 of the present modification is configured to have substantially the same configuration and function as the test device 10 shown in Fig. 1, and therefore the same reference numerals are given to the test device 10 shown in Fig. 1 . The components have approximately the same configuration and functional components, and the descriptions other than the following differences are omitted.

The electronic component 200 of the present modification is connected to an external circuit. Further, the electronic component 200 self-diagnoses whether or not the wiring between the electronic component 200 and the external circuit is short-circuited to other wiring.

The electronic component 200 includes an internal circuit 210 and a interface circuit 220. The internal circuit 210 generates a transmission signal that can be given to an external circuit. Further, the internal circuit 210 operates in response to a reception signal given by an external circuit. Further, the internal circuit 210 has a short circuit determining unit 54.

The interface circuit 220 includes a transmission buffer 62, a reception buffer 64, a signal acquisition unit 40, and a switching unit 42. The transfer buffer 62 transfers the transfer signal from the internal circuit toward the external circuit connected to the interface. The receiving buffer 64 receives the received signal from the external circuit from the wiring between the external circuit and the transfer buffer 62, and outputs the logical value of the received signal.

The signal acquisition unit 40 acquires the logical value of the received signal output from the reception buffer 64 at the acquisition timing specified for the received signal. The switching unit 42 switches between which of the logical value of the received signal output by the receiving buffer 64 and the logical value of the received signal obtained by the signal acquiring unit 40 is to be output.

In the normal operation, the switching unit 42 outputs the logical value of the received signal obtained by the signal acquisition unit 40 to the internal circuit 210. When the wiring between the test transfer buffer 62 and the external circuit is short-circuited, the switching unit 42 outputs the logical value of the signal received from the wiring output from the receiving buffer 64 to the short-circuit determination unit of the internal circuit 210. 54. Thereby, the switching unit 42 is based on the comparison result between the logical value of the signal between the transmission buffer 62 and the external circuit and the logical value of the transmission signal outputted from the transmission buffer 62 by the short-circuit determination unit 54. It is determined whether the wiring between the transfer buffer 62 and the external circuit is short-circuited to other wiring.

According to the electronic component 200 of the present modification as described above, it is possible to self-diagnose the wiring between the electronic component 200 and the external circuit and whether it is short-circuited to other wiring.

Fig. 10 is a view showing an example of the hardware configuration of the computer 1900 of the present embodiment. The computer 1900 of the present embodiment includes a CPU 2000, a RAM 2020, a graphics controller 2075, and a CPU peripheral portion having a display device 2080 that are connected to each other by a host controller 2082, and is connected to the CPU 2104 by the input/output controller 2084. The communication interface 2030 of the host controller 2082, the hard disk drive 2040, and the input/output portion having the CD-ROM drive 2060; and the ROM 2010, the floppy disk drive 2050, and the input/output chip 2070 to be connected to the input/output controller 2084 (legacy) input and output.

The host controller 2082 is connected to the RAM 2020, the CPU 2000 that accesses the RAM 2020 with a high transfer rate, and the graphics controller 2075. The CPU 2000 operates based on programs stored in the ROM 2010 and the RAM 2020, and controls each unit. The graphics controller 2075 acquires video data generated on a frame buffer provided in the RAM 2020, such as the CPU 2000, and displays it on the display device 2080. Instead of this, the graphics controller 2075 can also include a frame buffer for storing image data generated by the CPU 2000 or the like.

The input/output controller 2084 is connected to the host controller 2082, the communication interface 2030 of the relatively high speed input/output device, the hard disk drive 2040, and the CD-ROM drive 2060. The communication interface 2030 communicates with other devices through the network. The hard disk drive 2040 stores programs and data used by the CPU 2000 in the computer 1900. The CD-ROM drive 2060 reads a program or material from the CD-ROM 2095 and supplies it to the hard disk drive 2040 via the RAM 2020.

Further, the input/output controller 2084 is connected to the relatively low-speed input/output devices of the ROM 2010, the floppy disk drive 2050, and the input/output chip 2070. The ROM 2010 is a boot program that is executed when the computer 1900 is started up, and a program that depends on the hardware of the computer 1900. The floppy disk drive 2050 reads a program or data from the floppy disk 2090 and provides it to the hard disk drive 2040 via the RAM 2020. The input/output chip 2070 connects the floppy disk drive 2050 to the input/output controller 2084, and at the same time, various input/output devices are connected via, for example, a parallel port, a series port, a keyboard 埠, and a mouse 埠. Connected to the input and output controller 2084.

The program supplied to the hard disk drive 2040 via the RAM 2020 is stored in a recording medium such as a floppy disk 2090, a CD-ROM 2095, or an IC card, and is provided by a user. The program is read from the memory medium and installed in the hard disk drive 2040 in the computer 1900 via the RAM 2020, and is executed in the CPU 2000.

The computer 1900 is installed as a program for controlling the control unit 50 of the testing device 10, and has an open circuit determination module, a short circuit determination module, and a function test module. These programs or modules drive the CPU 2000 and cause the computer 1900 to function as the open circuit determination unit 52, the short circuit determination unit 54, and the function test unit 56, respectively.

The information processing described in these programs is read by the computer 1900, and is used as an open circuit determination unit 52, a short-circuit determination unit 54, and a function test unit 56 of a specific device in which the software and the above-described various hardware resources cooperate. Play the function. Further, in accordance with these specific devices, the control unit 50 of the specific test device 10 for the purpose of use is constructed by calculating or processing the information according to the purpose of use of the computer 1900 in the present embodiment.

As an example, when the computer 1900 communicates with an external device or the like, the CPU 2000 executes a communication program uploaded to the RAM 2020, and instructs the communication interface 2030 to perform communication processing based on the processing content described in the communication program. The communication interface 2030 receives the control of the CPU 2000, and reads the transmission data stored in the transmission buffer area or the like set on the memory device such as the RAM 2020, the hard disk drive 2040, the floppy disk 2090, or the CD-ROM 2095, and The data transmitted to the network or received from the network is written into the receiving buffer field set on the memory device. In this way, the communication interface 2030 can also transmit and receive data between the memory devices by means of DMA (Direct Memory Access). Instead of this, the CPU 2000 can also read data from the memory device or communication interface 2030 of the transmission source. And transmitting and receiving the data by directing and writing the data to a communication interface or a memory device at the transmission location.

Further, the CPU 2000 is a DMA transfer or the like from a file or a database stored in an external storage device such as a hard disk drive 2040, a CD-ROM drive 2060 (CD-ROM 2095), or a floppy disk drive 2050 (floppy disk 2090). Read all or necessary parts into RAM 2020 and perform various processing on the data on RAM 2020. Then, the CPU 2000 directs and processes the processed data to the external memory device by DMA transfer. In such a process, the RAM 2020 is regarded as temporarily holding the contents of the external memory device. Therefore, in the present embodiment, the RAM 2020 and the external memory device are collectively referred to as a memory, a memory, or a memory device. Various kinds of information such as various programs, materials, tables, and databases in the present embodiment are stored in such a memory device and are targeted for information processing. Further, the CPU 2000 stores a part of the RAM 2020 in the cache memory, and can also read and write on the cache memory. Even in such a state, since the cache memory system functions as a part of the RAM 2020, in the present embodiment, the cache memory is included in the RAM 2020, the memory, and/or in addition to the difference. In the memory device.

Further, the CPU 2000 performs various processes including the various calculations, information processing, condition determination, information retrieval, and replacement described in the present embodiment, which are specified by the program command line, for the data read from the RAM 2020. And face and write back to RAM2020. For example, when the CPU 2000 performs the condition determination, the CPU 2000 compares the various variables shown in the present embodiment with other variables or constants, and determines whether the conditions of greater than, less than, above, below, phase, and the like are satisfied, and In the case where the condition is established (or if it is not established), the difference is to a different command line, or to the sub-coutine (subroutine).

Further, the CPU 2000 can search for information stored in a file or a database in the memory device. For example, for the attribute value of the first attribute, the attribute value of the second attribute corresponds to each of the associated multiple entry entries, and when stored in the memory device, the CPU 2000 is stored in the plural from the memory device. In the entry point, an entry point whose attribute value of the first attribute is consistent with the specified condition is retrieved, and by reading the attribute value of the second attribute stored in the entry point, the first attribute satisfying the predetermined condition can be obtained. The attribute value of the associated second attribute.

The program or module shown above can also be stored in an external memory medium. In addition to the floppy disk 2090 and the CD-ROM 2095, a semiconductor recording medium such as an optical recording medium such as a DVD or a CD, a magneto-optical recording medium such as an MO, a magnetic tape medium, or an IC card can be used as the recording medium. Further, a memory device such as a hard disk or a RAM provided on a server system connected to a dedicated communication network or the Internet can be used as a memory medium, and the program can be supplied to the computer 1900 through the network.

The present invention has been described above using the embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It is understood that various changes or improvements can be applied to the above embodiments. It is understood from the description of the scope of the patent application that the form in which such changes or improvements are applied can also be included in the technical scope of the present invention.

The order of execution of the processes, procedures, steps, and stages in the devices, systems, programs, and methods shown in the claims, the description, and the drawings is not specifically stated as "before" or "before" Etc., or if the previously processed output is not used for later processing, it should be noted that it can be implemented in any order. The operation flow in the patent application scope, the specification, and the drawings is described using "first", "continued", etc., in convenience, but it does not mean that it must be implemented in this order.

10. . . Test device

20. . . Tested component

twenty two. . . Power input terminal

twenty four. . . Signal terminal

32. . . Power supply department

34. . . Pattern generation department

36. . . Signal supply department

38. . . Signal receiving unit

40. . . Signal acquisition unit

42. . . Switching department

44. . . Logic comparison department

46. . . Checkout department

50. . . Control department

52. . . Open circuit determination department

54. . . Short circuit determination unit

56. . . Functional test department

60. . . Internal circuit

62. . . Transfer buffer

64. . . Receive buffer

66-1. . . First protective diode

66-2. . . Second protective diode

70. . . Timing switching unit

200. . . Electronic component

210. . . Internal circuit

220. . . Interface circuit

1900. . . computer

2000. . . CPU

2010. . . ROM

2020. . . RAM

2030. . . Communication interface

2040. . . Hard disk drive

2050. . . Floppy disk player

2060. . . CD-ROM drive

2070. . . Input and output chip

2075. . . Graphics controller

2080. . . Display device

2082. . . Host controller

2084. . . Input and output controller

2090. . . floppy disk

2095. . . CD-ROM

Fig. 1 is a view showing the configuration of the test apparatus 10 of the present embodiment and the member to be tested 20 together.

Fig. 2 is a view showing an example of the configuration of the device under test 20.

Fig. 3 is a flow chart showing the processing of the test apparatus 10 of the present embodiment.

Fig. 4 is a flow chart showing the processing of the open circuit test in step S11 of Fig. 3.

Fig. 5 is a flow chart showing the processing of the short-circuit test in step S12 of Fig. 4.

Fig. 6 is a view showing the configuration of the test apparatus 10 and the member to be tested 20 according to the first modification of the embodiment.

Fig. 7 is a flowchart showing the processing of the test apparatus 10 according to the first modification of the embodiment.

Fig. 8 is a view showing the test apparatus 10 and the member to be tested 20 according to a second modification of the embodiment.

Fig. 9 is a view showing the configuration of the electronic component 200 of the present embodiment.

Fig. 10 is a view showing an example of the hardware configuration of the computer 1900 of the present embodiment.

10. . . Test device

20. . . Tested component

twenty two. . . Power input terminal

twenty four. . . Signal terminal

32. . . Power supply department

34. . . Pattern generation department

36. . . Signal supply department

38. . . Signal receiving unit

40. . . Signal acquisition unit

42. . . Switching department

44. . . Logic comparison department

46. . . Checkout department

50. . . Control department

52. . . Open circuit determination department

54. . . Short circuit determination unit

56. . . Functional test department

Claims (20)

A test apparatus for performing an open circuit test or a short circuit test related to a functional test of a device to be tested, comprising: a power supply unit that supplies a power supply voltage to a power supply input terminal of the device under test; and a signal supply unit that supplies a test signal to a signal terminal of the device to be tested; and a detection unit that detects a power supply voltage lower than a voltage supplied to the signal terminal and supplies the power supply voltage to the power supply input terminal, and detects the signal from the signal supply unit a protective diode in the device under test, a current flowing toward the power input terminal, and a protective diode in the device to be tested is used to cause an overvoltage input to the signal terminal to face the power input terminal And flowing. The test apparatus according to claim 1, further comprising: an open circuit determining unit that determines the signal supply unit and the signal when detecting a current flowing from the signal terminal toward the power input terminal There is no open circuit between the terminals. The test apparatus according to claim 2, further comprising: a signal receiving unit that receives an output output from the signal terminal of the device under test from a wiring between the signal supply unit and the signal terminal a signal, and outputting a logic value of the output signal; and a signal acquisition unit that acquires a logic value of the output signal at a predetermined acquisition timing for the output signal; a short circuit determination unit that determines a logical value of a signal between the signal supply unit and the signal terminal received by the signal receiving unit and the signal supply unit in a state where the output signal is not output from the device under test The result of the comparison of the logical values of the output test signals determines whether or not the wiring between the signal supply unit and the signal terminal is short-circuited to another wiring. The test apparatus according to claim 2, wherein the power supply unit is configured to allow the test element to be used when the signal supply unit and the signal terminal are determined to be not open circuits. The power supply voltage to be operated is supplied to the power supply input terminal, and the signal supply unit supplies a test signal for operating the device under test to the signal terminal to perform a function test of the device to be tested. The test apparatus according to claim 2, wherein the test element includes a plurality of the signal terminals, and the signal supply unit supplies a high voltage to the plurality of signal terminals to be an open circuit. One of the signal terminals of the test object supplies a low voltage to the other signal terminals, and the power supply unit supplies a ground voltage to the power supply input terminal in the open circuit test. The test device according to claim 5, wherein: the test device individually selects the plurality of signal terminals as an object of an open circuit test; The signal supply unit supplies a high voltage to one of the signal terminals to be subjected to the open circuit test, and supplies a low voltage to the other signal terminals. The detection unit is a signal for the target of the open circuit test. The terminal detects a current flowing from the signal supply unit toward the power supply input terminal; and the open circuit determination unit determines that the signal supply unit is open based on a detection result of the signal terminal to be subjected to the open circuit test. Whether the signal terminals of the aforementioned test elements of the test object are open circuits. The test device according to claim 5, wherein the test element includes a plurality of the signal terminals, and the signal supply unit supplies a high voltage to the plurality of signal terminals; and the power supply unit In the open circuit test, the ground voltage is supplied to the power input terminal; the detecting unit detects the magnitude of the current flowing through the power input terminal; and the open circuit determining unit detects the response in the detecting unit. The current of the size above the reference is determined, and it is determined that the plurality of signal terminals are not open. The test apparatus according to claim 7, wherein the signal supply unit sequentially outputs the plurality of signal terminals in response to the detection unit detecting a current of a size less than a reference. Select as the object of the open circuit test and supply a high voltage to become an open circuit One of the signal terminals of the test, and a low voltage is supplied to the other signal terminals; and the detecting unit detects, for each of the plurality of signal terminals, flowing from the signal supply unit toward the power input terminal. The current; the open circuit determination unit specifies at least one of the signal terminals that is open to the signal supply unit based on an individual determination result of the plurality of signal terminals. A test apparatus for performing a short-circuit test related to a functional test of a device to be tested, comprising: a signal supply unit that supplies a test signal to a signal terminal of the test element; and a signal receiving unit that receives the signal supply unit and the signal The wiring between the terminals receives an output signal output from the signal terminal of the device under test, and outputs a logic value of the output signal; and the signal acquisition unit acquires an output signal at a predetermined acquisition timing for the output signal. a logic value; and a short circuit determining unit that determines a logical value of a signal between the signal supply unit and the signal terminal received via the signal receiving unit without outputting the output signal from the device under test The result of the comparison of the logical values of the test signals outputted by the signal supply unit determines whether or not the wiring between the signal supply unit and the signal terminal is short-circuited to another wiring. The test apparatus according to claim 9, further comprising: a logic comparison unit that acquires the signal acquisition unit at the acquisition timing The logical value of the obtained output signal is compared with the expected value. The test apparatus according to claim 10, wherein the signal supply unit is configured to determine that the signal supply unit and the signal terminal are not short-circuited to another wiring. a test signal for operating the device to be tested is supplied to the signal terminal, and the signal acquisition unit acquires a logical value of an output signal of the device under test corresponding to the test signal and outputs the signal from the signal terminal at the acquisition timing; The logic comparison unit compares the logical value of the output signal obtained by the signal acquisition unit with an expected value to perform a function test of the device under test. The test apparatus according to claim 10, wherein the test element includes a plurality of the signal terminals, and the signal supply unit is one of the plurality of signal terminals that is a target of a short-circuit test. The signal terminal supplies a test signal having a logic value different from that of the other signal terminals. The test apparatus according to claim 12, wherein the signal supply unit sequentially selects the plurality of signal terminals as one of the target terminals of the short-circuit test as a target of the short-circuit test. a test signal for supplying a logic value different from the other signal terminals; the short circuit determination unit is a logic value of a signal between the signal supply unit and the signal terminal, and a test output by the signal supply unit The logical values of the test signals are identical, and it is determined that the wiring between the signal supply portion and the signal terminal is not short-circuited. The test apparatus according to claim 10, wherein the signal supply unit outputs a test signal whose logic value is changed at a predetermined timing to a signal terminal in the short-circuit test, and the short-circuit determination unit The signal supply unit and the signal terminal are determined based on a change in a logical value of a signal between the signal supply unit and the signal terminal and a comparison result of a change in a logical value of a test signal outputted by the signal supply unit. The connection state between the wirings. The test apparatus according to claim 10, further comprising: a switching unit that supplies a logic value of an output signal obtained by the signal acquisition unit to the logic comparison unit in a function test, and In the short-circuit test, the logic value of the output signal output from the signal receiving unit is supplied to the logic comparison unit, and the short-circuit determination unit is based on the logic comparison unit between the signal supply unit and the signal terminal. Whether the logical value of the signal and the logical value of the test signal outputted by the signal supply unit are compared, it is determined whether or not the wiring between the signal supply unit and the signal terminal is short-circuited. A test method for performing an open circuit test or a short circuit test related to a functional test of a device to be tested, wherein a power supply voltage is supplied from a power supply unit to a power supply input terminal of the device under test, and a test signal is supplied from the signal supply unit to the aforementioned The signal terminal of the component being tested, On the other hand, when the power supply voltage lower than the voltage supplied to the signal terminal is supplied to the power supply input terminal, the protective diode is detected from the signal supply unit and passes through the device under test. A current flowing through the power input terminal, and a protective diode in the device to be tested is used to cause an overvoltage input to the signal terminal to flow toward the power input terminal. A computer program product that functions as an open circuit determination unit provided in the test device according to any one of claims 2 to 8. A test method for performing a short-circuit test related to a functional test of a device to be tested, wherein a signal is supplied from a signal supply unit to a signal terminal of the device to be tested, and a signal receiving unit is provided from the signal supply unit and the aforementioned The wiring between the signal terminals receives an output signal output from the signal terminal of the device under test, and outputs a logic value of the output signal, and obtains a predetermined timing for the output signal by the signal acquisition unit. And outputting a logical value of the signal based on a logical value of the signal between the signal supply unit and the signal terminal received by the signal receiving unit without causing the output signal to be output from the device under test The result of the comparison of the logical values of the test signals outputted by the supply unit determines whether or not the wiring between the signal supply unit and the signal terminal is short-circuited to the other wiring. A computer program product, which is a short circuit determination unit provided in a test device according to any one of claims 9 to 15 Play the function. An electronic component for self-diagnosis for self-diagnosing wiring between the electronic component itself and the external circuit, whether short-circuited to other wiring, the electronic component having: a transmission buffer that transmits a signal from an internal circuit, Transmitting to an external circuit connected to the receiving place; receiving a buffer for receiving a received signal from the external circuit from a wiring between the external circuit and the transmitting buffer, and outputting a logical value of the received signal; a logical value of the received signal obtained by the acquisition timing defined for the received signal, and a logic for the logical value of the received signal output by the receive buffer and the received signal obtained by the signal acquisition unit Which of the values is to be output for switching; and the short-circuit determining unit determines whether or not the wiring between the transfer buffer and the external circuit is short-circuited; wherein the wiring between the transfer buffer and the external circuit is tested In the case of a short circuit, the switching unit will receive the reception from the foregoing The logical value of the signal received by the device and outputted by the device is outputted, and the short circuit determining unit is based on the logical value of the signal between the transfer buffer and the external circuit and output by the transfer buffer. As a result of the comparison of the logical values of the transfer signals, it is determined whether or not the wiring between the transfer buffer and the external circuit is short-circuited.