TWI405172B - Liquid crystal display device and driving method thereof - Google Patents

Abstract

The present invention relates to a liquid crystal display device and a driving method thereof. The liquid crystal display device includes a liquid crystal display panel, a data driving circuit, a common voltage generation circuit and a scanning driving circuit. The liquid crystal display panel includes a plurality of data lines, a plurality of scanning lines that intersect with the data lines and a plurality of common electrodes. The scanning driving circuit provides a plurality of scanning signals to scan the scanning lines. The common voltage generation circuit provides a common voltage to the common electrodes. The data driving circuit provides a plurality of gray scale voltages to the data lines. Thereinto, the common voltage's period is two frames at least, and it makes of impulse signals. The impulse signals always change periodically in every frame, and there are two different impulse signals' periods within one period of the common voltage.

Description

Liquid crystal display device and driving method thereof

The present invention relates to a liquid crystal display device and a method of driving the same.

In a general thin film transistor liquid crystal display device, an image is displayed by changing a voltage applied to each pixel to change an electric field on both sides of a liquid crystal molecule corresponding to the pixel region to control a twist angle thereof, thereby controlling light. It is achieved by quantity. The liquid crystal molecules have such a characteristic that if the direction of the electric field applied to the two sides of the liquid crystal layer remains unchanged for a long time, the physical properties of the liquid crystal molecules are destroyed, that is, the corresponding rotation can no longer be performed according to the change of the electric field. Therefore, the direction of the electric field applied to the two sides of the liquid crystal layer must be changed at regular intervals to cause the liquid crystal molecules to be deflected alternately in opposite directions to prevent the physical properties from being destroyed. At present, the inversion driving method of the liquid crystal display device includes Frame Inversion, Column Inversion, Line/Row Inversion, and Dot Inversion. Among them, the column inversion driving includes a single line column inversion driving and a two line column inversion driving.

Please refer to FIG. 1, which is a schematic diagram of a prior art single line column inversion driving method. Specifically, in the single-line column inversion driving method, all the pixels in any column of each frame are loaded with the same polarity of voltage, and the polarity of the voltage applied to each column of each frame of the picture is adjacent to the column of the adjacent column. The voltage of the load is reversed in polarity; the polarity of the voltage applied to each pixel is inverted frame by frame.

Please refer to FIG. 2 and FIG. 3 together. FIG. 2 is a schematic diagram of a 1-line Column Flicker Pattern of a liquid crystal display device using a single-line column inversion driving method. Figure 3 shows the single line column shown in Figure 2. Reverse the schematic of the flashing pattern. In FIG. 2, the blank square indicates that the corresponding pixel displays a bright state, and the luminance values are equal, and the shaded square indicates that the corresponding pixel displays a dark state. In FIG. 3, the pixels indicated by the circles correspond to the blank squares in FIG. 2, that is, they all display a bright state, and the brightness values are equal; the pixels without the circle mark correspond to the shaded squares in FIG. 2, that is, they all display darkness. state. When the liquid crystal display device uses the single line column inversion driving method to display the single line column inversion flashing pattern shown in FIG. 2, the polarity of the voltage applied to all the pixels displaying the bright state is positive in the nth frame, at the n+1th. All frames are negative polarity, and all of the n+2 frames are positive, and the other frames can be analogized. Thereby, the polarity of the voltage applied to both sides of the liquid crystal layer is inverted once every frame, so that the liquid crystal molecules maintain good physical properties.

Generally, the common voltage applied to one side of the liquid crystal molecules is a continuous square wave pulse signal, and the pulse period of the common voltage of each frame is the same. The pixel voltage applied to the other side of the liquid crystal molecule corresponds to the common male voltage. When the common voltage is less than the corresponding pixel voltage, the voltage applied by the corresponding pixel is positive, otherwise, when the common voltage is greater than the corresponding pixel voltage, the voltage applied to the corresponding pixel is negative. Sex. However, in practical applications, the common voltage applied to one side of the liquid crystal molecules is usually shifted, that is, the waveform is asymmetrical, thereby causing the liquid crystal display device using the single line column inversion driving method to display a still picture. The positive polarity voltage value of the pixel displayed in the bright state is not exactly equal to the negative voltage value loaded in the pixel, and the brightness of the n+1th frame is different from the brightness of the nth frame, the n+2 The brightness of the frame picture is different from the brightness of the n+1th frame picture, that is, the brightness of each adjacent two frames is inconsistent, and the brightness is different from the entire display process of the liquid crystal display device. Straight to exist. Since the human eye can distinguish this brightness difference, it will see the flickering of the picture.

In order to solve the above problems, the industry has proposed a two-line column inversion driving method. Please refer to FIG. 4 , which is a schematic diagram of a two-line column inversion driving method. Specifically, in the two-line column inversion driving method, the 2n-1th column (n is a natural number) of each frame picture and the voltage polarity of all the pixels in the 2nth column are matched, and the 2n+1th column is identical. The polarity of the voltage applied to all the pixels in the 2n+2th column is the same, and the polarity of the voltage applied to the 2n-1th, 2nth column of pixels is opposite to the polarity of the voltage applied to the 2n+1th, 2n+2th column of pixels; The polarity of the voltage applied to the pixel is inverted frame by frame.

Please refer to FIG. 5 , which is a schematic diagram of a liquid crystal display device using a two-line column inversion driving method to display the single-line column inverted flashing pattern shown in FIG. 2 . In FIG. 5, the pixels indicated by the circles display a bright state, and the pixels without the circle display a dark state. When the liquid crystal display device adopts the double line column inversion driving method to display the single line column inversion flashing pattern, in any frame, half of the plurality of pixels in the display bright state are positive polarity and the other half is negative polarity. The brightness of the positive polarity pixel and the brightness of the negative polarity pixel are spatially compensated for each other, so that the brightness of each frame is uniform. Therefore, the human eye does not feel the change of the picture brightness between the frame and the frame, thereby effectively solving the problem of flickering of the picture generated by the single line column inversion driving method shown in FIG. 2 when the single line column inversion blinking pattern is displayed.

However, when the liquid crystal display device using the two-line column inversion driving method displays the two-line column inversion flashing pattern, there is still a problem of flickering of the screen, as described below: Referring to FIG. 6 and FIG. 7, FIG. 6 is a liquid crystal display device. Double line reverse flashing pattern with 2-line column inversion drive method (2-Line Schematic of the Column Flicker Pattern). Figure 7 is a schematic diagram of a two-line column inverted flashing pattern. In FIG. 6, the blank square indicates that the corresponding pixel displays a bright state, and the luminance values are equal, and the shaded square indicates that the corresponding pixel displays a dark state. In FIG. 7 , the pixels indicated by the circles correspond to the blank squares in FIG. 6 , that is, they all display a bright state, and the brightness values are equal; the pixels without the circle mark correspond to the shaded squares in FIG. 6 , that is, they all display the dark state. . When the liquid crystal display device uses the two-line column inversion driving method to display the two-line column inversion flashing pattern, the polarity of the voltage applied to all the pixels displaying the bright state is positive in the nth frame, and all in the n+1th frame. The negative polarity is all positive in the n+2th frame. Because the positive polarity voltage value of the pixel displayed in the bright state in FIG. 7 is not exactly equal to the negative polarity voltage value loaded therein, the brightness of the n+1th frame picture is different from the brightness of the nth frame picture, The brightness of the n+2 frame picture is different from the brightness of the n+1th frame picture, that is, the brightness of each adjacent two frame picture is different, and the brightness difference always exists in the entire display process of the liquid crystal display device. Since the human eye can distinguish this brightness difference, it will see the flickering of the picture.

Therefore, regardless of whether the single-line column inversion driving method is employed or the two-line column inversion driving method is employed, the liquid crystal display device has a flicker phenomenon when displaying a specific screen.

In view of the above, it is necessary to provide a liquid crystal display device capable of improving the flickering phenomenon of a picture.

It is also necessary to provide a driving method of a liquid crystal display device capable of improving flickering of a picture.

A liquid crystal display device comprising a liquid crystal display panel and a data a driving circuit, a common voltage generating circuit and a scan driving circuit. The liquid crystal display panel includes a plurality of data lines, a plurality of scan lines intersecting the data lines, and a plurality of common electrodes. The scan driving circuit is configured to apply a series of scan signals to the scan line. The common voltage generating circuit is for supplying a common voltage to the common electrode. The data driving circuit is configured to apply a complex gray scale voltage signal corresponding to the common voltage to the data line when the liquid crystal display panel is scanned. The common voltage is a pulse signal with at least two frames as a period. In each frame, the pulse signal is periodically changed, and the common voltage includes at least two different pulse signal periods in one cycle.

A liquid crystal display device comprising a liquid crystal display panel, the liquid crystal display panel comprising a plurality of data lines, a plurality of scan lines intersecting the data lines, and a plurality of common electrodes, the driving method comprising the steps of: (a Applying a series of scan signals to the scan lines; (b) applying a common voltage to the common electrode; (c) applying a plurality of gray scale voltage signals corresponding to the common voltage to the data lines when the liquid crystal display panel is scanned. The common voltage is a pulse signal with at least two frames as a period. In each frame, the pulse signal is periodically changed, and the common voltage includes at least two different pulse signal periods in one cycle.

Compared with the prior art, in the liquid crystal display device and the driving method thereof, the common voltage is a pulse signal with at least two frames as a period, and in each frame, the pulse signal is periodically changed, and the common The voltage includes at least two different pulse signal periods in one cycle. The data driving circuit applies a complex gray scale voltage signal corresponding to the common voltage to the data line when the liquid crystal display panel is scanned. Therefore, the driving method of the liquid crystal display device of the present invention integrates at least a single line column inversion driving method and a double line column There are two kinds of inversion driving methods and three-line column inversion driving methods. Therefore, the polarities of the voltages applied to the pixels displaying the bright state in all frame pictures are not all positive or negative, and are displayed in one frame. The brightness of the positive polarity pixel in the bright state and the brightness of the negative polarity pixel in the display bright state are spatially compensated for each other, so there is no difference in the brightness of the picture between the frame and the frame or the difference in the brightness of the picture exists only for part of the time. Therefore, the liquid crystal display device driving method of the present invention can improve the flickering phenomenon of the screen.

Please refer to FIG. 8, which is a block diagram of a circuit of a liquid crystal display device of the present invention. The liquid crystal display device 1 includes a liquid crystal display panel 10, a scan driving circuit 20, a data driving circuit 30, a common voltage generating circuit 40, and a timing controller 50. The timing controller 50 includes a memory 60. The memory 60 stores a program provided by an external system (not shown).

The liquid crystal display panel 10 includes a plurality of scanning lines 11 that are parallel to each other and a plurality of data lines 12 that are parallel to each other and that are perpendicularly insulated from the scanning lines 11 respectively. The plurality of scanning lines 11 and the plurality of data lines 12 divide the liquid crystal display panel 10 into a plurality of pixels 13 . Each of the pixels 13 includes a thin film transistor 14 and a pixel electrode adjacent to the scanning line 11 and the data line 12 . 15. A common electrode 16 disposed opposite the pixel electrode 15 and liquid crystal molecules sandwiched between the two electrodes 15, 16. A gate (not shown) of the thin film transistor 14 is connected to the scan line 11, a source (not shown) is connected to the data line 12, and a drain (not shown) is connected to the pixel electrode 15.

An external circuit 70 delivers three primary color (Red Green Blue, RGB) signals and a plurality of control signals to the timing controller 50. The complex control signal includes a Vertical Synchronization (VSYNC) signal and level Horizontal Synchronization (HSYNC) signal.

The VSYNC signal is the initial synchronization signal of one frame scanning period, and the RGB signal of each frame is intercepted. The HSYNC signal is a start sync signal of a scan period, and the RGB signals of the pixels 13 on each column of scan lines 11 are intercepted. The period of the HSYNC signal is the time when the scan signal scans the scan line 11 of the column.

The timing controller 50 receives the RGB signal and the complex control signal. According to the control signal and the program stored in the memory 60, the timing controller 50 generates a polarity inversion signal POL and a complex timing control signal, and outputs the polarity inversion signal POL to the common voltage generating circuit 40 to output the RGB. The signal and the corresponding timing control signal are sent to the data driving circuit 30 and the output timing control signal to the scan driving circuit 20. The polarity inversion signal POL is a continuous square wave pulse signal with at least two frames as a period, and the pulse signal in each frame changes periodically. The polarity inversion signal POL includes at least two different pulse signal periods in one cycle. The polarity inversion signal POL uses the VSYNC signal and the HSYNC signal as a time reference standard. In the timing, the period of the polarity inversion signal POL in each frame is an even multiple of the HSYNC signal period, and the duty ratio is 50%.

Please refer to FIG. 9 and FIG. 10 together. FIG. 9 is a flowchart of a method for generating the polarity inversion signal POL by the timing controller 50. FIG. 10 is a driving timing diagram of the first embodiment in which the timing controller 50 generates the polarity inversion signal POL. The method for the timing controller 50 to generate the polarity inversion signal POL includes the following steps: Step S1: Start.

Step S2: Count the VSYNC signal as n.

When the VSYNC signal received by the timing controller 50 changes from a low level 0 to a high level 1, the timing controller 50 counts the VSYNC signal according to the program stored in the memory 60, and sets the current VSYNC signal to be the first n.

Step S3: Divide the HSYNC signal by two to generate a polarity inversion signal POL.

The timing controller 50 receives the HSYNC signal, and divides the HSYNC signal by two according to a program stored in the memory 60 to generate a polarity inversion signal POL whose level changes from high to low periodically, and outputs the The polarity inversion signal POL is supplied to the common voltage generating circuit 40.

Step S4: determining whether the n+1th VSYNC signal is present. If yes, go to step S5; if no, go to step S3.

If the timing controller 50 determines that the n+1th VSYNC signal appears, that is, the liquid crystal display device 1 enters a new frame display screen, otherwise step S5 is performed; otherwise, the liquid crystal display device 1 does not enter a new frame display screen, Go to step S3.

Step S5: The VSYNC signal is counted as n+1.

Step S6: dividing the HSYNC signal by four to generate a polarity inversion signal POL.

The timing controller 50 receives the HSYNC signal, and divides the HSYNC signal by four according to a program stored in the memory 60 to generate a polarity inversion signal POL whose level is inverted from a low to a high periodicity. The polarity inversion signal POL is output to the common voltage generating circuit 40.

Step S7: determining whether the n+2th VSYNC signal is present. If yes, step S2 is performed; if not, step S6 is performed.

If the timing controller 50 determines that the n+2 VSYNC signals appear, that is, the liquid crystal display device 1 enters a new frame display screen, step S2 is executed, and the timing controller 50 starts to generate the polarity inversion signal of the next cycle. POL; otherwise, the liquid crystal display device 1 does not enter the new frame display screen, and then step S6 is performed.

Please refer to FIG. 11 , which is a waveform diagram of driving signals of the liquid crystal display panel 10 . Wherein, G1-G4n is a waveform diagram of the scan signal outputted by the scan driving circuit 20, and Vn is a waveform of a plurality of gray scale voltage signals applied to the data line 12 by the data driving circuit 30, and VCOM is the common voltage generating circuit 40. A common voltage generated on the common electrode 16 is generated according to the polarity inversion signal POL received.

The scan driving circuit 20 outputs a series of scanning signals G1-G4n to the scanning line 11 of the liquid crystal display panel 10 according to the received timing control signal, and the thin film transistors 14 on the scanning line 11 are sequentially turned on. The scan signal is a periodic pulse signal, and the period is the time of scanning the scan line 11 of the column.

At the same time, the common voltage generating circuit 40 correspondingly outputs the common voltage VCOM alternating between positive and negative polarity to the common electrode 16 of the liquid crystal display panel 10 according to the received polarity inversion signal POL. When the polarity inversion signal POL received by the common voltage generating circuit 40 is at a high level, it correspondingly outputs a positive polarity common voltage to the common electrode 16, otherwise, when the common voltage generating circuit 40 receives the polarity inversion signal POL is low. At the level, it corresponds to the output of the negative common voltage to the common electrode 16. therefore, The common voltage VCOM is a continuous square wave pulse signal with a period of two frames, and the pulse signal in each frame changes periodically. The common voltage VCOM includes at least two different pulse signal periods. In the timing, the period of the common voltage VCOM in each frame is an even multiple of the period of the HSYNC signal, that is, an even multiple of the scan signal period applied to the liquid crystal display panel 10 by the scan driving circuit 20, and The space ratio is 50%.

At this time, the data driving circuit 30 converts the received RGB signal into a complex gray scale voltage signal Vn corresponding to the common voltage VCOM according to the received synchronization control timing, and applies the complex gray scale voltage signal Vn to the liquid crystal. The data line 12 of the display panel 10 is formed by the source and the drain of the thin film transistor 14 to the pixel electrode 15, so that the liquid crystal display panel 10 realizes display.

Referring to FIG. 12 together, FIG. 12 is a schematic diagram showing the voltage polarity of the pixel 13 of the liquid crystal display panel 10 in the driving mode shown in FIG. In the nth frame and the n+2th frame, the liquid crystal display device 1 adopts a single line column inversion driving method, and the polarity of the voltage applied to each pixel 13 in the n+2th frame is the same as the nth frame; in the n+1th frame And in the n+3th frame, the liquid crystal display device 1 adopts a two-line column inversion driving method, and the polarity of the voltage applied to each pixel 13 in the n+3th frame is the same as the n+1th frame. The nth frame to the n+1th frame are one cycle.

Please refer to FIG. 13 , which is a schematic diagram showing the single-line column inverted flashing pattern shown in FIG. 2 in the liquid crystal display device 1 of the present invention under the inversion driving method shown in FIG. 11 . In Fig. 13, the pixel 13 indicated by the circle shows a bright state, and the pixel 13 without the circle indicates a dark state. When the liquid crystal display device 1 displays the single-line column inverted blinking pattern shown in FIG. 2 by the inversion driving method of the present invention, in the n+1th frame and the n+3th frame, the plurality of pixels 13 in the displayed bright state are Have A part of the applied voltage is positive polarity, and the other part is negative polarity. The brightness of the positive polarity pixel 13 and the brightness of the negative polarity pixel 13 are spatially compensated each other, so the brightness of the n+1th frame picture and the first The difference in brightness of the n frame picture is small, and the difference between the brightness of the n+3 frame picture and the brightness of the n+2 frame picture is small, so the picture changes from the nth frame to the n+1th frame and is n+2 When the frame picture changes to the n+3th frame, the human eye does not feel the change in the brightness of the n+1th frame and the n+3th frame, that is, the picture flickering is not seen.

Please refer to FIG. 14 , which is a schematic diagram showing the double line column inverted flashing pattern shown in FIG. 6 by using the liquid crystal display device 1 reverse driving method of the present invention. In Fig. 14, the pixel 13 indicated by the circle shows a bright state, and the pixel 13 without the circle indicates a dark state. When the liquid crystal display device 1 displays the two-line column inversion blinking pattern shown in FIG. 2 by the inversion driving method of the present invention, in the nth frame and the n+2th frame, the plurality of pixels 13 of the display bright state are present. Part of the applied voltage is positive polarity, and the other part is negative polarity. The brightness of the positive polarity pixel 13 and the brightness of the negative polarity pixel 13 are spatially compensated each other, so the difference between the brightness of the nth frame picture and the previous frame picture Very small, the brightness of the n+2th frame and the brightness of the n+1th frame are very small, so the picture changes from the previous frame to the nth frame and from the n+1th frame to the nth frame In the n+2th frame, the human eye does not feel the change in the brightness of the nth frame and the n+2th frame, that is, the flickering phenomenon is not seen.

Compared with the prior art, the timing controller 50 of the liquid crystal display device 1 of the present invention includes a memory 60. The memory 60 stores a program provided by an external system. The timing controller 50 reads the program stored in the memory 60 and generates a polarity inversion signal POL according to the received VSYNC signal and the HSYNC signal. The common voltage generating circuit 40 receives the polarity inversion signal No. POL, which in turn outputs a common voltage alternating between positive and negative polarity to the common electrode 16. The common voltage VCOM is in a period of two frames. In one cycle, the period of the pulse signal in each frame is different, and the period of the pulse signal of one frame is the scan applied to the scan line 11 by the scan driving circuit 20. The period of the pulse signal of the other frame is twice the period of the scanning signal applied to the scanning line 11 by the scan driving circuit 20. The data driving circuit 30 outputs a gray scale voltage signal Vn corresponding to the common voltage VCOM to the pixel electrode 15. Therefore, the driving method of the liquid crystal display device 1 of the present invention integrates the single-line column inversion driving method and the two-line column inversion driving method, so that the polarity of the voltage applied to the pixels 13 displaying the bright state in all the frame images is not all positive. Or negative polarity, so there is no difference in picture brightness between frames and frames or the difference in picture brightness exists only for part of the time. Therefore, the liquid crystal display device driving method of the present invention can improve the flickering phenomenon of the screen.

Referring to FIG. 15 and FIG. 16, FIG. 15 is a flowchart of a method for generating the second embodiment of the polarity inversion signal POL by the timing controller 50. FIG. 16 is a driving timing diagram of the second embodiment in which the timing controller 50 generates the polarity inversion signal POL. The method for the timing controller 50 to generate the polarity inversion signal POL includes the following steps: Step S21: Start.

Step S22: Count the VSYNC signal as n.

When the VSYNC signal received by the timing controller 50 changes from a low level 0 to a high level 1, the timing controller 50 counts the VSYNC signal according to the program stored in the memory 60, and sets the current VSYNC signal to be the first n.

Step S23: dividing the HSYNC signal by two to generate a pole Sexual reversal signal POL.

The timing controller 50 receives the HSYNC signal, and divides the HSYNC signal by two according to a program stored in the memory 60 to generate a polarity inversion signal POL, and outputs the divided level from high to low. The polarity of the polarity changes the signal POL to the common voltage generating circuit 40.

Step S24: determining whether the n+1th VSYNC signal is present. If yes, go to step S25; if no, go to step S23.

If the timing controller 50 determines that the n+1th VSYNC signal appears, that is, the liquid crystal display device 1 enters a new frame display screen, step S25 is performed; if the liquid crystal display device 1 does not enter a new frame display screen, Step S23 is performed.

Step S25: The VSYNC signal is counted as n+1.

Step S26: Divide the HSYNC signal by four to generate a polarity inversion signal POL.

The timing controller 50 receives the HSYNC signal, and divides the HSYNC signal by four according to a program stored in the memory 60 to generate a polarity inversion signal POL, and outputs the divided level from high to low. The polarity of the polarity changes the signal POL to the common voltage generating circuit 40.

Step S27: It is judged whether the n+2th VSYNC signal is present. If yes, go to step S28; if no, go to step S26.

Step S28: The VSYNC signal is counted as n+2.

Step S29: dividing the HSYNC signal by six to generate a polarity inversion signal POL.

The timing controller 50 receives the HSYNC signal, and according to the program stored in the memory 60, the HSYNC signal is divided by six. The polarity inversion signal POL is generated, and the polarity inversion signal POL whose frequency is periodically changed from low to high is output to the common voltage generating circuit 40.

Step S30: determining whether the n+3th VSYNC signal is present. If yes, go to step S22; if no, go to step S29.

If the timing controller 50 determines that the n+3th VSYNC signal appears, that is, the liquid crystal display device 1 enters a new frame display screen, step S22 is executed, and the timing controller 50 starts to generate the polarity inversion signal of the next cycle. POL; otherwise, the liquid crystal display device 1 does not enter the new frame display screen, and then step S29 is performed.

Please refer to FIG. 17 , which is a schematic diagram of the voltage polarity of the pixel 13 of the liquid crystal display panel 10 under the control of the polarity inversion signal POL shown in FIG. 16 . In the nth frame and the n+3th frame, the liquid crystal display device 1 adopts a single line column inversion driving method, and in the n+1th frame and the n+4th frame, the liquid crystal display device 1 adopts a double line column inversion driving method. In the n+2th frame and the n+5th frame, the liquid crystal display device 1 employs a three-line column inversion driving method. The nth frame to the n+2th frame are one cycle. The inversion driving method further integrates the three-line column inversion driving method, and the period thereof is extended, and each frame of the three-line column inversion driving method displays a portion of the pixel 13 in which the bright state is loaded with a positive polarity, and the other portion It is negative polarity. Therefore, the difference in brightness of the screen between the frame and the frame is further reduced, so that the liquid crystal display device 1 can further improve the flickering phenomenon of the screen.

The program stored in the memory 60 of the liquid crystal display device 1 of the present invention may have various other modifications. The inversion driving method of the liquid crystal display device 1 is changed by changing the program stored in the memory 60. By counting a plurality of times, the VSYNC signal is counted in turn, and the HSYNC signal is Performing frequency division and determining whether the VSYNC signal is 0 or not, and as long as the polarity inversion signal POL obtained by dividing the HSYNC signal in a period is non-periodically changed, the period of the polarity inversion signal POL is It can be extended, and the period of the corresponding common voltage can be extended to four cycles, five frames, six frames... as a cycle. Accordingly, the driving method of the liquid crystal display device 1 can further improve the flickering phenomenon of the screen.

The common pulse of two frames is a period, and the period of the pulse signal in each frame can also be twice and six times of the period of the scanning signal.

The common voltage of two frames is one cycle, and the period of the pulse signal in each frame can also be four times and six times of the period of the scanning signal.

The common voltage of three frames is one cycle, and the period of the pulse signal of two frames may be the same, but the waveform of the pulse signal in the two frames is inverted, and the period of the pulse signal in the other frame is within the period of the two frames. The period of the pulse signal can be different.

In summary, the present invention has indeed met the requirements of the invention, and has filed a patent application according to law. However, the above description is only the preferred embodiment of the present invention, and the scope of the present invention is not limited to the above-described embodiments, and equivalent modifications or variations made by those skilled in the art in light of the spirit of the present invention are It should be covered by the following patent application.

Liquid crystal display device ‧‧1

LCD panel ‧‧10

Scan drive circuit ‧‧20

Data drive circuit ‧ ‧ 30

Timing controller ‧ ‧ 50

Common voltage generating circuit ‧‧40

Memory ‧‧60

External circuit ‧‧70

Scanning line ‧‧11

Information line ‧‧12

Pixel ‧‧13

Thin film transistor ‧‧14

Public electrode ‧‧16

Pixel electrode ‧‧15

1 is a schematic diagram of a prior art single line column inversion driving method.

2 is a schematic diagram of a single-line column reverse flashing pattern of a liquid crystal display device using a single-line column inversion driving method.

Fig. 3 is a schematic diagram showing the single line column inverted flashing pattern shown in Fig. 2.

FIG. 4 is a schematic diagram of a two-line column inversion driving method.

FIG. 5 is a schematic diagram showing a liquid crystal display device displaying a single-line column inverted flashing pattern shown in FIG. 2 by a two-line column inversion driving method.

6 is a schematic diagram of a two-column inverted flashing pattern of a liquid crystal display device using a two-line column inversion driving method.

Fig. 7 is a schematic diagram showing the double line column inversion blinking pattern shown in Fig. 6.

Figure 8 is a block diagram showing the circuit of the liquid crystal display device of the present invention.

9 is a flow chart showing a method of the first embodiment of the polarity inversion signal POL generated by the timing controller of the liquid crystal display device shown in FIG.

FIG. 10 is a driving timing diagram of the first embodiment in which the timing controller generates the polarity inversion signal POL.

11 is a waveform diagram of driving signals of a liquid crystal display panel of the liquid crystal display device shown in FIG.

FIG. 12 is a schematic diagram showing voltage polarities of pixels of the liquid crystal display panel in the driving mode shown in FIG.

FIG. 13 is a schematic diagram showing the liquid crystal display device of FIG. 8 showing the single-line column inverted flashing pattern shown in FIG. 2 under the inversion driving method shown in FIG.

Fig. 14 is a schematic diagram showing the double line column inversion blinking pattern shown in Fig. 6 by the liquid crystal display device inversion driving method shown in Fig. 8.

FIG. 15 is a flow chart of a method for generating a second embodiment of the polarity inversion signal POL by the timing controller.

FIG. 16 is a driving timing diagram of the second embodiment in which the timing controller generates the polarity inversion signal POL.

Figure 17 is a diagram showing the voltage polarity of the pixels of the liquid crystal display panel under the control of the polarity inversion signal POL shown in Figure 16.

Liquid crystal display device ‧‧1

LCD panel ‧‧10

Scan drive circuit ‧‧20

Data drive circuit ‧ ‧ 30

Timing controller ‧ ‧ 50

Common voltage generating circuit ‧‧40

Memory ‧‧60

External circuit ‧‧70

Scanning line ‧‧11

Information line ‧‧12

Pixel ‧‧13

Thin film transistor ‧‧14

Public electrode ‧‧16

Pixel electrode ‧‧15

Claims (10)

A liquid crystal display device comprising: a liquid crystal display panel, the liquid crystal display panel comprising a plurality of data lines, a plurality of scan lines intersecting the data lines and a plurality of common electrodes; and a scan driving circuit for applying a series of scan signals to a scan line; a common voltage generating circuit for supplying a common voltage to the common electrode; and a data driving circuit for applying a complex gray scale voltage signal corresponding to the common voltage when the scan line is scanned To the data line; wherein the common voltage is a pulse signal with at least two frames as a period, and the pulse signal is periodically changed in each frame, and the common voltage is at least three different in one cycle. a pulse signal period, wherein the at least three different pulse signal periods include a first pulse signal that is twice the period of the scan signal, a second pulse signal that is four times the period of the scan signal, and a third pulse signal that is Six times the scan signal period. The liquid crystal display device of claim 1, wherein the duty ratio of the pulse signal of the common voltage is 50%. The liquid crystal display device of claim 2, further comprising a timing controller, wherein the common voltage is generated according to the timing controller generating a polarity inversion signal. The liquid crystal display device of claim 3, wherein the timing controller comprises a memory for storing a program provided by an external system, the timing controller is provided according to an external circuit. The sync signal and the vertical sync signal, and the program stored in the memory generate the polarity inversion signal, and output the polarity inversion signal to the common voltage generating circuit. The liquid crystal display device of claim 4, wherein the polarity inversion signal is a pulse signal with at least two frames as a period, and the pulse signal periodically changes in each frame, the polarity The inversion signal is in one cycle, including at least two different pulse signal periods. In each frame, the pulse signal period of the polarity inversion signal is an even multiple of the horizontal synchronization signal period, and the duty ratio is 50%. . The liquid crystal display device of claim 5, wherein when the polarity inversion signal received by the common voltage generating circuit is at a high level, it outputs a positive common voltage to the common electrode, and the common voltage generating circuit When the received polarity inversion signal is low, it outputs a negative common voltage to the common electrode. A liquid crystal display device comprising a liquid crystal display panel, the liquid crystal display panel comprising a plurality of data lines, a plurality of scan lines intersecting the data lines, and a plurality of common electrodes, the driving method comprising the steps of: (a Applying a series of scan signals to the scan line, the scan signal being a periodic pulse signal having a period of time for scanning the scan line of the column; (b) applying a common voltage to the common electrode; and (c) being applied to the liquid crystal display panel Applying a plurality of gray scale voltage signals corresponding to the common voltage to the data line during scanning; wherein the common voltage is a pulse signal with at least two frames as a period, and the pulse signal is periodically changed in each frame, and The public electricity Pressing in one cycle, including at least three different pulse signal periods, the at least three different pulse signal periods include a first pulse signal that is twice the period of the scan signal, and a second pulse signal is four times of the scan signal period. The multiple and a third pulse signal are six times the period of the scanning signal. The driving method of claim 7, wherein the duty ratio of the pulse signal of the common voltage is 50%. The driving method of claim 8, wherein the liquid crystal display device further comprises a timing controller, the step (b) of the driving method generating the common voltage before applying a common voltage to the common electrode. The driving method of claim 9, wherein the generating the common voltage further comprises: providing a horizontal synchronizing signal and a vertical synchronizing signal to the timing controller; generating a polarity according to the horizontal synchronizing signal and the vertical synchronizing signal Inverting the signal, wherein the polarity inversion signal is a pulse signal with at least two frames as a period, and the pulse signal is periodically changed in each frame, and the polarity inversion signal is in one cycle, including at least two different The pulse signal period, the period of the pulse signal of the polarity inversion signal is an even multiple of the horizontal synchronization signal period, that is, an even multiple of the scanning signal period, and the duty ratio is 50%; and according to the polarity The inversion signal produces the common voltage.