TWI404156B - Contour-detecting method for sawing lanes of a wafer - Google Patents

Abstract

A contour-detecting method for sawing lanes of a wafer includes the steps of: color processing; localizing sawing lines; energy transformation and analysis; localizing die walls; calculating die wall symmetries; measuring distances between die walls and sawing lines; measuring orientations of sawing lines.

Description

Wafer cutting trench profile detection method

The present invention relates to a method for detecting a profile of a wafer cutting trench; in particular, the present invention relates to a method for detecting a profile of a wafer cutting trench without prior collection or storage of sample training.

Referring to FIG. 1 , the semiconductor wafer [wafer] 1 has a plurality of dies 10 and a plurality of isolation trenches 11 . The trench 11 extends through the die 10 to properly isolate the peripheral edge of the die 10. The width of the trench is typically about 50 microns [micron], which acts as a sawing lane. The cutting track usually has three types: a cross lane 11a, a vertical lane 11b, and a horizontal lane 11c.

Generally, in the process of wafer sawing, the cutting machine has a wafer type, a wafer type, a feed speed, a knife speed. Factors such as knife type, knife power, and knife wear cause the cutting edge of the die to be irregular and determine the severity of the irregularity.

Under normal conditions, the wafer only has a slightly irregular cutting edge that does not exceed the width of the trench. Conversely, when a severely irregular cutting edge occurs on the wafer, the cutting edge extremely exceeds the width of the trench and causes cracks in the edges of the die.

In addition, the cutting machine uses deionized water to cool down during wafer cutting to ensure cutting quality and extended cutter life. In fact, deionized water may leave or adhere to the swarf particles produced by cutting, thus greatly reducing the cutting yield.

Figures 9a through 9d illustrate image views of various scribe line shapes produced by a semiconductor wafer during the dicing process. Figure 9a is a complete image of the shape of the cutting path, which is regarded as a good cutting path; Figure 9b is an image of a slightly damaged cutting path shape, the outer edge of the grain and the die wall are still intact, It is a normal cutting path; the 9th figure is an image of the shape of the cutting path with a severely damaged notch, and the outer edge of the damaged grain and the retaining wall (as indicated by the arrow) are regarded as abnormal cutting paths; It is an image of the shape of the cutting path with a severely damaged notch, and is too close to the retaining wall of the grain (as indicated by the marking circle), which is regarded as an abnormal cutting path.

Early traditional wafer defect inspection usually required the use of manual inspection methods. The inspectors used the naked eye to inspect the wafer through a high-magnification electron microscope and issued a warning of abnormal cutting. However, the use of the manual inspection method has the disadvantages of high labor cost and low inspection efficiency, and can cause misjudgment due to eye fatigue or lack of experience of the examiner.

In view of this, the traditional wafer defect inspection further utilizes a neural network-based inspection method to improve the shortcomings of manual inspection. However, in the process of establishing a classification mode, this test method has the disadvantages of requiring a large number of samples to be trained and learned in advance, requiring a large amount of learning, calculating time, and requiring a large-capacity computing device.

Although the neural network-based inspection method is used to improve the shortcomings of manual inspection, it still cannot meet the current wafer inspection requirements, in order to provide a lower cost and higher efficiency inspection method. Obviously, there is still a need for further improvements in wafer defect inspection to meet the aforementioned requirements.

Regarding semiconductor wafer dicing technology, it is also disclosed in the technical content of some domestic patents. For example, in the Republic of China Patent No. 476142, a method of cutting a wafer from a semiconductor wafer and a trench structure disposed on the dicing region are invented; and, in addition, a semiconductor wafer dicing technique is also disclosed in the section. The technical content of domestic patents. For example, the Republic of China Patent Publication No. 200839225, a high-resolution image capturing method for the surface defects on the edge of a wafer, the aforementioned patent of the Republic of China is only a reference to the technical background of the present invention and a description of the current state of the art. However, it is not intended to limit the scope of the invention.

Regarding semiconductor wafer dicing technology, it is also disclosed in the technical content of many national patents. For example, U.S. Patent No. 7,435,047, No. 74, 1988, No. 7,265, 034, No. 721, 1500, No. 70,710, 032, No. 70, 050, 053, No. 7054477, No. 7041579, No. 7005081, No. 6969669, No. 6821866, No. 6818550, No. 6,759,276, No. 6,672,163, No. 6,662,799, No. 6,620,228, No. 6,583,383, No. 6,576,567, No. 6,500047, No. 6421456, No. 6415698, No. 6367467, No. 6357330, No. 6295978 No. 6253758, No. 6253755, No. 6219910, No. 6112740, No. 6067977, No. 5960613, No. 5809987, No. 5387331, No. 6105567, No. 4,552,515, No. 4804641, No. 4779497, No. 4,696,712, 4,673,317, 4, 603, 609, and 4, 138, 430, and the like; US Patent and Patent Publication No. 20080311727, No. 20080261351, No. 20080258269, No. 20080184855, No. 20080176360, No. 20080153260, No. 20080121347 , No. 20080113492, No. 20080045124, No. 20080001259, No. 20070287266, No. 20070111481, No. 20070057349, No. 20070004175, No. 20070004174, No. 20060292828, No. 20060189100, No. 20060189099, No. 20060073676, No. 20060027531, No. 20060024922, No. 20050090076, No. 20050072766, No. 20040180513, No. 20040139601, No. 20040211611, No. 20040091141, No. 20040555634 No., No. 2004023470, No. 20030228739, No. 20030162313, No. 200303030130, No. 2003023, 494, No. 20030222508, No. 20020178883, No. 20020166428, No. 20020085746, No. 20020063115, No. 20020033171, No. 20010040152, No. 20010029938 and No. 20010002569. The above-mentioned U.S. patents and patent publications are only for the purpose of the present invention and are not intended to limit the scope of the present invention.

In view of the above, the present invention provides a method for detecting a profile of a wafer cutting trench, which uses a distance between a retaining wall and a cutting track to calculate a cutting trench profile to achieve a simplified detection process. Improve the efficiency of detection.

The main object of the present invention is to provide a method for detecting the contour of a wafer cutting trench, which uses a distance between the retaining wall and a cutting path to calculate a cutting ditch contour to achieve a simplified detection process and improve detection efficiency. .

In order to achieve the above object, the method for detecting a profile of a wafer cutting trench of the present invention comprises the steps of:

Color information pre-processing;

Ditch candidate area selection and location;

Energy conversion and analysis;

Anti-retaining wall positioning;

Measuring the distance between the retaining walls;

Anti-blocking wall distance symmetry;

Measure the distance between the retaining wall and the cutting path.

The preferred embodiment of the invention further comprises the step of measuring the course of the cutting track. The color information pre-processing of the preferred embodiment of the present invention includes converting the RGB color information of the image into the YC _b C _r color space, finding the ROI block, and binarizing the ROI block.

In a preferred embodiment of the present invention, a series of trench alignments are performed on the ROI block as the scribe lane candidate regions are positioned.

In the preferred embodiment of the present invention, image binarization processing is performed after energy conversion. The anti-retaining wall positioning of the preferred embodiment of the present invention includes: performing overall projection of the binarized image energy in the horizontal direction and the vertical direction; dividing the binarized image into eight regional positions; and locally projecting the eight regions.

In order to fully understand the present invention, the preferred embodiments of the present invention are described in detail below and are not intended to limit the invention.

The method for detecting the profile of a wafer dicing trench according to a preferred embodiment of the present invention is applicable to any dicing process of semiconductor wafers of various sizes, and is suitable for profile detection of various dicing trench shapes formed by the same, but the wafer size and The shape of the trench is not intended to limit the scope of application of the present invention.

FIG. 2 is a block diagram showing the flow of a method for detecting a profile of a wafer cutting trench according to a preferred embodiment of the present invention. Referring to FIG. 2, the method for detecting the contour of the wafer cutting trench according to the preferred embodiment of the present invention includes the steps of: color information pre-processing; selection and positioning of the candidate channel of the trench; energy conversion and analysis; positioning of the anti-retaining wall; The distance between the retaining walls; the symmetry of the retaining wall; measure the distance between the retaining wall and the cutting path.

FIG. 3 is a flow chart showing the contour detecting operation of the wafer cutting trench contour detecting method according to the preferred embodiment of the present invention. Referring to FIG. 3, a method for detecting a profile of a wafer dicing trench according to a preferred embodiment of the present invention performs color information pre-processing on the wafer image after inputting the wafer image. For example, the input image is divided into two regions, the first region is a trench [cutting channel] portion, and the portion of the wafer other than the trench is a second region, but it is not intended to limit the present invention.

The color information pre-processing includes converting the RGB color information of the image into the YC _b C _r color space, wherein the conversion between RGB and YC _b C _r can be performed by using equations (1), (2), and (3):

After the RGB color information is converted to the YC _b C _r color space, the spatial distribution of the color space parameters to the skin-like color distribution is adjusted, and the adjustment matrix can be solved by using equation (4):

The distribution range of the ditch is: 148< Y <252, -24< C _b <3,6< C _r <25, and the wafer distribution range is: 0< Y <217, -23< C _b <73,-4< C _r <57.

Next, based on equation (5) for detecting skin color, equation (6) is used to linearly cut the image of the trench region. The preferred embodiment of the invention uses equations (5) and (6) as:

To obtain a Region of Interest (ROI). The linearly cut image is subjected to binarization processing. The binarization process is to set the grayscale value of the white pixel in the ROI block to be equal to 0, and the grayscale value of the remaining pixels is equal to 255. Figure 10 discloses a preferred embodiment of the present invention for ROI block An image map of the binarization result.

Referring to FIG. 3 again, after the color information pre-processing, the number of candidate regions of the scribe line is calculated; when the number of candidate regions of the scribe lane is equal to 1, the subsequent steps can be performed; otherwise, the number of candidate regions for the scribe lane When it is equal to 0, the contour detection is stopped and the ditch abnormality is warned.

Figure 4 is a schematic diagram showing the use of a 10 x 10 grid cross-shaped template for dicing candidate region localization in accordance with a preferred embodiment of the present invention. Please refer to Figure 4, and then perform a series of trench matching on the ROI block with a 10×10 grid cross template when positioning the candidate area of the scribe line to execute the trench [cutting path] The location of the candidate region, but it is not intended to limit the invention. At this time, the sum of the binarized values is calculated using equation (7). The preferred embodiment of the invention uses equation (7) as:

Where C _n is the sum of the binarized values of the pixels included in the nth square, and L _N is the sum of the binarized values of the cells contained in the Nth L -shaped region.

Please refer to Figure 4 again. After dividing the template with a design size of 220×220 pixels into 10×10=100 cells, each cell has 22×22=484 pixels, and the number of pixels per cell is 22×22. The order value is subjected to an accumulation operation, and is marked in the center position of the template satisfying the decision rule of the equation (8). The preferred embodiment of the invention uses equation (8) as: L ₃ > L ₂ & L ₃ > L ₄ (8)

According to the template calculation principle, the binarization value of the ditch area is usually larger than the IC block. Therefore, the sum of the binarization values in each of the squares in the template is calculated, and the post-selection area of the cross ditch can be found and marked. The candidate areas of each dot mark are integrated, and the center of gravity of the area is calculated to locate the cross ditch [cutting path]. On the other hand, if the entire binarized image is compared through the template, no candidate region that meets the condition can be found, and the trench portion is abnormally cut and an abnormal warning is issued. [warning].

Please refer to Figure 3 again to perform energy conversion and analysis after positioning the candidate area of the scribe line. Figure 5 is a schematic diagram showing the processing of the trajectory candidate region in the preferred embodiment of the present invention using a 3 x 3 mask to process the gray image of the trench. Referring to Figure 5, the energy E ( x, y ) [Energy] of each pixel is calculated using equations (9) and (10):

Where ε is the mask average grayscale value, N is the number of mask pixels, x , y is the pixel coordinate position, G ( x , y ) is the pixel ( x , y ) gray scale value, and E ( x , y ) is Pixel ( x , y ) energy value.

Figure 11 is a diagram showing the result of calculating the energy of the grayscale image of the ditch in the preferred embodiment of the present invention.

The binarization process is performed using equation (11), and the energy binarized image B and its pixel dipolarization value B ( x , y ) are obtained.

Where B is the binarized image of energy, ( x , y ) is the pixel coordinate position, and B ( x , y ) is the binarized value of the pixel ( x , y ).

A pixel whose area energy is greater than or equal to a threshold value (Thresholding Value) of 255 is selected to have a grayscale value of 255; otherwise, the grayscale value is selected to be 0.

FIG. 12 is a view showing the result of binarizing the grayscale image energy of the trench in the preferred embodiment of the present invention.

Please refer to Figure 3 again to perform the anti-retaining wall positioning after energy conversion and analysis. In a preferred embodiment of the present invention, the binarized image energy is used to locate the anti-retaining wall in a region of the cutting path and the anti-retaining wall. The image is imaged (12) using the integral projection in the horizontal direction and the vertical direction (Integral projection), that is, the first projection, and the trajectory and the anti-retaining wall region are obtained by projecting the projection images of the binarized images in the horizontal direction and the vertical direction. The initial location. The preferred embodiment of the invention uses equation (12) as:

Where A is the image size, H ( y ) is the horizontal projection, Width is the width, V ( x ) is the vertical projection, and Height is the height.

Figure 13 is a diagram showing the result of horizontal projection of a binarized image in accordance with a preferred embodiment of the present invention. Figure 14 is a diagram showing the result of vertical projection of a binarized image in accordance with a preferred embodiment of the present invention.

FIG. 6 is a schematic diagram showing the positioning of the anti-retaining wall in the preferred embodiment of the present invention to divide the binarized image into eight regional positions and corresponding images. Referring to Figure 6, the eight regions are sub-projected, that is, the second projection. The cumulative distribution of projections for each region has two relatively high cumulative values, the cumulative magnitude of the relative position of the cutting lane to the retaining wall. The position of the cutting and anti-locking wall can be determined according to the corresponding coordinate position.

Please refer to Figure 3 again. After the energy conversion and analysis, measure the distance between the anti-retaining walls, that is, measure the width between the anti-blocking wall in the four directions of the cross ditch to the anti-blocking wall, and calculate the symmetry of the anti-blocking wall. Sex. The preferred embodiment of the present invention obtains four sets of anti-blocking wall distance: left anti-block wall distance ( W _L ), right anti-blocking wall distance ( W _R ), upper anti-blocking wall distance ( W _U ) and lower anti-blocking wall distance ( W _D ). Calculate the left and right group anti-blocking wall distance ratio R _h [as in equation (13)], the upper and lower groups of anti-blocking wall distance ratio R _v [as in equation (13)), if the ratio is between 0.94 and 1, the cutting is normal; Conversely, if the ratio is less than the critical value of 0.94, it is a cutting abnormality and alerts the ditches to anomalies. The preferred embodiment of the invention uses equation (13) as:

Where W _L is the left guard wall distance, W _R is the right guard wall distance, W _U is the upper guard wall distance, W _D is the lower guard wall distance, R _h is the left and right group anti-block wall distance ratio, R _v For the upper and lower groups, the anti-range wall distance ratio.

In addition, calculate the individual average values of the left and right anti-blocking wall distances and the upper and lower anti-blocking wall distances, and calculate the ratio R _{d of the} two groups of averages [as in equation (14)]. If the ratio is between 0.9 and 1, it is a cutting. Normal; if the ratio is less than 0.9, it is judged to be abnormal in cutting, and the ditches are warned. The preferred embodiment of the invention uses equation (14) as:

Where W _L is the left guard wall distance, W _R is the right guard wall distance, W _U is the upper guard wall distance, W _D is the lower guard wall distance, W _{H is} about the anti-block wall distance average, W _V up and down The group defense wall spacing is average, and R _d is the ratio of the average distance between the two groups of anti-blocking walls.

Referring to Figure 3 again, after measuring the distance between the retaining walls, measure the distance between the retaining wall and the cutting path. Figure 7 is a schematic view showing the preferred embodiment of the present invention for detecting the distance between the retaining wall and the cutting path by using adjacent grid elements. Referring to FIG. 7, adjacent grid cells are formed as eight adjacent [8-adiacency] according to the relationship between pixels and their adjacent pixels. It contains eight adjacent pixels P based on the four down, left, and right adjacent pixels and the four diagonal pixels of the pixel P, respectively, which coordinates :( x, y -1), ( x, y +1 ), ( x -1, y ), ( x +1, y ), ( x -1, y -1), ( x +1, y -1), ( x -1, y +1), ( x +1, y +1), expressed as N ₈ ( P ). The trajectory of the scribe track is tracked by eight adjacent adjacent grid elements, and the distance between the trajectory track to the adjacent retaining wall is calculated. When the cutting is normal, the width between the cutting path and the anti-blocking wall is greater than the critical width of 5 pixels; conversely, if the cutting is abnormal, the distance between the cutting path and the anti-blocking wall is inevitably reduced. If the distance is less than the minimum width of 5 pixels, Then the cutting abnormality is determined and the ditch abnormality is warned.

Referring to Figure 3, after measuring the distance between the retaining wall and the cutting path, measure the cutting path. The preferred embodiment of the present invention uses Least Squares Regression (LSR) when there are n data points ( x ₁ , y ₁ ), ( x ₂ , y ₂ ), ..., ( x _n , y _n ) The preferred embodiment of the present invention uses equations (15), equations (16), equations (17), and equations (18) of the linear model as:

f ( x )= ax + b (15)

θ=tan ^-1 ( a ) (18)

a is the slope of the linear model f ( x ),

b is the intercept of the linear model f ( x ),

θ is the tilt angle of the linear model f ( x ).

Figure 8 is a schematic diagram showing the least square regression line of a horizontal scribe line and a vertical scribe line obtained by least squares regression analysis in accordance with a preferred embodiment of the present invention. Referring first to FIG. 8, the trajectory of the horizontal and vertical scribe scribe line are input coordinate point of the equation (16) is obtained f (x) the slope a, the other (17) is obtained f (x) by the equation of intercept b . Furthermore, the slope a and the intercept b are substituted into the equation (15) to obtain two straight line equations in the horizontal direction and the vertical direction, that is, the least square regression line of the horizontal cutting line and the vertical cutting path. Next, the deflection angle θ in the horizontal direction and the vertical direction can be obtained by the equation (18). When the cutting is normal, the deflection angle θ of the cutting track is less than 1 degree; conversely, if the cutting angle is abnormal, the cutting angle θ is greater than 1 degree, and the cutting abnormality is determined, and the ditch abnormality is warned.

Referring to Figures 2 and 3, the present invention relates to a method for detecting a profile of a wafer cutting trench; in particular, the present invention relates to a profile inspection of a wafer cutting trench without prior collection or storage of sample training. method.

The foregoing preferred embodiments are merely illustrative of the invention and the technical features thereof, and the techniques of the embodiments can be carried out with various substantial equivalent modifications and/or alternatives; therefore, the scope of the invention is subject to the appended claims. The scope defined by the scope shall prevail.

1‧‧‧Semiconductor wafer

10‧‧‧ grain

11‧‧‧ Ditch

11a‧‧ cross channel

11b‧‧‧Vertical channel

11c‧‧‧ horizontal channel

Figure 1: Schematic diagram of a semiconductor wafer.

2 is a block diagram showing the flow of a method for detecting a profile of a wafer cutting trench according to a preferred embodiment of the present invention.

FIG. 3 is a flow chart showing the contour detecting operation of the wafer cutting trench profile detecting method according to the preferred embodiment of the present invention.

Fig. 4 is a schematic view showing the use of a 10 x 10 grid cross-shaped template for dicing candidate region positioning in a preferred embodiment of the present invention.

Fig. 5 is a schematic view showing the processing of the crater candidate region in the preferred embodiment of the present invention by using a 3x3 mask to process the grayscale image of the trench.

Figure 6 is a schematic diagram showing the positioning of the anti-retaining wall in the preferred embodiment of the present invention to divide the binarized image into eight regions and their corresponding images.

Figure 7: A preferred embodiment of the present invention uses adjacent grid cells to detect the distance between the retaining wall and the cutting track.

Figure 8 is a schematic diagram showing the least square regression line of a horizontal scribe line and a vertical scribe line using a least squares regression analysis in accordance with a preferred embodiment of the present invention.

Figures 9a to 9d: Image diagrams of various scribe line shapes produced by a semiconductor wafer during the dicing process.

Figure 10 is a view showing an image of a result of binarization processing of an ROI block in accordance with a preferred embodiment of the present invention.

Figure 11 is a diagram showing the result of obtaining the energy of the grayscale image of the ditch in the preferred embodiment of the present invention.

Fig. 12 is a view showing the result of binarizing the gray scale image energy of the ditch in the preferred embodiment of the present invention.

Figure 13: Horizontal projection of binarized images in accordance with a preferred embodiment of the present invention The resulting image.

Figure 14 is a diagram showing the result of vertical projection of a binarized image in accordance with a preferred embodiment of the present invention.

[No component symbol]

Claims (7)

A method for detecting a profile of a wafer cutting trench, comprising the steps of: color information pre-processing; selection and positioning of a candidate channel of a trench; energy conversion and analysis; positioning of a retaining wall; measuring a distance between the retaining walls; and measuring a retaining wall The distance from the cutting path. A method for detecting the contour of a wafer cutting trench, comprising steps; color information pre-processing; selection and positioning of candidate trench regions; energy conversion and analysis; positioning of anti-retaining wall; measuring distance between anti-retaining walls; And measure the distance between the retaining wall and the cutting path. According to the method for detecting the contour of a wafer cutting trench according to claim 1 or 2, the method further comprises the steps of: measuring the trend of the cutting channel. The method for detecting a contour of a wafer cutting trench according to claim 1 or 2, wherein the color information pre-processing includes converting the RGB color information of the image into the YC _b C _r color space, finding the ROI block and binarizing The ROI block is processed. The method for detecting a profile of a wafer cutting trench according to claim 1 or 2, wherein a plurality of trench alignments are performed on the ROI block when the candidate region of the scribe line is positioned. The method for detecting a profile of a wafer cutting trench according to claim 1 or 2, wherein after the energy conversion, image binarization processing is performed. The method for detecting a profile of a wafer cutting trench according to claim 1 or 2, wherein the positioning of the anti-retaining wall comprises: projecting the binarized image energy in a horizontal direction and a vertical direction; and binarizing the image Eight area locations are divided; eight areas are partially projected.