TWI404150B - Bonding pad flatten method for bumping structure package feasibility improvement - Google Patents
Bonding pad flatten method for bumping structure package feasibility improvement Download PDFInfo
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- TWI404150B TWI404150B TW099134707A TW99134707A TWI404150B TW I404150 B TWI404150 B TW I404150B TW 099134707 A TW099134707 A TW 099134707A TW 99134707 A TW99134707 A TW 99134707A TW I404150 B TWI404150 B TW I404150B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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Abstract
Description
本發明係有關一種晶圓製程,特別是關於一種晶圓級構裝的凸塊製程(bumping)。This invention relates to a wafer process, and more particularly to a bumping process for a wafer level package.
在晶圓級構裝時,因晶圓表面的地形起伏或後鈍化層(re-passivation layer)塗佈而造成電鍍後的共平面性不好,而共平面性不好會造成後續的打線封裝或壓合封裝的困難。如圖1所示,習知的凸塊製程係在鋁墊10上直接成長凸塊16,而鋁墊10的邊緣有晶圓鈍化層12及後鈍化層14形成的峭壁,因此在電鍍後,凸塊16的邊緣會有高聳的凸起18。此凸塊16應用在打線封裝時,如圖2所示,凸起18會影響打線窗,造成接合線20無法勞固結合在凸塊16上,因而降低良率。凸塊16應用在壓合封裝時,如圖3所示,係藉施壓使凸塊16壓碎面板22上的導電膠24中的導電粒子,以達成與面板22上的線路的電性連接,但凸塊16的表面平坦度不佳造成導電粒子被壓碎的比率降低,因而降低良率。已知的解決方案有修改頂層金屬佈局(top metal layout)、更動晶圓鈍化層12之前的製程、更動頂層金屬的參數模型(SPICE model)、加大鋁墊10的面積及使用較細的接合線20,但這些都會產生其他的缺點或有無法克服的困難。例如,加大鋁墊10的面積會增加晶粒(die)的面積,較細的接合線20無法承受大電流,不能應用在電源接合墊上。At the wafer level, the coplanarity after plating is not good due to the topography of the wafer surface or the re-passivation layer coating, and the poor coplanarity will cause subsequent wire bonding. Or the difficulty of pressing the package. As shown in FIG. 1, the conventional bump process directly grows the bumps 16 on the aluminum pad 10, and the edge of the aluminum pad 10 has a cliff formed by the wafer passivation layer 12 and the back passivation layer 14, so that after plating, The edges of the bumps 16 have raised protrusions 18. When the bump 16 is applied to the wire bonding package, as shown in FIG. 2, the protrusion 18 affects the wire drawing window, so that the bonding wire 20 cannot be firmly bonded to the bump 16, thereby reducing the yield. When the bumps 16 are applied in the press-fit package, as shown in FIG. 3, the bumps 16 are pressed to crush the conductive particles in the conductive paste 24 on the panel 22 to achieve electrical connection with the wires on the panel 22. However, the poor surface flatness of the bumps 16 causes the ratio of the conductive particles to be crushed to be lowered, thereby lowering the yield. Known solutions include modifying the top metal layout, changing the process before the wafer passivation layer 12, changing the SPICE model of the top layer metal, increasing the area of the aluminum pad 10, and using finer joints. Line 20, but these all have other shortcomings or insurmountable difficulties. For example, increasing the area of the aluminum pad 10 increases the area of the die, and the thinner bonding wire 20 cannot withstand large currents and cannot be applied to the power pad.
有厚金屬(大於3μm)需求的產品,為了降低電阻值而增加凸塊16的厚度,導致凸塊18的表面平坦度更差,因此後續封裝的難度也越高。In the case of a product having a thick metal (greater than 3 μm), the thickness of the bump 16 is increased in order to lower the resistance value, resulting in a worse surface flatness of the bump 18, so that the difficulty of subsequent packaging is also higher.
後鈍化層14很厚,因此很難降低前述凸塊16的不平坦表面引起的問題。具有再佈線層(Re-Distribution Layer;RDL)的產品有超過99%需要後鈍化層14,因此也很難避免前述凸塊16的不平坦表面引起的困難。The rear passivation layer 14 is thick, so that it is difficult to reduce the problems caused by the uneven surface of the aforementioned bumps 16. A product having a Re-Distribution Layer (RDL) has more than 99% requiring a post-passivation layer 14, and thus it is also difficult to avoid the difficulty caused by the uneven surface of the aforementioned bump 16.
本發明的目的之一,在於提出一種晶圓級構裝的凸塊製程。One of the objects of the present invention is to provide a bump process for wafer level fabrication.
本發明的目的之一,在於提出一種改善凸塊結構封裝可行性的接合墊平坦化製程。One of the objects of the present invention is to provide a bond pad planarization process that improves the feasibility of bump structure packaging.
根據本發明,一種改善凸塊結構封裝可行性的接合墊平坦化製程包括在焊墊上依序濺鍍障礙層及種子層,在該種子層上形成厚金屬層,研磨該厚金屬層以形成平坦化金屬膜,在該銲墊上方的該平坦化金屬膜覆蓋光阻,以該光阻為蝕刻罩依序蝕刻該種子層及障礙層,以及去除該光阻後在該平坦化金屬膜上成長凸塊。According to the present invention, a bonding pad planarization process for improving the feasibility of a bump structure package includes sequentially sputtering a barrier layer and a seed layer on a pad, forming a thick metal layer on the seed layer, and grinding the thick metal layer to form a flat a metal film, the planarized metal film over the solder pad covers the photoresist, and the seed layer and the barrier layer are sequentially etched by using the photoresist as an etching mask, and the photoresist is removed and grown on the planarized metal film. Bump.
根據本發明,一種改善凸塊結構封裝可行性的接合墊平坦化製程包括在焊墊上依序濺鍍障礙層及種子層,在該種子層上形成厚金屬層,研磨該厚金屬層以形成平坦化金屬膜,在該平坦化金屬膜上覆蓋光阻,但曝露該銲墊上方的區域,在該曝露的區域成長凸塊,去除該光阻,以及以該凸塊為蝕刻罩依序蝕刻該種子層及障礙層。According to the present invention, a bonding pad planarization process for improving the feasibility of a bump structure package includes sequentially sputtering a barrier layer and a seed layer on a pad, forming a thick metal layer on the seed layer, and grinding the thick metal layer to form a flat a metal film covering the photoresist on the planarized metal film, but exposing a region above the pad, growing a bump in the exposed region, removing the photoresist, and sequentially etching the bump as an etch mask Seed layer and barrier layer.
本發明在形成平坦化金屬膜後,再於其上成長凸塊,因此大幅提昇凸塊的平整性,有助於增加封裝製程的可行性及良率。After forming the planarized metal film, the present invention further grows the bumps thereon, thereby greatly improving the flatness of the bumps, and contributing to the feasibility and yield of the packaging process.
圖4A到圖4H係第一實施例的流程圖。在完成晶圓的前段製程後,如圖4A所示,晶圓鈍化層12及後鈍化層14覆蓋在晶圓上,只曝露銲墊10,銲墊10通常是鋁。要製作接合墊時,如圖4B所示,依序濺鍍障礙層262及種子層264。障礙層262可為鈦(Ti)、鈦化鎢(TiW)或鉻(Cr),厚度介於250A~4000A。種子層264可為銅(Cu)或金(Au),厚度介於1000A~5000A。到此為止和習知技術是一樣的。接著在種子層264上電鍍銅或金的厚金屬層30,成為圖4C所示的結構。較佳者,厚金屬層30的厚度大於3μm。然後化學機械研磨(Chemical Mechanical Polishing;CMP)厚金屬層30的表面,成為圖4D所示的平坦化金屬膜32。接著如圖4E所示,以黃光製程在銲墊10上方的平坦化金屬膜32上形成光阻34作為蝕刻罩,以銅蝕刻或金蝕刻製程去除殘餘的種子層28,之後再以鈦、鈦化鎢或鉻蝕刻製程去除障礙層262,成為圖4F所示的結構。去除光阻34後如圖4G所示,再從平坦化金屬膜32成長凸塊36,如圖4H所示。凸塊製程已是相當熟知的技術,故不再詳述。4A to 4H are flowcharts of the first embodiment. After the wafer front-end process is completed, as shown in FIG. 4A, the wafer passivation layer 12 and the post-passivation layer 14 are overlaid on the wafer, and only the pad 10 is exposed. The pad 10 is typically aluminum. When the bonding pad is to be formed, as shown in FIG. 4B, the barrier layer 262 and the seed layer 264 are sequentially sputtered. The barrier layer 262 may be titanium (Ti), titanium tungsten (TiW) or chromium (Cr), and has a thickness of 250A to 4000A. The seed layer 264 can be copper (Cu) or gold (Au) with a thickness between 1000A and 5000A. So far, it is the same as the conventional technology. Next, a thick metal layer 30 of copper or gold is plated on the seed layer 264 to have the structure shown in Fig. 4C. Preferably, the thickness of the thick metal layer 30 is greater than 3 μm. Then, the surface of the thick metal layer 30 is chemically mechanically polished (CMP) to form the planarized metal film 32 shown in FIG. 4D. Next, as shown in FIG. 4E, a photoresist 34 is formed on the planarization metal film 32 above the pad 10 as an etching mask by a yellow light process, and the residual seed layer 28 is removed by a copper etching or gold etching process, followed by titanium, The titanium oxide or chromium etching process removes the barrier layer 262 to form the structure shown in FIG. 4F. After the photoresist 34 is removed, as shown in FIG. 4G, the bump 36 is grown from the planarization metal film 32 as shown in FIG. 4H. The bump process is a well-known technique and will not be described in detail.
凸塊36應用在打線封裝時,如圖5所示,因為凸塊36的表面相當平坦,所以有較寬的窗供打線,增加打線封裝的可行性。When the bump 36 is applied to the wire bonding package, as shown in FIG. 5, since the surface of the bump 36 is relatively flat, a wider window is provided for wire bonding, which increases the feasibility of the wire bonding package.
凸塊36應用在壓合封裝時,如圖6所示,因為凸塊36的表面相當平坦,所以可以充分壓碎導電膠24中的導電粒子,增加壓合封裝的可行性及良率。When the bump 36 is applied to the press-fit package, as shown in FIG. 6, since the surface of the bump 36 is relatively flat, the conductive particles in the conductive paste 24 can be sufficiently crushed to increase the feasibility and yield of the press-fit package.
圖7A到圖7H係第二實施例的流程圖,其中前四個步驟與圖4A到圖4D的步驟相同,但本實施例在CMP後經黃光製程覆蓋光阻34並直接進行金凸塊、銅凸塊或後鈍化層導線再重佈的圖樣化,如圖7E所示,光阻34只曝露銲墊10上方的平坦化金屬膜32,跟著如圖7F所示,在平坦化金屬膜32上成長銅或金凸塊36。較佳者,凸塊36的厚度大於3μm。接著去除光阻34,如圖7G所示,再以凸塊36為蝕刻罩施行蝕刻製程去除殘餘的種子層28及障礙層262,成為圖7H所示的結構。此凸塊36的表面相當平坦,因此增加封裝製程的可行性及良率,如圖5及圖6所示。7A to 7H are flowcharts of the second embodiment, wherein the first four steps are the same as the steps of FIGS. 4A to 4D, but the present embodiment covers the photoresist 34 by a yellow light process after CMP and directly performs gold bumps. The pattern of the copper bump or the post-passivation layer conductor is redistributed. As shown in FIG. 7E, the photoresist 34 exposes only the planarization metal film 32 over the bonding pad 10, as shown in FIG. 7F, in the planarization metal film. 32 copper or gold bumps 36 are grown. Preferably, the thickness of the bump 36 is greater than 3 μm. Then, the photoresist 34 is removed, and as shown in FIG. 7G, the etching process is performed by using the bump 36 as an etching mask to remove the residual seed layer 28 and the barrier layer 262, and the structure shown in FIG. 7H is obtained. The surface of the bump 36 is relatively flat, thus increasing the feasibility and yield of the packaging process, as shown in FIGS. 5 and 6.
如上述流程所示,本發明的方法毋須特別修改頂層金屬佈局,也毋須更動晶圓鈍化層12之前的製程或頂層金屬的參數模型,對於支援大電流的接合墊應用也不必特別加大銲墊10的尺寸。As shown in the above process, the method of the present invention does not require special modification of the top metal layout, and it is not necessary to change the process model of the wafer passivation layer 12 or the top metal model. It is not necessary to particularly increase the pad for the bonding pad application supporting high current. 10 size.
以上對於本發明之較佳實施例所作的敘述係為闡明之目的,而無意限定本發明精確地為所揭露的形式,基於以上的教導或從本發明的實施例學習而作修改或變化是可能的,實施例係為解說本發明的原理以及讓熟習該項技術者以各種實施例利用本發明在實際應用上而選擇及敘述,本發明的技術思想企圖由以下的申請專利範圍及其均等來決定。The above description of the preferred embodiments of the present invention is intended to be illustrative, and is not intended to limit the scope of the invention to the disclosed embodiments. It is possible to make modifications or variations based on the above teachings or learning from the embodiments of the present invention. The embodiments are described and illustrated in the practical application of the present invention in various embodiments, and the technical idea of the present invention is intended to be equivalent to the scope of the following claims. Decide.
10...銲墊10. . . Solder pad
12...晶圓鈍化層12. . . Wafer passivation layer
14...後鈍化層14. . . Post passivation layer
16...凸塊16. . . Bump
18...凸起18. . . Bulge
20...接合線20. . . Bonding wire
22...面板twenty two. . . panel
24...導電膠twenty four. . . Conductive plastic
262...障礙層262. . . Barrier layer
264...種子層264. . . Seed layer
30...厚金屬層30. . . Thick metal layer
32...平坦化金屬膜32. . . Flattening metal film
34...光阻34. . . Photoresist
36...凸塊36. . . Bump
圖1係習知的凸塊結構;Figure 1 is a conventional bump structure;
圖2係圖1的凸塊應用在打線封裝的示意圖;2 is a schematic view showing the application of the bump of FIG. 1 in a wire bonding package;
圖3係圖1的凸塊應用在壓合封裝的示意圖;3 is a schematic view showing the application of the bump of FIG. 1 in a press-fit package;
圖4A到圖4H係本發明的第一實施例的流程圖;4A to 4H are flowcharts of a first embodiment of the present invention;
圖5係本發明的凸塊應用在打線封裝的示意圖;5 is a schematic view showing the application of the bump of the present invention in a wire bonding package;
圖6係本發明的凸塊應用在壓合封裝的示意圖;以及Figure 6 is a schematic view showing the application of the bump of the present invention to a press-fit package;
圖7A到圖7H係本發明的第二實施例的流程圖。7A through 7H are flowcharts of a second embodiment of the present invention.
10...銲墊10. . . Solder pad
12...晶圓鈍化層12. . . Wafer passivation layer
14...後鈍化層14. . . Post passivation layer
20...接合線20. . . Bonding wire
262...障礙層262. . . Barrier layer
32...平坦化金屬膜32. . . Flattening metal film
36...凸塊36. . . Bump
Claims (8)
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Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
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TW200737454A (en) * | 2006-03-16 | 2007-10-01 | Advanced Semiconductor Eng | Method for forming metal bumps |
TW201023279A (en) * | 2008-12-11 | 2010-06-16 | Powertech Technology Inc | Wafer structure with conductive bumps and fabrication method thereof |
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TW200737454A (en) * | 2006-03-16 | 2007-10-01 | Advanced Semiconductor Eng | Method for forming metal bumps |
TW201023279A (en) * | 2008-12-11 | 2010-06-16 | Powertech Technology Inc | Wafer structure with conductive bumps and fabrication method thereof |
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