TWI399922B - Power supply system for motherboard - Google Patents

Power supply system for motherboard Download PDF

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Publication number
TWI399922B
TWI399922B TW97115307A TW97115307A TWI399922B TW I399922 B TWI399922 B TW I399922B TW 97115307 A TW97115307 A TW 97115307A TW 97115307 A TW97115307 A TW 97115307A TW I399922 B TWI399922 B TW I399922B
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Taiwan
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power supply
motherboard
pin
transistor
south bridge
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TW97115307A
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Chinese (zh)
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TW200945777A (en
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Hua Zou
Feng-Long He
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Hon Hai Prec Ind Co Ltd
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Priority to TW97115307A priority Critical patent/TWI399922B/en
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Publication of TWI399922B publication Critical patent/TWI399922B/en

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Description

主機板供電系統 Motherboard power supply system

本發明係關於一種主機板供電電路,特別係關於一種電腦主機板上可方便清除南橋晶片中之CMOS資料之供電系統。 The invention relates to a power supply circuit for a motherboard, in particular to a power supply system for conveniently removing CMOS data in a south bridge chip on a computer motherboard.

電腦主機板上之供電電路通常利用跳線來清除南橋晶片中之CMOS資料或者恢復BIOS設置,使得用戶在忘記CMOS密碼或者BIOS設置無法啟動電腦時可啟動電腦。電腦主機板上最常見的是一種鍵帽式跳線,鍵帽式跳線由底座和鍵帽組成。跳線之底座上設置有複數不連通之引腳,相鄰之兩根引腳之間可透過跳線之鍵帽電性連接以實現特定之連接關係。在電腦正常工作之情況下,鍵帽被安裝在底座上之兩個特定引腳之間以實現供電電路對南橋晶片之正常供電,保證南橋晶片中之CMOS資料不會丟失。當電腦設置出現故障時,用戶可將鍵帽從底座上取下並安裝在另外兩個引腳之間以清除南橋晶片中之CMOS資料。這就需要拆開機箱,找到清除CMOS資料之跳線位置,再進行跳線操作,給用戶帶來極大之不便。 The power supply circuit on the computer motherboard usually uses jumpers to clear the CMOS data in the south bridge chip or restore the BIOS settings, so that the user can start the computer when the CMOS password is forgotten or the BIOS setting cannot start the computer. The most common type on a computer motherboard is a keycap jumper. The keycap jumper consists of a base and a keycap. A plurality of pins that are not connected are disposed on the base of the jumper, and the adjacent two pins are electrically connected through the jumper of the jumper to achieve a specific connection relationship. In the normal working condition of the computer, the key cap is installed between the two specific pins on the base to realize the normal power supply of the south bridge chip by the power supply circuit, and the CMOS data in the south bridge chip is not lost. When the computer settings fail, the user can remove the keycap from the base and install it between the other two pins to clear the CMOS data in the south bridge chip. This requires disassembling the chassis, finding the location of the jumper to clear the CMOS data, and then performing the jumper operation, which brings great inconvenience to the user.

鑒於以上內容,有必要提供一種主機板供電系統,可方便用戶清除南橋晶片中之CMOS資料。 In view of the above, it is necessary to provide a motherboard power supply system, which is convenient for the user to clear the CMOS data in the south bridge chip.

一種主機板供電系統,包括給一南橋晶片供電之一電源電路及一控制電路,該電源電路之輸入端連接一電源供應器,該電源電路之輸出端連接該南橋晶片之一重定端,該控制電路包括一第一電晶體及一第二電晶體,該第一電晶體之第一端用於接收南橋晶片之一控制訊號,該第二電晶體之第一端連接該第一電晶體之第二端,該第二電晶體之第二端連接該南橋晶片之重定端,該第一、第二電晶體之第三端均接地,主機板正常工作時,該控制訊號處於第一邏輯狀態,使該第二電晶體之第二端為高電平,當需要清除主機板之CMOS資料時,該控制訊號處於第二邏輯狀態,使該第二電晶體之第二端以及南橋晶片之重定端為低電平,來清除主機板之CMOS資料。 A motherboard power supply system includes a power supply circuit for supplying power to a south bridge chip and a control circuit, wherein an input end of the power supply circuit is connected to a power supply, and an output end of the power supply circuit is connected to one of the reset ends of the south bridge chip, the control The circuit includes a first transistor and a second transistor, the first end of the first transistor is configured to receive a control signal of the south bridge chip, and the first end of the second transistor is coupled to the first transistor The second end of the second transistor is connected to the re-set end of the south bridge chip, and the third ends of the first and second transistors are grounded. When the motherboard is working normally, the control signal is in the first logic state. The second end of the second transistor is at a high level. When the CMOS data of the motherboard needs to be cleared, the control signal is in a second logic state, so that the second end of the second transistor and the re-set end of the south bridge chip Low level to clear the CMOS data of the motherboard.

該主機板供電系統透過電源電路給南橋晶片提供持續之供電,還透過南橋晶片之控制訊號來控制兩個電晶體之導通及截止,來清除CMOS資料,避免了拆開機箱等繁瑣之步驟,給用戶帶來了方便。 The motherboard power supply system provides continuous power supply to the south bridge chip through the power supply circuit, and controls the turn-on and turn-off of the two transistors through the control signal of the south bridge chip to clear the CMOS data, thereby avoiding cumbersome steps such as opening the chassis, The user brings convenience.

10‧‧‧電源電路 10‧‧‧Power circuit

V‧‧‧直流電源 V‧‧‧DC power supply

20‧‧‧濾波電路 20‧‧‧Filter circuit

Q1、Q2‧‧‧MOSFET Q1, Q2‧‧‧ MOSFET

40‧‧‧跳線 40‧‧‧jumper

RTCRST‧‧‧重定端 RTCRST‧‧‧Reposition

C1、C2‧‧‧電容 C1, C2‧‧‧ capacitor

Vcc‧‧‧電源供應器 Vcc‧‧‧Power supply

D1‧‧‧肖特基二極體 D1‧‧‧Schottky diode

30‧‧‧控制電路 30‧‧‧Control circuit

GPIO_CLRCMOS‧‧‧引腳 GPIO_CLRCMOS‧‧‧ pin

41-43‧‧‧引腳 41-43‧‧‧ Pin

R1-R4‧‧‧電阻 R1-R4‧‧‧ resistance

圖1係本發明主機板供電系統較佳實施方式之電路圖。 1 is a circuit diagram of a preferred embodiment of a power supply system for a motherboard of the present invention.

請參閱圖1,本發明主機板供電系統用於給電腦主機板上之南橋晶片供電,確保南橋晶片中之CMOS(Complementary Metal Oxide Semiconductor)資料不會因斷電而丟失,同時在用戶需要恢復電腦設置時可方便清除CMOS資料。該主機 板供電系統之較佳實施方式包括一電源電路10、一濾波電路20、一控制電路30及一跳線40,該跳線40具有三個引腳41,42及43,該電源電路10透過該濾波電路20給南橋晶片供電,該電源電路10還透過該濾波電路20連接到該跳線40之引腳42,該跳線40之引腳41接地,該跳線40之引腳43懸空,該跳線40之引腳42連接該南橋晶片之一重定端RTCRST。 Referring to FIG. 1, the motherboard power supply system of the present invention is used to supply power to the south bridge chip on the computer motherboard, ensuring that the CMOS (Complementary Metal Oxide Semiconductor) data in the south bridge chip is not lost due to power failure, and the user needs to recover the computer. It is easy to clear CMOS data when setting. The host A preferred embodiment of the board power supply system includes a power circuit 10, a filter circuit 20, a control circuit 30, and a jumper 40. The jumper 40 has three pins 41, 42 and 43 through which the power circuit 10 passes. The filter circuit 20 supplies power to the south bridge chip. The power supply circuit 10 is further connected to the pin 42 of the jumper 40 through the filter circuit 20. The pin 41 of the jumper 40 is grounded, and the pin 43 of the jumper 40 is suspended. A pin 42 of the jumper 40 is connected to one of the south bridge wafers RTCRST.

該電源電路10包括肖特基二極體D1,電阻R1及直流電源V,該肖特基二極體D1包括一第一陽極1,一第二陽極2及一陰極3,該肖特基二極體D1之第一陽極1連接到一電源供應器Vcc,第二陽極2透過電阻R1連接到該直流電源V,該肖特基二極體D1之陰極3連接濾波電路20之輸入端。 The power supply circuit 10 includes a Schottky diode D1, a resistor R1 and a DC power supply V. The Schottky diode D1 includes a first anode 1, a second anode 2 and a cathode 3. The Schottky II The first anode 1 of the polar body D1 is connected to a power supply Vcc, and the second anode 2 is connected to the direct current power supply V through a resistor R1. The cathode 3 of the Schottky diode D1 is connected to the input end of the filter circuit 20.

該濾波電路20包括電阻R2,電容C1及C2。該電容C1之一端作為該濾波電路2之輸入端,連接該肖特基二極體D1之陰極,還透過串聯連接之電阻R2以及電容C2接地,該電阻R2與電容C2之連接節點作為該濾波電路20之輸出端,連接該跳線40之引腳42。 The filter circuit 20 includes a resistor R2 and capacitors C1 and C2. One end of the capacitor C1 serves as an input end of the filter circuit 2, and is connected to the cathode of the Schottky diode D1, and is also grounded through a resistor R2 and a capacitor C2 connected in series. The connection node of the resistor R2 and the capacitor C2 serves as the filter. The output of circuit 20 is connected to pin 42 of jumper 40.

該控制電路30包括兩MOS(Metal Oxide Semiconductor)型場效應電晶體(MOSFET)Q1及Q2,以及電阻R3及R4,該MOSFET Q1及Q2均為N通道MOSFET,該MOSFET Q1之閘極作為該控制電路30之輸入端,連接至南橋晶片中通用輸入輸出埠(GPIO)之一引腳GPIO_CLRCMOS,該MOSFET Q1之閘極還透過電阻R3連接至該電源供應器Vcc,該MOSFET Q1之汲極連接該MOSFET Q2之閘極,該MOSFET Q2之閘極透過電阻R4連 接至該電源供應器Vcc,該MOSFET Q2之汲極作為該控制電路30之輸出端,連接該電阻R2與電容C2之連接節點,該MOSFET Q1及Q2之源極均接地。該GPIO可透過編程BIOS來控制。作為其他實施方式,該MOSFET Q1及Q2也可為NPN(Negative-Positive-Negative)型電晶體,該NPN型電晶體之基極、集極及射極之連接方式分別與MOSFET之閘極、汲極及源極之連接方式相同。 The control circuit 30 includes two MOS (Metal Oxide Semiconductor) field effect transistors (MOSFETs) Q1 and Q2, and resistors R3 and R4. The MOSFETs Q1 and Q2 are N-channel MOSFETs, and the gate of the MOSFET Q1 serves as the control. The input end of the circuit 30 is connected to one of the general-purpose input/output port (GPIO) pins GPIO_CLRCMOS of the south bridge chip, and the gate of the MOSFET Q1 is also connected to the power supply Vcc through the resistor R3, and the drain of the MOSFET Q1 is connected to the gate Gate of MOSFET Q2, the gate of MOSFET Q2 is connected through resistor R4 Connected to the power supply Vcc, the drain of the MOSFET Q2 serves as the output end of the control circuit 30, and is connected to the connection node of the resistor R2 and the capacitor C2. The sources of the MOSFETs Q1 and Q2 are both grounded. The GPIO can be controlled by programming the BIOS. In other embodiments, the MOSFETs Q1 and Q2 may also be NPN (Negative-Positive-Negative) type transistors. The base, collector and emitter of the NPN transistor are connected to the gate and the MOSFET respectively. The connection between the pole and the source is the same.

當電腦正常工作時,電源供應器Vcc透過肖特基二極體D1輸出電源給南橋晶片之重定端RTCRST,給南橋晶片供電,在電腦主機斷電時,電源供應器Vcc無輸出,此時直流電源V經電阻R1及肖特基二極體D1輸出電源,給南橋晶片供電,濾波電路20可濾除電源訊號傳輸過程中所產生之雜波,消除雜波訊號對南橋晶片之影響,其可省略。 When the computer is working normally, the power supply Vcc transmits power to the re-terminal RTCRST of the south bridge chip through the Schottky diode D1 output power, and supplies power to the south bridge chip. When the computer mainframe is powered off, the power supply Vcc has no output. The power supply V is powered by the resistor R1 and the Schottky diode D1 to supply power to the south bridge chip. The filter circuit 20 can filter out the clutter generated during the power signal transmission process, and eliminate the influence of the clutter signal on the south bridge chip. Omitted.

在電腦正常工作時,該跳線40之引腳42透過一鍵帽與引腳43相連,該GPIO之引腳GPIO_CLRCMOS呈現高阻態,MOSFET Q1導通,MOSFET Q2截止,MOSFET Q2之汲極呈現高電平。當用戶需要清空南橋晶片中CMOS資料時,可透過跳線方式,即將鍵帽取下後重新安裝在引腳41及42上,使引腳42接地而呈現低電平,以清空南橋晶片中之CMOS資料;還可進入BIOS,修改BIOS中對該GPIO之引腳GPIO_CLRCMOS之電平之設置,使GPIO之引腳GPIO_CLRCMOS呈現低電平,進而使MOSFET Q1截止,MOSFET Q2導通,MOSFET Q2之汲極呈現低電平,使該南橋晶片之重定端RTCRST為低電平,以清空南橋晶片中 CMOS資料,可進一步在電腦鍵盤上設置熱鍵,以直接啟動BIOS對該GPIO之引腳GPIO_CLRCMOS電平設置之控制。 When the computer is working normally, the pin 42 of the jumper 40 is connected to the pin 43 through a keycap. The GPIO pin GPIO_CLRCMOS exhibits a high impedance state, the MOSFET Q1 is turned on, the MOSFET Q2 is turned off, and the drain of the MOSFET Q2 is high. Level. When the user needs to clear the CMOS data in the south bridge chip, the jumper can be removed by re-installing on the pins 41 and 42 to make the pin 42 grounded to a low level to clear the south bridge chip. CMOS data; can also enter the BIOS, modify the BIOS setting of the GPIO pin GPIO_CLRCMOS level, so that the GPIO pin GPIO_CLRCMOS is low, so that MOSFET Q1 is turned off, MOSFET Q2 is turned on, MOSFET Q2 is bungee Presenting a low level, causing the re-terminal RTCRST of the south bridge wafer to be low to clear the south bridge wafer CMOS data, you can further set the hotkey on the computer keyboard to directly start the BIOS to control the GPIO_CLRCMOS level setting of the GPIO pin.

本發明主機板供電系統既保留了用跳線清除南橋晶片中CMOS資料之方式,還可使用戶選擇熱鍵之方式,避免在需要清除南橋晶片中CMOS資料時拆開機箱,給用戶帶來了方便。 The power supply system of the motherboard of the invention not only retains the manner of using the jumper to clear the CMOS data in the south bridge chip, but also allows the user to select the hot key mode, thereby avoiding the need to clear the CMOS data in the south bridge chip, and unpacking the chassis, bringing the user Convenience.

綜上所述,本發明符合發明專利要件,爰依法提出專利申請。惟,以上所述者僅為本發明之較佳實施例,舉凡熟悉本案技藝之人士,在爰依本發明精神所作之等效修飾或變化,皆應涵蓋於以下之申請專利範圍內。 In summary, the present invention complies with the requirements of the invention patent and submits a patent application according to law. The above description is only the preferred embodiment of the present invention, and equivalent modifications or variations made by those skilled in the art will be included in the following claims.

10‧‧‧電源電路 10‧‧‧Power circuit

V‧‧‧直流電源 V‧‧‧DC power supply

20‧‧‧濾波電路 20‧‧‧Filter circuit

Q1、Q2‧‧‧MOSFET Q1, Q2‧‧‧ MOSFET

40‧‧‧跳線 40‧‧‧jumper

RTCRST‧‧‧重定端 RTCRST‧‧‧Reposition

C1、C2‧‧‧電容 C1, C2‧‧‧ capacitor

Vcc‧‧‧電源供應器 Vcc‧‧‧Power supply

D1‧‧‧肖特基二極體 D1‧‧‧Schottky diode

30‧‧‧控制電路 30‧‧‧Control circuit

GPIO_CLRCMOS‧‧‧引腳 GPIO_CLRCMOS‧‧‧ pin

41-43‧‧‧引腳 41-43‧‧‧ Pin

R1-R4‧‧‧電阻 R1-R4‧‧‧ resistance

Claims (7)

一種主機板供電系統,包括給一南橋晶片供電之一電源電路及一控制電路,該電源電路之輸入端連接一電源供應器,該電源電路之輸出端連接該南橋晶片之一重定端,該控制電路包括一第一電晶體及一第二電晶體,該第一電晶體之第一端用於接收南橋晶片之一控制訊號,該第二電晶體之第一端連接該第一電晶體之第二端,該第二電晶體之第二端連接該南橋晶片之重定端,該第一、第二電晶體之第三端均接地,主機板正常工作時,該控制訊號處於第一邏輯狀態,使該第二電晶體之第二端為高電平,當需要清除主機板之CMOS(Complementary Metal Oxide Semiconductor)資料時,該控制訊號處於第二邏輯狀態,使該第二電晶體之第二端以及南橋晶片之重定端為低電平,來清除主機板之CMOS資料。 A motherboard power supply system includes a power supply circuit for supplying power to a south bridge chip and a control circuit, wherein an input end of the power supply circuit is connected to a power supply, and an output end of the power supply circuit is connected to one of the reset ends of the south bridge chip, the control The circuit includes a first transistor and a second transistor, the first end of the first transistor is configured to receive a control signal of the south bridge chip, and the first end of the second transistor is coupled to the first transistor The second end of the second transistor is connected to the re-set end of the south bridge chip, and the third ends of the first and second transistors are grounded. When the motherboard is working normally, the control signal is in the first logic state. The second end of the second transistor is at a high level. When it is required to clear the CMOS (Complementary Metal Oxide Semiconductor) data of the motherboard, the control signal is in a second logic state, so that the second end of the second transistor And the reset terminal of the south bridge chip is low to clear the CMOS data of the motherboard. 如申請專利範圍第1項所述之主機板供電系統,其中該電源電路包括一第一電阻、一肖特基二極體及一直流電源,該肖特基二極體包括一第一陽極、一第二陽極及一陰極,該肖特基二極體之第一陽極作為該電源電路之輸入端,該肖特基二極體之第二陽極透過該第一電阻連接該直流電源,該肖特基二極體之陰極作為該電源電路之輸出端。 The motherboard power supply system of claim 1, wherein the power circuit comprises a first resistor, a Schottky diode, and a DC power supply, the Schottky diode includes a first anode, a second anode and a cathode, the first anode of the Schottky diode is used as an input end of the power circuit, and the second anode of the Schottky diode is connected to the DC power source through the first resistor The cathode of the special base diode serves as the output of the power supply circuit. 如申請專利範圍第2項所述之主機板供電系統,還包括一濾波電路,該肖特基二極體之陰極透過該濾波電路與南橋晶片之重定端連接,該濾波電路包括一第一電容、一第二電容及 一第二電阻,該第一電容之一端連接該肖特基二極體之陰極,另一端接地,該第二電容之一端透過該第二電阻連接該肖特基二極體之陰極,該第二電容之一端還連接該第二電晶體之第二端,該第二電容之另一端接地。 The motherboard power supply system of claim 2, further comprising a filter circuit, wherein the cathode of the Schottky diode is connected to the re-terminal of the south bridge chip through the filter circuit, the filter circuit includes a first capacitor a second capacitor and a second resistor, one end of the first capacitor is connected to the cathode of the Schottky diode, and the other end is grounded, and one end of the second capacitor is connected to the cathode of the Schottky diode through the second resistor. One end of the second capacitor is also connected to the second end of the second transistor, and the other end of the second capacitor is grounded. 如申請專利範圍第3項所述之主機板供電系統,還包括一跳線,該跳線具有一第一引腳,一第二引腳及一第三引腳,該跳線之第二引腳連接該第二電晶體之第二端,該跳線之第一引腳接地,該跳線之第三引腳懸空,在主機板供電系統正常工作時,一鍵帽置於跳線之第二引腳及第三引腳上;在清除南橋晶片之CMOS資料時,鍵帽置於跳線之第二引腳及第一引腳上。 The motherboard power supply system of claim 3, further comprising a jumper, the jumper having a first pin, a second pin and a third pin, the second lead of the jumper The pin is connected to the second end of the second transistor, the first pin of the jumper is grounded, and the third pin of the jumper is suspended. When the power supply system of the motherboard is working normally, the first button cap is placed in the jumper On the second pin and the third pin; when the CMOS data of the south bridge chip is cleared, the key cap is placed on the second pin and the first pin of the jumper. 如申請專利範圍第1項所述之主機板供電系統,其中該控制訊號由該南橋晶片中通用輸入輸出埠之一引腳發出。 The motherboard power supply system of claim 1, wherein the control signal is sent by one of the universal input/output ports of the south bridge chip. 如申請專利範圍第1項所述之主機板供電系統,其中該第一、第二電晶體均為N通道MOS(Metal Oxide Semiconductor)型場效應電晶體,該第一、第二、第三端分別為閘極、汲極及源極。 The motherboard power supply system of claim 1, wherein the first and second transistors are N-channel MOS (Metal Oxide Semiconductor) field effect transistors, the first, second, and third ends They are the gate, the drain and the source. 如申請專利範圍第1項所述之主機板供電系統,其中該第一、第二電晶體均為NPN(Negative-Positive-Negative)型電晶體,該第一、第二、第三端分別為基極、集極及射極。 The motherboard power supply system of claim 1, wherein the first and second transistors are NPN (Negative-Positive-Negative) transistors, and the first, second, and third ends are respectively Base, collector and emitter.
TW97115307A 2008-04-25 2008-04-25 Power supply system for motherboard TWI399922B (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWM313911U (en) * 2006-12-15 2007-06-11 Hon Hai Prec Ind Co Ltd Circuit for controlling sequence
CN101038563A (en) * 2006-03-17 2007-09-19 联想(北京)有限公司 Method and device remotely automatic recovering CMOS date with network

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101038563A (en) * 2006-03-17 2007-09-19 联想(北京)有限公司 Method and device remotely automatic recovering CMOS date with network
TWM313911U (en) * 2006-12-15 2007-06-11 Hon Hai Prec Ind Co Ltd Circuit for controlling sequence

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