TWI399752B - Motherboard having mixed-slots architecture - Google Patents

Description

Motherboard with hybrid slot architecture

The invention relates to a computer motherboard, in particular to a host that can flexibly support Double Data Rate 2 (DDR2) memory and Double Data Rate 3 (DDR3) memory. board.

Nowadays, on the general computer motherboard, in addition to the central processing unit, the control chip set and the slot for installing the external card, there are a plurality of slots for mounting the memory. Users can install different amounts of memory as needed. With the rapid development of memory manufacturing technology, DDR3 memory will become the mainstream of future memory due to its superior power consumption and speed. However, the transition from the currently widely used DDR2 memory to DDR3 memory still requires a transition period.

In view of the above, it is necessary to provide a motherboard with a hybrid slot architecture to flexibly support DDR2 memory and DDR3 memory.

A motherboard with a hybrid slot architecture includes a north bridge chip, a first set of slots for plugging the first memory, a second set of slots for plugging the second memory, and a voltage An adjustment circuit, the north bridge chip is connected to the first group of slots through a first channel, and the second group of slots is connected through a second channel, The voltage adjustment circuit is connected to the first group of slots and the second group of slots. When the first memory or the second memory is installed in the corresponding slot, the slot corresponding to the memory is generated. a level signal, the voltage adjustment circuit determines the type of the memory to be mounted according to the level signal, and provides an operating voltage for the memory, the voltage adjustment circuit includes a controller, a feedback bias circuit and a filter The input end of the filter is connected to the controller, the controller includes a feedback pin, the feedback bias circuit includes a first field effect transistor and a second field effect transistor, the first and the The gates of the two field effect transistors are respectively connected to the ground pins of the first connector and the second connector, and the gate of the first field effect transistor is further connected to a power source through a first resistor. a source of the first field effect transistor is grounded, and a drain of the first field effect transistor is connected to a gate of the second field effect transistor and connected to the power source through a second resistor, the second field effect electricity The source of the crystal is grounded, the first The drain of the field effect transistor is connected to the feedback pin of the controller through a third resistor, and the drain of the second field effect transistor is grounded through a fourth resistor and transmitted through a fifth resistor and the filter respectively. The output is connected to the first and second connectors.

Compared with the prior art, the memory slot on the motherboard with the hybrid slot architecture adopts a two-channel hybrid arrangement. For the wiring design, the arrangement of the memory slots can be reduced in the same channel. Hybrid memory wiring complexity; for signal design, the hybrid memory slot arrangement can handle the signal integrity of the hybrid memory separately, simplifying the difficulty of signal design.

40‧‧‧ North Bridge Chip

50‧‧‧First set of slots

60‧‧‧Second set of slots

10‧‧‧Voltage adjustment circuit

52‧‧‧First connector

54‧‧‧ terminating resistor

62‧‧‧Second connector

12‧‧‧ Controller

14‧‧‧ Filter

16‧‧‧Linear regulator

18‧‧‧Reward bias circuit

Q1, Q2‧‧‧ field effect transistor

R1, R2, R3, R4, R5‧‧‧ resistors

1 is a block diagram of a preferred embodiment of a motherboard having a hybrid slot architecture of the present invention.

Figure 2 is a comparison of the address signal waveforms of the DDR2 memory of Figure 1 with and without termination resistors.

Figure 3 is a circuit diagram of the power supply system of Figure 1.

Referring to FIG. 1, a preferred embodiment of a motherboard having a hybrid socket architecture includes a north bridge wafer 40, a first set of slots 50, a second set of slots 60, and a voltage regulating circuit 10.

The first set of slots 50 includes two first connectors 52 and two terminal resistors 54 respectively connected to the two first connectors 52. The first connectors 52 are used for plugging in the first memory. In the embodiment, the first connector 52 is a DDR2 connector, and the first memory is a DDR2 memory. The termination resistor 54 can obtain a better quality signal for the first memory 52, but considering cost saving and wiring area, The terminating resistor 54 can be removed, and the address signal after the removal can still meet the signal design requirements. The second set of slots 60 includes two second connectors 62 for plugging in the second memory. In the preferred embodiment, the second connectors 62 are DDR3 connectors, and the second memory is DDR3 memory. . The north bridge chip 40 is connected to the first group of slots 50 through a first channel A, and the second group of slots 60 is connected through a second channel B. The first connector 52 and the second connector 62 are connected to the voltage regulating circuit 10, and the voltage regulating circuit 10 supplies operating voltages to the first connector 52 and the second connector 62. This embodiment connects two of the most common channels. Connector example. The motherboard with the hybrid slot architecture adopts a hybrid storage slot arrangement or analogous to each channel to connect multiple connectors, such as three or more.

Please refer to FIG. 2 , which is a comparison diagram of the address signal waveforms of the DDR2 memory on the motherboard with the hybrid slot architecture, and the termination signal 54 without the termination resistor 54 , wherein the curve 200 has the termination resistor 54 The address signal waveform is set, and the curve 100 is the address signal waveform after the termination resistor 54 is removed. According to the technical specifications of internal memory established by the Joint Electron Device Engineering Council (JEDEC), the design specifications for memory signal integrity have the following items: overshoot, undershoot, etc. The overshoot of the DDR2 memory is less than 2.3V, and the undershoot is greater than -0.5V to meet the specification requirements. Therefore, the waveform waveforms of the two address signals in Figure 2 are in compliance with the specifications. Therefore, regardless of whether or not the terminating resistor 54 is present on the motherboard, the address signals of the DDR2 memory can meet the design specifications.

Referring to FIG. 3, the voltage regulating circuit 10 includes a controller 12, a filter 14, a linear regulator 16, and a feedback bias circuit 18.

The feedback bias circuit 18 includes two field effect transistors Q1 and Q2 and five resistors R1 R R5. The two field effect transistors Q1 and Q2 are NMOS field effect transistors, and the gates of the two field effect transistors Q1 and Q2 are respectively connected to the ground pins of one of the first connector 52 and the second connector 62. The gate of the field effect transistor Q1 is further connected to a 5V power supply through the resistor R1. The source of the field effect transistor Q1 is grounded, and the gate of the field effect transistor Q1 and the gate of the field effect transistor Q2 are connected. The pole is connected and connected to the 5V power supply through the resistor R2, the field effect transistor Q2 The source is grounded, and the drain of the field effect transistor Q2 is connected to a feedback pin of the controller 12 through the resistor R3. The feedback pin is grounded through the resistor R4 and connected to one end of the resistor R5.

The output end of the controller 12 is connected to the input end of the filter 14 to transmit a voltage signal, the output end of the filter 14 outputs a filtered voltage VDD, and the output end of the filter 14 and the feedback bias voltage The other end of the resistor R5 of the circuit 18 is connected to form a feedback loop, and the filter 14 further transmits a voltage VDD to the linear regulator 16 and is converted into a voltage VTT via the linear regulator 16 to be supplied to the first The connector 52 and the second connector 62. The output end of the filter 14 is directly connected to the first connector 52 and the second connector 62 to output a voltage VDD to the first connector 52 and the second connector 62.

In the preferred embodiment, the feedback voltage Vfb of the controller 12 is set to 0.78V, and the resistance values of the resistors R1 R R5 are 4.7 kilo ohms, 4.7 kilo ohms, 2.4 kilo ohms, and 1.2 thousand, respectively. Ohm and 1.1 kilo ohms.

When the DDR2 memory is mounted on the first connectors 52, the second connectors 62 are vacant. When the computer system is turned on, the gate of the field effect transistor Q1 receives the ground pins of the first connectors 52. A low level signal is generated, so the field effect transistor Q1 is turned off and the field effect transistor Q2 is turned on because the feedback bias circuit 18 must adjust the feedback voltage Vfb of the controller 12 to the pin terminal to the controller 12. The set value of the feedback pin is 0.78V, according to the voltage division formula VDD=Vfb*(R5+RX)/RX of the feedback voltage Vfb and the output voltage VDD of the filter 14, where RX=R3*R4/(R3+R4), The output voltage VDD is calculated to be 1.8V, so the controller 12 will adjust the output voltage so that the output voltage VDD of the filter 14 is 1.8V. The output voltage VDD is directly supplied to the feedback bias circuit 18 and the DDR2 memory mounted on the first connector 52. The output voltage VDD is further converted into a VTT voltage (0.9V) through the linear regulator 16 to provide DDR2 memory. body.

When the DDR3 memory is mounted on the second connectors 62, the first connectors 52 are vacant, and the gate of the field effect transistor Q2 receives the ground pins of the second connectors 62 when the computer system is turned on. A low level signal is generated, so the field effect transistor Q2 is turned off, and the resistor R3 is connected to the feedback circuit because the feedback bias circuit 18 must adjust the feedback voltage Vfb of the controller 12 to the pin terminal to be set to the setting. The value is 0.78V. According to the voltage division formula VDD=Vfb*(R5+R4)/R4 of the feedback voltage Vfb and the output voltage VDD of the filter 14, the output voltage VDD is calculated to be 1.5V, so the controller 12 will adjust the output voltage. The output voltage VDD of the filter 14 is 1.5V, and the output voltage VDD is directly supplied to the feedback bias circuit 18 and the DDR3 memory mounted on the second connector 62. The output voltage VDD is transmitted through the linear regulator. 16 is converted to a VTT voltage (0.75V) for DDR3 memory. Only one type of memory can be selected to be installed on the motherboard at the same time.

Different types of memory can be installed on the motherboard with the hybrid slot structure, and the memory slots are arranged in a two-channel hybrid arrangement, which reduces the wiring complexity of the hybrid memory in the same channel. Separate processing of the signal integrity of the hybrid memory simplifies the difficulty of signal design. You can choose to remove the DDR2 termination resistor on the motherboard, which reduces the difficulty for developers in wiring design and signal design, and saves cost and space. The motherboard supporting the hybrid memory can automatically detect the memory installed on the motherboard Type, and through the voltage regulation circuit to provide a suitable voltage, so that the same motherboard can flexibly support different types of memory to meet the needs of different users. In the memory replacement period, especially during the transition period of DDR2 memory to DDR3 memory, the user is provided with greater application flexibility.

In summary, the present invention complies with the requirements of the invention patent and submits a patent application according to law. The above description is only the preferred embodiment of the present invention, and equivalent modifications or variations made by those skilled in the art will be included in the following claims.

40‧‧‧ North Bridge Chip

50‧‧‧First set of slots

60‧‧‧Second set of slots

10‧‧‧Voltage adjustment circuit

52‧‧‧First connector

54‧‧‧ terminating resistor

62‧‧‧Second connector

Claims (8)

A motherboard with a hybrid slot architecture includes a north bridge chip, a first set of slots for plugging the first memory, a second set of slots for plugging the second memory, and a voltage An adjustment circuit, the north bridge chip is connected to the first group of slots through a first channel, and the second group of slots is connected through a second channel, the voltage regulating circuit and the first group of slots and the second group of slots a slot connection, when the first memory or the second memory is mounted in a slot corresponding thereto, the slot in which the corresponding memory is mounted generates a level signal, and the voltage adjustment circuit determines that the signal is determined according to the level signal Installing a memory type and providing a working voltage for the memory, the voltage regulating circuit includes a controller, a feedback bias circuit and a filter, and the input end of the filter is connected to the controller, the controller Included as a feedback pin, the feedback bias circuit includes a first field effect transistor and a second field effect transistor, and the gates of the first and second field effect transistors are respectively connected to the first connectors And one of the second connectors The gate of the first field effect transistor is further connected to a power source through a first resistor, the source of the first field effect transistor is grounded, and the drain of the first field effect transistor and the second field The gate of the effect transistor is connected and connected to the power source through a second resistor, the source of the second field effect transistor is grounded, and the drain of the second field effect transistor is transmitted through a third resistor and the controller The feedback pin is connected. The drain of the second field effect transistor is grounded through a fourth resistor and connected to the output end of the filter and the first and second connectors through a fifth resistor. The motherboard of the hybrid slot architecture of claim 1, wherein the first set of slots includes two first connectors connected to the voltage regulating circuit and two connected to the first connections Terminal resistance of the device. The motherboard of the hybrid slot architecture of claim 2, wherein the second set of slots comprises two second connectors connected to the voltage regulating circuit. The motherboard of the hybrid slot architecture of claim 1, wherein the voltage regulating circuit further comprises a linear regulator, wherein the output of the filter is further transmitted through the linear regulator and the first One and the second connector are connected. The motherboard of the hybrid slot architecture of claim 1, wherein the first and second field effect transistors are NMOS field effect transistors. The motherboard of the hybrid slot architecture of claim 1, wherein the resistance values of the first to fifth resistors are 4.7 kilo ohms, 4.7 kilo ohms, 2.4 kilo ohms, 1.2 kilo ohms, and 1.1 thousand, respectively. Ohmic, and the voltage at the feedback pin of the controller is 0.78V. The motherboard of the hybrid slot architecture of claim 1, wherein the first memory is DDR2 memory. The motherboard of the hybrid slot architecture of claim 1, wherein the second memory is DDR3 memory.