TWI397959B - Method for making microstructure of polycrystalline silicon - Google Patents
Method for making microstructure of polycrystalline silicon Download PDFInfo
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本發明係有關一種製作複晶矽微結構之方法,特別是指一種應用於CMOS製程製作複晶矽為結構層之元件的後製程方法。The invention relates to a method for fabricating a microcrystalline structure of a polycrystalline silicon, in particular to a post-processing method for fabricating a component of a polycrystalline silicon as a structural layer in a CMOS process.
近年來許多先進國家利用CMOS製程製造微機電元件,並製造與整合各式微感測器(μ-sensor)、微致動器(μ-actuator)、微處理器(μ-processor)、微光學元件(μ-optical device)以及電子電路等元件模組化於單一晶片上,利用MEMS技術將元件微小化並帶來許多的優勢,如高響應度、高精確度、以及低功率損耗等。In recent years, many advanced countries have used CMOS processes to fabricate MEMS components, and manufacture and integrate various types of micro-sensors, μ-actuators, μ-processors, and micro-optics. Components such as μ-optical devices and electronic circuits are modularized on a single wafer, and MEMS technology is used to miniaturize components and bring many advantages such as high responsivity, high accuracy, and low power loss.
光學微機電技術(Optical MEMS)是MEMS領域一項重點發展的範疇,各式使用面型微機械加工技術製造之微光學元件為了使其能夠成功致動,在後製程中微結構的釋放(Release)則為最重要的過程,如何在不破壞特定結構層之前提下,成功釋放微結構,其釋放結果直接影響到元件的性能,當元件的體積越小(<0.18 μm),晶圓尺寸越大(>8吋),蝕刻選擇比與均勻度就更加重要,因此完整的釋放微結構將是使用共用製程製作微機電元件成功與否的重要關鍵。Optical MEMS is a key development area in MEMS. Various micro-optical components manufactured by surface micromachining technology are used to enable successful actuation of microstructures in post-process (Release). ) is the most important process, how to release the microstructure before it is destroyed without destroying the specific structural layer, and the release result directly affects the performance of the component. When the volume of the component is smaller (<0.18 μm), the wafer size is more Large (>8吋), etching selectivity and uniformity are more important, so the complete release microstructure will be the key to the success of using a common process to make MEMS components.
蝕刻技術可以分為乾式蝕刻(Dry Etching)及濕式蝕刻(Wet Etching)兩類,乾式蝕刻為非等向性蝕刻(Anisotropic Etching),具有較好的方向性(Directional Properties)但比濕式蝕刻較差的選擇性(Selectivity),而濕式蝕刻主要為等向性蝕刻(Isotropic Etching),具有製程簡單、設備便宜與可批量生產之優點。若要使用濕式蝕刻釋放CMOS-MEMS製程之元件, 則須考慮蝕刻液與結構之間的選擇比以及蝕刻材料之厚度。Etching technology can be divided into dry etching (Dry Etching) and wet etching (Wet Etching). Dry etching is anisotropic etching, which has better directivity but is more than wet etching. Poor selectivity, and wet etching is mainly isotropic etching, which has the advantages of simple process, cheap equipment and mass production. To release components of a CMOS-MEMS process using wet etching, The choice between the etchant and the structure and the thickness of the etched material must be considered.
一般來說,CMOS製程大多使用複晶矽(poly-silicon)來做為線路的佈局,但若使用複晶矽來製作MEMS微結構,則須採用高選擇比的蝕刻液,才能在進行蝕刻犧牲層時不會傷害到微結構。然而,選擇比高的蝕刻液雖然縮短蝕刻的時間,但在犧牲層結構尚未完全蝕刻乾淨時,複晶矽組成的微結構也會遭受嚴重的蝕刻。換個角度來看,若是元件之犧牲層太厚或蝕刻液的蝕刻速率較慢,而導致蝕刻時間增加,也會使微結構產生過度蝕刻而損毀。In general, CMOS processes mostly use poly-silicon as the layout of the circuit. However, if a polysilicon is used to fabricate the MEMS microstructure, a high selectivity etching solution must be used in order to perform the etching sacrifice. Layers do not harm the microstructure. However, the selection of a higher etching liquid shortens the etching time, but when the sacrificial layer structure is not completely etched clean, the microstructure of the polycrystalline germanium is also subjected to severe etching. From another point of view, if the sacrificial layer of the component is too thick or the etching rate of the etching solution is slow, resulting in an increase in etching time, the microstructure is excessively etched and damaged.
鑒於以上的問題,本發明的主要目的在於提供一種製作複晶矽微結構之方法,乃利用CMOS-MEMS製程金屬層能阻擋乾式蝕刻的特性,來降低犧牲層的厚度與蝕刻時間,藉此可將複晶矽材料為主之微結構成功完整釋放並保持元件的完整性。In view of the above problems, the main object of the present invention is to provide a method for fabricating a germanium germanium microstructure by using a CMOS-MEMS process metal layer capable of blocking the characteristics of dry etching to reduce the thickness of the sacrificial layer and the etching time. The microstructure of the polycrystalline germanium material is successfully released and the integrity of the component is maintained.
因此,為達上述目的,本發明所揭露之製作複晶矽微結構之方法,應用於一利用CMOS製程所製得之MEMS元件,且MEMs元件是以複晶矽作為結構層,並以金屬層做為蝕刻阻擋層來降低犧牲層的厚度,先在第一道後製程以乾式蝕刻將犧牲層蝕刻至金屬層後停止蝕刻,然後,再透過第二道後製程以濕式蝕刻的方式,先移除金屬層,再移除保護複晶矽結構層之犧牲層,將可縮短蝕刻犧牲層之時間,同時也可避免過度蝕刻而使結構層的完整性受損。Therefore, in order to achieve the above object, the method for fabricating a germanium germanium microstructure disclosed in the present invention is applied to a MEMS device fabricated by a CMOS process, and the MEMs device is a polycrystalline germanium as a structural layer and a metal layer. As an etch barrier to reduce the thickness of the sacrificial layer, the sacrificial layer is etched to the metal layer by dry etching in the first post-process, then the etching is stopped, and then the second post-process is wet-etched first. In addition to the metal layer, removing the sacrificial layer protecting the polysilicon structure layer will shorten the time for etching the sacrificial layer, and also avoid excessive etching to impair the integrity of the structural layer.
另外,本發明可在第一道後製程中利用側邊開孔設計之光罩,對於犧牲層進行蝕刻,以避免製程失誤直接將金屬層蝕穿而造成複晶矽結構層受 損。另外,在第二道後製程亦可將側邊裸露之金屬層蝕刻,同時使金屬層上方之犧牲層剝離,再將保護複晶矽結構層之犧牲層蝕刻,從而可大幅降低犧牲層厚度與蝕刻時間,更提高了元件在完全釋放後的完整性與成功致動的可能性。In addition, the present invention can utilize the photomask of the side opening design in the first post-process, and etch the sacrificial layer to avoid the process error directly eroding the metal layer and causing the polycrystalline germanium structure layer to be affected. damage. In addition, in the second post-process, the exposed metal layer of the side layer can also be etched, and the sacrificial layer above the metal layer is peeled off, and the sacrificial layer of the protective polysilicon structure layer is etched, thereby greatly reducing the thickness of the sacrificial layer and etching. Time increases the integrity of the component after complete release and the likelihood of successful actuation.
為使對本發明的目的、特徵及其功能有進一步的了解,茲配合圖式詳細說明如下:In order to further understand the purpose, features and functions of the present invention, the drawings are described in detail as follows:
請參照第1A圖~第1D圖,為本發明之第一實施例所提供之製作複晶矽微結構之方法的流程示意圖。Please refer to FIG. 1A to FIG. 1D for a schematic flow chart of a method for fabricating a polysilicon structure according to a first embodiment of the present invention.
本實施例乃利用CMOS製程製作以複晶矽為結構層之MEMS元件,如第1A圖所示,此MEMS元件主要是由含矽基材10、複晶矽結構層20、鋁金屬層30、二氧化矽犧牲層40與場氧化層50所構成,且複晶矽結構層20藉由場氧化層50隔離於含矽基材10上方,金屬層30位於複晶矽結構層20上方,而犧牲層40覆蓋於含矽基材10、複晶矽結構層20、金屬層30與場氧化層50上方並將金屬層30與複晶矽結構層20相隔離。當MEMS元件經由CMOS-MEMS共用製程平台製造,需要接續的後製程步驟將複晶矽結構層20自犧牲層40中釋放,才能得以成功致動。In this embodiment, a MEMS device is formed by using a CMOS process as a structural layer. As shown in FIG. 1A, the MEMS device is mainly composed of a germanium-containing substrate 10, a germanium germanium structure layer 20, and an aluminum metal layer 30. The germanium dioxide sacrificial layer 40 and the field oxide layer 50 are formed, and the germanium germanium structure layer 20 is separated from the germanium-containing substrate 10 by the field oxide layer 50, and the metal layer 30 is located above the germanium germanium structure layer 20, and sacrificed. The layer 40 covers the germanium-containing substrate 10, the germanium germanium structure layer 20, the metal layer 30 and the field oxide layer 50, and isolates the metal layer 30 from the germanium germanium structure layer 20. When the MEMS component is fabricated via a CMOS-MEMS shared process platform, a subsequent post-process step is required to release the polysilicon structure layer 20 from the sacrificial layer 40 for successful actuation.
如第1B圖所示,藉由第一道後製程之反應離子蝕刻(Reactive Ion Etching;RIE)的非等向性蝕刻,加上其金屬層30可做為蝕刻阻擋層之特性,將二氧化矽犧牲層40蝕刻至複晶矽結構層20上方之金屬層30後停止蝕刻,以減少二氧化矽犧牲層40之厚度。As shown in FIG. 1B, the anisotropic etching by Reactive Ion Etching (RIE) of the first post-process, plus the metal layer 30 can be used as an etch barrier layer, and the dioxide is oxidized. The sacrificial layer 40 is etched to the metal layer 30 above the polysilicon structure layer 20 and then etched to reduce the thickness of the cerium oxide sacrificial layer 40.
如第1C圖所示,第二道後製程是利用磷酸不會與二氧化矽材料產生反 應之特性,將保護複晶矽結構層20之金屬層30蝕刻。As shown in Figure 1C, the second post-process is the use of phosphoric acid that does not react with the cerium oxide material. In accordance with the characteristics, the metal layer 30 protecting the polysilicon structure layer 20 is etched.
最後,如第1D圖所示,再以二氧化矽蝕刻液(氫氟酸(HF)或Silox Vapox III)將複晶矽結構層20周圍之犧牲層40a與場氧化層50蝕刻,即完成釋放。Finally, as shown in FIG. 1D, the sacrificial layer 40a around the polysilicon structure layer 20 and the field oxide layer 50 are etched by a cerium oxide etching solution (hydrofluoric acid (HF) or Silox Vapox III) to complete the release. .
本實施例利用CMOS-MEMS製程中金屬能阻擋RIE蝕刻的特性以及使用二氧化矽來保護微結構的方式,可減低複晶矽結構層上方之犧牲層厚度,同時,也使金屬層上下之犧牲層厚度大幅縮減,此方法將可在短時間內成功釋放微結構且能保持元件的完整性。This embodiment utilizes the characteristics of the metal barrier RIE etching in the CMOS-MEMS process and the manner in which the germanium is used to protect the microstructure, which can reduce the thickness of the sacrificial layer above the polycrystalline germanium structure layer, and at the same time, the metal layer is sacrificed. The layer thickness is greatly reduced, and this method will successfully release the microstructure in a short time and maintain the integrity of the component.
再者,請參照第2A圖~第2D圖,為本發明之第二實施例所提供之製作複晶矽微結構之方法的流程示意圖。Furthermore, please refer to FIG. 2A to FIG. 2D, which are schematic flowcharts of a method for fabricating a polysilicon structure according to a second embodiment of the present invention.
本實施例利用CMOS製程所製作之MEMS元件,如第2A圖所示。接著,在第一道後製程之反應離子蝕刻過程中,為了避免製程失誤使反應離子蝕刻直接將金屬層30打穿造成複晶矽結構層20受損,乃於光罩設計時以側邊開孔進行反應離子蝕刻方式,來對於犧牲層40進行蝕刻,而僅露出金屬層30側邊,也就是說,使複晶矽結構層20上方之金屬層30仍受到金屬層30上方之犧牲層40b保護,並利用金屬層30來保護複晶矽結構層20的完整性,如第2B圖所示。This embodiment utilizes a MEMS device fabricated by a CMOS process, as shown in FIG. 2A. Then, in the reactive ion etching process of the first post-process, in order to avoid the process error, the reactive ion etching directly breaks the metal layer 30 to damage the polysilicon structure layer 20, and the side of the photomask is opened by the side. The holes are subjected to reactive ion etching to etch the sacrificial layer 40, and only the side of the metal layer 30 is exposed, that is, the metal layer 30 above the polysilicon structure layer 20 is still subjected to the sacrificial layer 40b over the metal layer 30. The metal layer 30 is protected and utilized to protect the integrity of the germanium structure layer 20, as shown in FIG. 2B.
然後,如第2C圖所示,第二道後製程是先將金屬層30以磷酸蝕刻,並連帶移除金屬層30上方的犧牲層40b。最後,再以二氧化矽蝕刻液(氫氟酸(HF)或Silox Vapox III)將犧牲層40a與場氧化層50蝕刻,釋放複晶矽結構層20,如第2D圖所示。Then, as shown in FIG. 2C, the second post-process is to first etch the metal layer 30 with phosphoric acid and remove the sacrificial layer 40b over the metal layer 30. Finally, the sacrificial layer 40a and the field oxide layer 50 are etched with a cerium oxide etching solution (hydrofluoric acid (HF) or Silox Vapox III) to release the polycrystalline germanium structure layer 20 as shown in FIG. 2D.
綜上所述,根據本發明所提供的製作複晶矽微結構之方法,將在使用複晶矽做為元件的主結構時,能大幅提升元件製作的良率與可行性。In summary, according to the method for fabricating the microcrystalline structure of the germanium provided by the present invention, the use of the polycrystalline germanium as the main structure of the component can greatly improve the yield and feasibility of the component fabrication.
雖然本發明以前述之實施例揭露如上,然其並非用以限定本發明。在不脫離本發明之精神和範圍內,所為之更動與潤飾,均屬本發明之專利保護範圍。關於本發明所界定之保護範圍請參考所附之申請專利範圍。Although the present invention has been disclosed above in the foregoing embodiments, it is not intended to limit the invention. It is within the scope of the invention to be modified and modified without departing from the spirit and scope of the invention. Please refer to the attached patent application for the scope of protection defined by the present invention.
10‧‧‧含矽基材10‧‧‧Inorganic substrate
20‧‧‧複晶矽結構層20‧‧‧Multilayer structure layer
30‧‧‧金屬層30‧‧‧metal layer
40‧‧‧犧牲層40‧‧‧ Sacrifice layer
40a‧‧‧犧牲層40a‧‧‧ sacrificial layer
40b‧‧‧犧牲層40b‧‧‧sacrificial layer
50‧‧‧場氧化層50‧‧‧ field oxide layer
第1A圖~第1D圖係為本發明之第一實施例所提供之製作複晶矽微結構之方法的流程示意圖。1A to 1D are schematic flow charts showing a method of fabricating a polycrystalline germanium microstructure according to a first embodiment of the present invention.
第2A圖~第2D圖係為本發明之第二實施例所提供之製作複晶矽微結構之方法的流程示意圖。2A to 2D are schematic flow charts showing a method of fabricating a germanium germanium microstructure according to a second embodiment of the present invention.
10‧‧‧含矽基材10‧‧‧Inorganic substrate
20‧‧‧複晶矽結構層20‧‧‧Multilayer structure layer
30‧‧‧金屬層30‧‧‧metal layer
40‧‧‧犧牲層40‧‧‧ Sacrifice layer
40a‧‧‧犧牲層40a‧‧‧ sacrificial layer
50‧‧‧場氧化層50‧‧‧ field oxide layer
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Henry Baltes, "Future of IC microtransducers", 1996, vol. 56, page 179~192 * |
Huikai Xiea, Yingtian Pan, Gary K. Fedder, "Endoscopic optical coherence tomographic imaging with a CMOS-MEMS micromirror", 2003, Vol. 103, page 237~241 * |
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