TWI397264B - Fractional-n phase-locked-loop and method - Google Patents

Description

Fractional-N phase lock device and method

The present invention relates to phase locked loops, and more particularly to a digital fractional-N phase lock loop having phase noise cancellation.

A digital phase lock loop (Digital Phase Lock Loop, Digital PLL) receives a reference clock having a first frequency and correspondingly generates an output clock having a second frequency. The output clock phase is phase-locked to the phase of the reference clock, and the second frequency of the output clock is N times higher than the first frequency. As shown in FIG. 1A, a typical digital phase locked loop 100A includes a time-to-digital converter (TDC) 110, a digital loop filter 120, and a digitally controlled oscillation. A digitally controlled oscillator (DCO) 130 and a divide-by-N circuit 140A. A time to digital converter (TDC) 110 is configured to measure a time difference between a reference clock REF having a first frequency and a feedback clock FB having a third frequency, and correspondingly generating the time difference One time difference signal TD. The loop filter 120 is configured to filter the time difference signal TD (which may be a digital signal) and generate a control code C. The digitally controlled oscillator 130 generates an output clock OUT having a second frequency in accordance with the control code. The divide-by-N circuit 140A divides the output clock OUT having the second frequency by a divisor N to generate a feedback clock FB having a third frequency. It should be noted that the second frequency (ie, the frequency of the output clock OUT, and at the same time the oscillation frequency of the digitally controlled oscillator 130) is controlled by the value of the control code C. In one embodiment, the frequency of the output clock OUT (ie, the second frequency, also the oscillation frequency of the digitally controlled oscillator 130) is increased (decreased) depending on the value of the control code being increased (decreased). And because of the divide by N function of the N circuit 140A, the frequency of the second frequency will be N times higher than the third frequency. When the control code C is too small (too large), the second frequency will also be too low (too high); and accordingly, the third frequency will also be too low (too high). In this way, the feedback clock FB will be too slow (too fast), and therefore backward (leading) reference clock REF. As a result, the time difference signal TD is positive (negative value), and this positive value (negative value) represents the time difference between the reference clock REF and the feedback clock FB. It should be noted that the digital loop filter 120 typically includes an integral function. Due to the integral function of the digital loop filter 120, when the time difference signal TD is positive (negative value), the control code C is increased (decreased). In this closed-loop manner, the control code C is adjusted (ie, increased or decreased) to enable the timing (ie, frequency or phase) of the feedback clock FB to track the reference clock REF. Timing. In steady state, the control code C is settle and is an appropriate value, and the mean value of the time difference signal TD must be zero (zero), otherwise the control code C will be due to the digital loop. The integral function of the filter 120 is blow up and cannot be stabilized. Therefore, at steady state, the third frequency must be equal to the first frequency. As a result, since the second frequency is N times higher than the third frequency by the processing of the N circuit 140A, the second frequency must be N times higher than the first frequency.

The divide-by-N circuit 140A of the digital phase lock loop 100A of FIG. 1A can be conveniently implemented using a divide-by-N counter (for example, setting N to an integer). However, because the divisor of the counter needs to be an integer, if N is not an integer, then directly using a counter with a fixed divisor will not work properly. To implement the divide-by-N function for dealing with non-integer N , we must assume N = N _int +α, where N _int is an integer and α is a fractional number between 0 and 1, and It is necessary to arbitrarily set (shuffle) the divisor value of the counter. In one embodiment, the divisor value can be arbitrarily set to N _int and ( N _int +1); as long as the probability of ( N _int +1) divisible value is α, and the probability of dividing by N _int is (1-α) The effective divisor value will be equal to N _int +α. In the prior art, a delta-sigma modulator is often used to dynamically set the divisor value.

The divide-by-N circuit 140A of the digital phase locked loop 100A is replaced by a digital phase locked loop PLL 100B having a divide-by-N and divide-and-score function in FIG. Circuit 140B of an embodiment includes a dual-modulus divider (DMD) 150 and a delta-sigma modulator (DSM) 160. The dual modulus divider 150 is configured to divide the output clock OUT by a divisor value N _int or ( N _int +1) and generate a feedback clock FB according to the binary code CARRY. The triangular integral modulator 160 is configured to receive the fractional value α, and adjust the fractional value α to become the binary code CARRY according to a timing provided by the feedback clock FB. The purpose of the delta-sigma modulator 160 is to generate a binary code CARRY, for example to produce CARRY as 0, possibly alpha, or 1, possibly (1-alpha), and the average of CARRY is equal to a. In this manner, the output clock OUT is divided by a value arbitrarily set between N _int and ( N _int +1), and the average value is a divisor value of N _{int +} α to generate a feedback clock FB.

The divisor value of the N-circuit can be effectively achieved by arbitrarily selecting (Shuffling) in addition to N and fractional- N division. In this embodiment, at steady state, the average time difference between the reference clock REF and the feedback clock FB (ie, the average value of the time difference signal TD) is still equal to zero, but the instantaneous time difference is not zero. And the maximum value can be almost T _DCO /2. Wherein, T _DCO represents one time period of the output clock OUT, and the divisor value is arbitrarily set to a value between N _int and ( N _int +1). The instantaneous time difference will cause the time difference signal TD to generate instantaneous noise, causing noise in the control code C, which will cause phase noise in the output clock OUT.

In addition to generating phase noise by arbitrarily selecting the divisor value, the non-ideal time-to-digital converter 110 (in Figure 1A or Figure 1B) also contributes phase noise in the output clock OUT. As shown in FIG. 1C, the time difference signal TD should be a ratio of the time difference between the reference clock REF and the feedback clock FB, as indicated by the dashed line 170 in the figure. However, in practice, the characteristics of the time to digital converter will deviate from the dashed line 170 as an arc 180. This problem of ideal linear deviation will cause an error in the time difference signal TD to produce unwanted phase noise to the output clock OUT.

One of the objects of the present invention is to provide a fractional-N phase lock loop that eliminates phase noise.

One of the objects of the present invention is to provide a fractional-N phase lock loop to reduce or avoid phase noise of the output clock due to instantaneous time difference.

One of the objects of the present invention is to provide a fractional-N phase lock loop to reduce or avoid phase noise of the output clock due to non-ideal time to digital converters.

One embodiment of the present invention provides a digital fractional-N phase locked loop. The digital fraction-N phase lock loop includes: a time to digital converter for converting a time difference between a reference clock and a feedback clock into a time difference signal; and a cancellation circuit for receiving time a difference signal, and generating a residual error signal according to the time difference signal and the instantaneous error signal; a digital loop filter for filtering the residual error signal to generate a control code; a digital control An oscillator for generating an output clock according to the control of the control code; a dividing circuit for receiving a fractional value to generate the instantaneous error signal; and dividing the output clock according to the control of the fractional value Divide the value to generate a feedback clock.

An embodiment of the present invention provides a method for reducing digital fractional-N phase lock loop phase noise, comprising the following steps: first, quantifying a reference clock and a feedback time a time difference value of the pulse to generate a time difference signal; generating a residual error signal according to the time difference signal and a momentary error signal; and then filtering the residual error signal to generate a control a code; an oscillator is controlled by the control code to generate an output clock; a fractional value between 0 and 1 is received to generate an instantaneous error signal; and thereafter, the output clock is divided by a division value according to the fractional value.

The following description of the preferred embodiments of the present invention will be understood by those skilled in the art that the invention may be practiced in various possible ways and not limited to the features of the following exemplary embodiments or embodiments . In addition, details are not repeatedly shown or described in detail to avoid obscuring the invention.

Still referring to Figure 1B, in a typical fractional-N phase-locked loop (fractional- N PLL) 100B, the fractional- N division function can effectively set the dual-modulus divider arbitrarily (Dual- The modulus divider, DMD) 150 divisor value is executed. However, setting the divisor value arbitrarily will cause an instantaneous error in the time difference between the reference clock REF and the feedback clock FB. The instantaneous error of this time difference is measured and digitized by time to digital converter 110. However, the time to digital converter 110 is typically non-ideal and, therefore, produces distortion to the digital converter 110 as previously described. The present invention will eliminate the instantaneous error of the time difference and the distortion of the time-to-digital converter 110 due to non-ideality.

Embodiments of the present invention utilize a series expansion of a set of basis functions to describe the non-ideal characteristics of a time to digital converter. In an exemplary embodiment, the Lei Jiande polynomial (Legendre polynomials series) can be implemented. The Lei Jiande polynomial includes a linear combination of Lei Jiande polynomials. The first of the Lei Jiande polynomials The first few terms are listed as follows: P ₀ ( x )=1 (1)

P ₁ ( x )= x (2)

P ₂ ( x )=(3 x ² -1)/2 (3)

P ₃ ( x )=(5 x ³ -3 x )/2 (4)

P ₄ ( x )=(35 x ⁴ -30 x ² +3)/8 (5)

P ₅ ( x )=(63 x ⁵ -70 x ³ +15 x )/8 (6)

The Lei Jiande polynomial is orthogonal (Orthogonal) in the interval [-1, 1]. In detail, it can be applied to the following relations: Where δ _mn is the Kronecker-delta function, ie

The Lei Jiande polynomial can be used as a set of basic equations to represent the conversion characteristics of time to digital converters. The instantaneous error of the time difference between the reference clock REF and the feedback clock FB is ε , and the time difference signal TD (ie, time-to-digital conversion) can be represented by the sequence expansion of the Lei Jiande polynomial (ie, the linear combination of Lei Jiande polynomials) Output of TDC): TD= c ₀ P ₀ ( ε )+ c ₁ P ₁ ( ε )+ c ₂ P ₂ ( ε )+ c ₃ P ₃ ( ε )+ c ₄ P ₄ ( ε )+ c ₅ P ₅ ( ε )+... (9)

The divisor value is arbitrarily set by a delta-sigma modulator in the digital fraction-N phase lock loop, and the value of ε (ie, the instantaneous error of the time difference between the reference clock REF and the feedback clock FB) can be accurately prediction. If the expansion coefficients ( c ₀ , c ₁ , c ₂ , c ₃ , ...) are also known, the error of the time difference signal TD can also be accurately estimated and eliminated.

Figure 2A shows a schematic diagram of a digital fraction-N phase lock loop 200A in accordance with one embodiment of the present invention. The digital fraction-N phase lock loop 200A includes a time-to-digital converter (TDC) 210, a cancellation circuit 215, a digital loop filter 220, and a digital bit. A Digitally Controlled Oscillator (DCO) 230, and a Divider circuit 240. In one embodiment, the cancellation circuit 215 includes a summing circuit (summation) Circuit) 270 and an adaptive series expansion function unit 280A. In one embodiment, the divide circuit 240 includes a dual-modulus divider (DMD) 250 and a delta-sigma modulator (DSM) 260.

In one embodiment, the time-to-digital converter 210 is configured to measure the time difference between the reference clock REF and the feedback clock FB, and correspondingly generate a time difference signal TD (which is a digital signal) for indicating the time difference. ). The summing circuit 270 is configured to subtract the time difference signal TD by a predetermined error signal PE to generate a residual error signal RE. The digital loop filter 220 is used to filter the residual error signal RE and generate the control code C. The digitally controlled oscillator 230 is operative to generate an output clock OUT in accordance with the control code C. The dual modulus divider 250 is configured to divide the output clock OUT by a divide value to generate a feedback clock FB. Among them, the divisor value is controlled by a binary carry signal CARRY. The triangular integral modulator 260 is configured to adjust a fractional value α to the binary carry signal CARRY, and generate a time instant error signal ε according to the clock provided by the feedback clock FB. The adaptive series expansion function unit 280A is configured to receive the instantaneous error signal ε and the residual error signal RE, and generate a preset error signal PE. The preset error signal PE can be expressed by the Lei Jiande polynomial series expansion:

Among them, the coefficients with hats represent the estimated coefficients of the Lei Jiande polynomial series in equation (9). In one embodiment, the estimated coefficients may be based on a least mean square (LMS) algorithm:

Where μ is an adaptation constant. This constant must be small enough to ensure convergence of the adaptive operation. The superscript "(old)" indicates an old value before the adaptive operation, and the superscript "(new)" indicates a new value after the adaptive operation. In fact, if the time difference signal TD is normalized to be related to T _DCO /2 (ie TD = ±1 when the time difference between the reference clock REF and the feedback clock FB is ± T _DCO /2 (where T _DCO represents the output) The clock period is cycled and the instantaneous error signal ε is also normalized (in the interval [-1, 1]), then the typical value of μ is 0.01. It should be noted that the larger the μ , the faster the convergence. However, the larger the adaptation noise is; on the contrary, the smaller the μ is, the slower the convergence is, but the smaller the adaptation noise is. In fact, μ can be set to a larger value in the initial state. Values to help converge; and μ is set to a smaller value after convergence to reduce adaptive noise. In one embodiment, in the initial state, all estimated coefficients are set to zero and will not be adaptively adjusted ( Adapted) until the digital fraction-N phase lock loop reaches a steady state condition. This steady state state can be confirmed by a timer timeout (which is set according to a preset time, this preset time For the digital fraction-N phase lock loop to reach steady state time), or by confirming the time difference The signal TD has been completely confirmed by falling into the standard time interval [-1, 1]. The adaptive operation can be performed continuously or intermittently.

Briefly, in an exemplary embodiment, the adaptive series expansion function unit 280A shown in FIG. 2A receives the instantaneous error signal ε and the residual error signal RE, and according to equations (10), (11), and equations ( The Lei Jiande polynomial defined by 1)~(6) is used to generate the preset error signal PE. When the value of the Lei Jiande polynomial expansion (equation (10)) is selected according to the user's judgment, it is usually sufficient to select 4 to 6 items to obtain satisfactory accuracy. Moreover, those skilled in the art can implement all the equations in various ways and forms as long as mathematical equivalence is maintained. For example, Legendre polynomials can be converted to a Taylor series (Taylor series) instantaneous error [epsilon] collected by the same order (order of power) of the item (i.e., [epsilon] collected all the items, all items of ε ^2, all ε ³ items, ...).

Figure 2B shows a schematic diagram of a digital fraction-N phase lock loop 200B in accordance with another embodiment of the present invention. The series expansion is based on the time difference signal TD (instead of the residual error signal RE). Here, an alternative adaptive series expansion function unit 280B is used in place of the adaptive series expansion function unit 280A of FIG. 2A. The same Lei Jiande polynomial series (Equation (10)) is still used to estimate the prediction error signal PE, but the coefficient part uses the following formula:

Where n = 0, 1, 2, 3, ..., and < A , B > represents the statistical average of A times B (A times B). In short, in the alternative embodiment, the adaptive series expansion function unit 280B of FIG. 2B receives the instantaneous error signal ε and the time difference signal TD, and according to the square multiplication formulas (10), (12) and The prediction error signal PE is generated by a Lei Jiande polynomial defined by equations (1) to (6). It should be noted that it is again stated that those skilled in the art can implement all equations in various ways and forms according to their needs, as long as mathematical equivalence is maintained. Furthermore, it should be noted that the unit of equation (12) is a constant known in advance and does not need to be estimated based on the number. If the instantaneous error signal is normalized and falls within a preset interval, such as [1, -1], it can be known in advance without performing the estimation of the following numbers.

According to the orthogonality of equation (7). In one embodiment, all of the estimated coefficients are set to zero in the initial state and will not be used for adaptation until the digital fractional-N phase locked loop reaches a steady state condition. It should be noted that the adaptation (equation (12)) can be implemented continuously or intermittently.

The time-to-digital converter 210 and the digitally controlled oscillator 230 of the embodiment of the second and second embodiments of the present invention are familiar to those skilled in the art, and thus the details thereof will not be described again. If you are not familiar with the time to digital converter, please refer to US Pat. No. 7,059,924. If it is not familiar with the digitally controlled oscillator, reference is made to U.S. Patent No. 7,718,860.

The digital loop filter 220 can be selected by the circuit designer to select based on the desired filter response. In an exemplary embodiment, digital loop filter 220 may perform the following discrete-time system response: H ( z ) = K _P z ^-1 + K _I z ^-1 /(1- z ^-1 ) (14)

Among them, the two parameters of K _P and K _I can be specified by the circuit designer.

The dual modulus divider 250 can be a counter-based divider that can have a divisor value of N _int (when CARRY is 1) or N _int +1 (when CARRY is 0). Where N _{int is} the integer part of the fractional division ratio of the digital fractional N-type interlocking loop (200A or 200B). Those skilled in the art will be familiar with the implementation of the counting type dual modulus division circuit as long as they are familiar with the phase locking circuit, and thus the details thereof will not be described again.

Fig. 3 is a view showing a triangular integral modulator 300 according to an embodiment of the present invention. The delta-sigma modulator 300 is adapted to implement the delta-sigma modulator 260 of the 2A or 2B diagram. The modulator 300 operates in synchronization with the feedback clock FB. The modulator 300 includes a first summing circuit 310, an integrator 320, a rounding operator 330, a second summing circuit 340, and a gain/delay element 350. The modulator 300 is basically an accumulator that accumulates the fraction α (where 0 < α < 1) using the integrator 320. The rounding operator 330 performs an inclusion operation on the accumulated amount to generate the carry signal CARRY. When the accumulated amount exceeds 0.5, the carrier signal CARRY is 1, and the first summing circuit 310 will accumulate the value -1; and when the accumulated amount does not exceed 0.5, the carrier signal CARRY is 0, and the value of the accumulator is not required at this time. Subtract any value. In this way, the accumulated amount can be controlled in the interval [-0.5, 0.5], and the carrier signal CARRY can only be 0 or 1.

The instantaneous error signal ε is used by the second summing circuit 340 to calculate the input and output time difference of the rounding operator 330, and is generated by the gain/delay element 350 by delaying and/or scaling the time difference. As shown in FIG. 3, the factor z-1 of the gain/delay element 350 indicates a unit delay, and the factor 2 is a gain factor to confirm whether the result of the instantaneous error ε is normalized to the interval [-1, 1].

The technology of the present invention can be implemented in various alternative embodiments without departing from the spirit and scope of the invention. For example, a higher order triangular integral modulator (DSM) can also be used with the present invention. In this way, the carry signal CARRY is not a binary signal, but becomes a multi-level integer signal, and the dual modulus divider needs to be replaced by a multi-modulus divider.

In addition, various types of series expansion can also be used to replace the Lei Jiande polynomial series. For example, it can be replaced with a Taylor series, a Fourier series, .... Those skilled in the art can arbitrarily determine the appropriate mathematical series expansion to apply according to their needs without departing from the spirit and scope of the present invention. For example, when selecting a Taylor series to replace, simply replace the equation Pn(x) of the Lei Jiande polynomial defined in equations (1)~(6)(n=0~5) with (n=0~5). However, it should be noted that the power functions of the equations are not orthogonal to each other. That is, Not with Orthogonal, assuming n is not equal to m. (The two-equation orthogonal system must be established without a zero statistical correlation between the two equations. In this way, the embodiment 200B of FIG. 2B is combined with equation (12) for adaptive operation (adaptation). Not appropriate, since equation (12) is based on orthogonal properties, the combined use of equation (12) is only appropriate if the expansion of the basic equation is orthogonal. However, embodiment 200B of Figure 2B can still be used, As long as the adaptive operation of the replacement includes the Gram-Schmidt orthgonalization method, the Gram-Schmidt orthogonalization method is familiar to those skilled in the art, no longer The details are described; if not, refer to the standard mathematics textbook. In any case, when the embodiment 200B of FIG. 2B is selected, the orthogonal equations developed as a series may be employed.

The present invention has been described in the above, but the scope of the present invention is not limited thereto, and various modifications and changes can be made by those skilled in the art without departing from the scope of the invention. category.

100A, 100B, 200A, 200B‧‧‧ phase lock loop

110, 210‧‧‧ converter

120, 220‧‧‧ filter

130, 230‧‧‧voltage controlled oscillator

140A, 140B, 240‧‧‧ division circuit

150, 250‧‧‧ divider

160, 260‧‧ ‧ modulator

270, 310, 340‧‧ ‧ total circuit

280A, 280B‧‧‧Adaptive series expansion function unit

320‧‧‧ integrator

330. . . Rounding operator

350. . . Gain/delay element

Figure 1A shows a schematic diagram of a conventional digital phase lock loop.

Figure 1B shows a schematic diagram of a conventional digital fractional N-type phase locked loop.

Figure 1C shows the conversion characteristics of a time to digital converter.

2A is a schematic diagram showing a digital fractional N-type phase locked loop in accordance with an embodiment of the present invention.

2B is a schematic diagram showing a digital fractional N-type phase locked loop according to another embodiment of the present invention.

Figure 3 is a schematic diagram showing an embodiment of a triangular integral modulator in Figures 2A and 2B.

200A‧‧‧phase lock loop

210‧‧‧ converter

220‧‧‧ filter

230‧‧‧Variable Control Oscillator

240‧‧‧Division circuit

250‧‧‧ divider

260‧‧‧Transformer

270‧‧‧ total circuit

280A‧‧‧Adaptive series expansion function unit

Claims (21)

A phase lock loop device includes: a time to digital converter for converting a time difference between a reference clock and a feedback clock into a time difference signal; and a cancellation circuit for receiving the time a difference signal, and generating a residual error signal according to the time difference signal and a momentary error signal; a digital loop filter for filtering the residual error signal to generate a control code; a digitally controlled oscillator, Generating an output clock according to the control of the control code; and a dividing circuit for receiving a fractional value to generate the instantaneous error signal; and dividing the output clock according to the control of the fractional value The value is divided by a value to generate the feedback clock; wherein the instantaneous error signal indicates an instantaneous error of the time difference between the reference clock and the feedback clock. The device of claim 1, wherein the cancellation circuit comprises: a series expansion unit (Map expansion) for mapping the instantaneous error signal to a preset error signal; The circuit subtracts the time difference from a predetermined error signal to generate the residual error signal. The apparatus of claim 2, wherein the series expansion unit is adapted to minimize Correlation of the instantaneous error signal with the residual signal. The device as recited in claim 2, wherein the series expansion unit is adapted to calculate a correlation (Correlation) of the time difference signal with the instantaneous error signal. The apparatus of claim 2, wherein the series expansion unit is a power series having an adaptive coefficient. The device as recited in claim 5, wherein the adaptability coefficient is based on a Least Mean Square (LMS) algorithm. The apparatus of claim 1, wherein the series expansion unit is a Legendre polynomial series having an adaptive coefficient. The device as recited in claim 7, wherein the adaptability coefficient is based on a Least Mean Square (LMS) algorithm. The device of claim 1, wherein the dividing circuit comprises: a delta-sigma modulator (DSM) for receiving the fractional value to generate a CARRY signal. And the instantaneous error signal; and a divider for dividing the output clock by a divisor factor according to the control of the CARRY signal. The device of claim 9, wherein the operation of the delta-sigma modulator is synchronized with the feedback signal. The device of claim 9, wherein when the CARRY signal is logic 1, the divisor value is a first integer; and when the CARRY signal is logic 0, the divisor is The value is a second integer. The apparatus of claim 9, wherein the delta-sigma modulator comprises at least one integrator. The device of claim 12, wherein the delta-sigma modulator comprises a rounding circuit. The device as recited in claim 1, wherein the score is between 0 and 1. A method for reducing fractional-N phase lock loop phase noise includes: quantizing a time difference between a reference clock and a feedback clock to generate a time difference signal; Generating a residual error signal according to the time difference signal and the instantaneous error signal; filtering the residual error signal to generate a control code; using the control code to control an oscillator to generate an output clock; receiving one Dividing the value to generate the instantaneous error signal; and dividing the output clock by a dividing value according to the fractional value; wherein the instantaneous error signal indicates an instantaneous error of the time difference between the reference clock and the feedback clock. The method as recited in claim 15 further includes: performing a trigonometric integral modulation on the fractional value to generate a CARRY signal and the instantaneous error signal; wherein the divisor value corresponds to the carrier signal (CARRY) Signal). The method of claim 15, wherein the step of generating the residual error signal comprises: mapping the instantaneous error signal to the preset error signal by using a first-order number expansion; wherein the series expansion The formula includes a linear combination of a plurality of basic equations each having a respective coefficient. The method of claim 17, wherein the step of generating the residual error signal further comprises: using a coefficient of the coefficients according to a correlation between a base equation and the residual error signal. Or, the correlation between the individual base equation and the time difference signal is selected. The method of claim 17, wherein the series expansion is a power series. The method of claim 17, wherein the series expansion is a Legendre polynomial series. The method of claim 15, wherein the score is between 0 and 1.