200947873 六、發明說明： 【發明所屬之技術領域】 本發明係關於相鎖迴路，特別是關於具有相位雜訊消除功能之分 數-N 相鎖迴路(digital phase loek bop >。 【先前技術】 般數位相鎖迴路(Digital Phase Lock Loop，Digital ?1^)接收一 具有第一頻率之參考時脈，且相應地產生一具有第二頻率之輸出時 脈。其中，輸出時脈係相位鎖定(Phase_1〇cked)於參考時脈之相位，且 輸出時脈之第二頻率高於第一頻率N倍。如第1A圖所示，一典型的 數位相鎖迴路100A包含有一時間至數位轉換器（Time t〇 digital converter ’ TDC)110、一數位迴路濾波器(Digital 1〇〇pfllter)12〇、一數 位控制震盈器 DCO (digitally controlled oscillator) 130、以及一除 N 電 路(divide-by-N circuit)140A。時間至數位轉換器(TDC) 11〇係用以量 測一具有第一頻率之參考時脈REF與一具有第三頻率之回授時脈1^ 間的時間差值，且相應地產生表示該時間差值之一時間差值訊號 TD。迴路濾波器120係用以濾波該時間差值訊號TD (可為數位訊 號），且產生一控制碼C。數位控制震盪器13〇係依據控制碼產生具 有第二頻率之輸出時脈OUT。除N電路14〇A係將具有第二頻率之 輸出時脈OUT除以一除數值(divis〇r)N，以產生具有第三頻率之回授 時脈FB。需注意，該第二頻率(即輸出時脈〇υτ之頻率，且同時為 '數位控制震盪器130之震盪頻率)係由控制碼c之數值所控制。一實 施例，輸出時脈out之頻率(即第二頻率，亦為數位控制震盪器13〇 之震盪頻率)係依據控制碼之數值增加(減少)而增加(減少）。而由於除 N電路14〇A之除N功能，該第二頻率之頻率將高於第三頻率\倍: 4 200947873 當控制碼c太小(太大)時，第二頻率亦會太低(太高）；且相應地，第 三頻率亦會太低(太高）。依此方式，回授時脈FB將會太慢(太快），且 因此落後(超前)參考時脈REF。結果，導致時間差值訊號TD為正值(負 值），此正值(負值)表示參考時脈REF與回授時脈FB之時間差值。須 注意，數位迴路濾波器120通常包含有積分功能。由於數位迴路濾波 器12〇之積分功能，時間差值訊號TD為正值(負值)時，將使控制碼 , c增加(減少）。於此閉迴路(closed-loop)之方式，控制碼c被調整(即 增加或減少)可使回授時脈FB的時序(timing)(即頻率或相位)能夠追 W 縱(加叫參考時脈REF的時序。於穩態下，控制碼C係穩定下來(settle) 而為一適當的數值’且時間差值訊號TD的平均值(mean value)必須為 零(zero) ’否則控制碼c將會因為數位迴路濾波器120之積分功能而 失效(blowup)，且無法穩定下來。因此，於穩態下，第三頻率必須等 於第一頻率。結果，由於除N電路140A之處理使第二頻率高於第三 頻率N倍，所以第二頻率必須高於第一頻率n倍。 第1A圖數位相鎖迴路100A之除N電路Η0Α可便利地使用除 N計數器(例如將N設為整數(integer))實現。然而，因為計數器之除 〇 數須要為整數，但若#不為整數，則直接使用具有一固定除數之計 ： 數器來實現將無法正常運作。若要實現用來處理非整數N(non-integer 州之除N功能，須假設# =况相+ α，其中况财為整數，α為04 之間的分數(fractional number)，且須要可任意設定(shuffle)計數器之 除數值。一實施例’除數值可任意設定與(乂汁丨）；只要(AU+1) 除數值之可能性(probability)為α、與I除數值可能性為(1_α)，有效 的除數值將等於Α^ + α。習知技術中，三角積分調變器(delta_sigma modulator)常用於動態設定該除數值。 5 200947873 將數位鎖相迴路100A之除N電路140A以第1B圖具有除\與 除分數功能之數位鎖相迴路PLL 100B來替換實施。一實施例之電路 140B 包含有一雙模數除法器(Dual-modulus divider，DMD)150 與一：r 角積分調變器(Delta-sigma modulator，DSM)160。雙模數除法器15〇 用以將輸出時脈OUT除以一除數值i或(乂,+1)，且依據二進制瑪 CARRY產生回授時脈FB。而三角積分調變器160用以接收分數值 «，且依據回授時脈FB提供之一時序來調變分數值^成為二進制碼 CARRY。三角積分調變器160之目的係用以產生二進制碼CARRY， 例如產生CARRY為0，可能為α、或丨、可能為(1_α)，且CARRY的 平均值等於π依此方式，輸出時脈0UT被除以任意設定在^㈣ (U1)之間之數值，且平均值為»的除數值，以產生回授時脈 FB 〇 任意選擇(Shuffling)除N電路之除數值可有效地達到除N與除分 數(fractionalWdivision)的效果。本實施例，於穩態下，參考時脈 與回授時脈FB的平均時間差值(即時間差值訊號扣之平均值)仍然 等於零’但是瞬間的(instantaneous)時間差值不為零，且最大值幾乎可 為心〇>/2。其中，7^0係表示輸出時脈〇υτ之一時間週期，且除數 值係任意設定為的數值。瞬間的铜差值將引起 時間差值訊號TD產生瞬間雜訊，造成控制碼c出現雜訊，進而導致 輸出時脈OUT產生相位雜訊。 除了由任意選擇除數值產生相位雜訊之外，非理想的時間至數位 轉換器110 (於第1A圖或第1B圖中)也會於輸出時脈贿中貢獻 (contribute)相位雜訊。如第lc圖所示’時間差值訊號功應為參考 時脈REF與回授時脈四時間差的一比值，如圖示中破折線Μ續 6 200947873 不。然而，實際上，時間至數位轉換器之特性將會如弧線18〇般偏離 破折線170。此由理想的直線偏離問題，將使時間差值訊號TD產生 誤差而對輸出時脈OUT產生出不想要的相位雜訊。 【發明内容】 本發明之目的之一係在提供一種可消除相位雜訊之分數_N相鎖 1 迴路。 * 本發明之目的之一係在提供一種分數-N相鎖迴路，以減少或避 免因瞬間時間差值所導致輸出時脈之相位雜訊。 本發明之目的之一係在提供一種分數_N相鎖迴路，以減少或避 免因非理想的時間至數位轉換器所導致輸出時脈之相位雜訊。 本發明之一實施例提供了 一種數位分數_N相鎖迴路。該數位分 數-N相鎖迴路包含有：一時間至數位轉換器，用以將一參考時脈與一 回授時脈之時間差值轉換為一時間差值訊號；一消除電路，用以接收 時間差值訊號，且依據時間差值訊號與一瞬間誤差訊號產生一餘值誤 差訊號(Residual error signal); —數位迴路濾波器，用以濾波餘值誤差 訊號，以產生一控制碼；一數位控制震盪器，用以依據控制碼之控制 〇 產生一輸出時脈；一除法電路，用以接收一分數值(Fractional - number) ’以產生該瞬間誤差訊號；且依據該分數值之控制將輸出時 脈除以一除數值，以產生回授時脈。 - 本發明之一實施例提供了一種用以減少數位分數·Ν相鎖迴路 (digital fractional-N phase lock loop)相位雜訊之方法，包含有下列步 驟：首先，量化一參考時脈與一回授時脈之時間差值，以產生一時間 差值訊號；依據時間差值訊號與一瞬間誤差訊號，產生一餘值誤差 訊號(Residual error signal);接著，濾波餘值誤差訊號，以產生一控制 7 200947873 碼；利用控制碼控制一震盪器，以產生一輸出時脈；接收一 0與！間 的分數值’以產生瞬間誤差訊號；之後，依據分數值將輸出時脈除以 一除數值。 【實施方式】 以下之說明將舉出本發明之數個較佳的示範實施例，熟悉本領域 * 者應可理解，本發明可採用各種可能的方式實施，並不限於下列示範 . 之實施例或實施例中的特徵。另外，眾所知悉之細節不再重覆顯示或 贅述，以避免模糊本發明之重點。 仍請參考第1B圖，於一典型的分數-N相鎖迴路(fractional·^ PLL) 100B中，除N分數(fractionakAMivision)功能可有效地由任意設 定雙模數除法器(Dual-modulus divider，DMD) 150之除數值來執行。 但是，任意設定除數值將造成參考時脈REF與回授時脈FB間之時間 差之瞬間誤差。該時間差之瞬間誤差係由時間至數位轉換器11〇量測 並數位化。然而’時間至數位轉換器11〇通常是非理想的，因此，會 產生如前述時間至數位轉換器110之失真。本發明將可消除時間差之 瞬間誤差與時間至數誤轉換器110因非理想所造成的失真。 ❹ 本發明各實施例利用級數展開式(series expansion)(即一組基本函 : 數的線性組合(a linear combination of a set of basis functions)來描缯出 時間至數位轉換器之非理想特性。在非限制之示例性實施例中，可採 用雷建德多項式(雷建德多項式級數(Legendre polynomials series))來 實施。雷建德多項式包含有一雷建德多項式之線性組合。雷建德多項 式之第一部份之項次(first few terms)列示如下： Λ)(χ) = 1 Ο) Ρι(λ：) = X (2) Pi{x) = (3χ2-1)/2 ⑶ 8 200947873200947873 VI. Description of the Invention: [Technical Field] The present invention relates to a phase-locked loop, and more particularly to a fractional-N phase lock loop having a phase noise canceling function (digital phase loek bop > [Prior Art] A digital phase lock loop (Digital Phase Lock Loop, Digital ?1^) receives a reference clock having a first frequency, and correspondingly generates an output clock having a second frequency, wherein the output clock phase is locked (Phase_1) 〇cked) is in reference to the phase of the clock, and the second frequency of the output clock is N times higher than the first frequency. As shown in FIG. 1A, a typical digital phase locked loop 100A includes a time to digital converter (Time) T〇digital converter ' TDC) 110, a digital loop filter (Digital 1〇〇pfllter) 12〇, a digitally controlled oscillator DCO (digitally controlled oscillator) 130, and a divide-by-N circuit (divide-by-N circuit) 140A. The time to digital converter (TDC) 11 is used to measure the time difference between a reference clock REF having a first frequency and a feedback clock 1 having a third frequency, and corresponding real estate A time difference signal TD representing the time difference is used. The loop filter 120 is configured to filter the time difference signal TD (which may be a digital signal) and generate a control code C. The digital control oscillator 13 is controlled according to the control. The code generates an output clock OUT having a second frequency. The divide-by-N circuit 14A divides the output clock OUT having the second frequency by a divisor value N to generate a feedback with the third frequency. Pulse FB. It should be noted that the second frequency (i.e., the frequency of the output clock ττ and simultaneously the oscillation frequency of the digitally controlled oscillator 130) is controlled by the value of the control code c. In one embodiment, the output clock The frequency of out (ie, the second frequency, which is also the oscillation frequency of the digitally controlled oscillator 13〇) is increased (decreased) according to the increase (decrease) of the value of the control code, and due to the N function except the N circuit 14〇A, The frequency of the second frequency will be higher than the third frequency \ times: 4 200947873 When the control code c is too small (too large), the second frequency will also be too low (too high); and accordingly, the third frequency will also Too low (too high). In this way, the feedback clock FB will be too slow (too fast), and Therefore, the backward (leading) reference clock REF. As a result, the time difference signal TD is positive (negative value), and the positive value (negative value) indicates the time difference between the reference clock REF and the feedback clock FB. The digital loop filter 120 usually includes an integral function. Due to the integral function of the digital loop filter 12, when the time difference signal TD is positive (negative value), the control code c is increased (decreased). In the closed-loop manner, the control code c is adjusted (ie, increased or decreased) to enable the timing (ie, frequency or phase) of the feedback clock FB to be tracked (referred to as the reference clock). The timing of REF. Under steady state, the control code C is settle and is an appropriate value 'and the mean value of the time difference signal TD must be zero (zero) ' Otherwise the control code c will It will be blown due to the integral function of the digital loop filter 120 and cannot be stabilized. Therefore, in steady state, the third frequency must be equal to the first frequency. As a result, the second frequency is processed due to the processing of the N-circuit 140A. It is higher than the third frequency by N times, so the second frequency must be higher than the first frequency by n times. The divide-by-N circuit Η0 of the phase lock circuit 100A of FIG. 1A can conveniently use the divide-by-N counter (for example, set N to an integer (integer) )). However, because the number of turns of the counter needs to be an integer, if # is not an integer, then the program with a fixed divisor is used directly: the implementation will not work properly. Integer N (non-integer state except N function, must assume # = condition + α, where the condition is an integer, α is the fractional value between 04, and the divisor value of the counter can be arbitrarily set (shuffled). In one embodiment, the divisible value can be arbitrarily set with (乂 juice丨); as long as (AU+1) the probability of dividing the value is α, and the probability of dividing by I is (1_α), the effective divisor value will be equal to Α^ + α. In the prior art, the triangular integral is adjusted. The delta_sigma modulator is often used to dynamically set the divisor value. 5 200947873 The divide-by-N circuit 140A of the digital phase-locked loop 100A is replaced by a digital phase-locked loop PLL 100B with a divide-and-score function in FIG. 1B. The circuit 140B of the embodiment includes a dual-modulus divider (DMD) 150 and a: delta-sigma modulator (DSM) 160. The dual-modulus divider 15 is used to The output clock OUT is divided by a divisor value i or (乂, +1), and the feedback clock FB is generated according to the binary CARRY. The delta-sigma modulator 160 is used to receive the fractional value «, and is provided according to the feedback clock FB. One of the timings is to change the fractional value ^ to become the binary code CARRY. Triangle The purpose of the splitter 160 is to generate a binary code CARRY, for example, to generate CARRY as 0, possibly α, or 丨, possibly (1_α), and the average value of CARRY is equal to π. In this way, the output clock OUT is Divide by the value set arbitrarily between ^(4) (U1), and the average value is the divisor value of » to generate the feedback clock FB 〇 arbitrarily selected (Shuffling) divide by N circuit can effectively achieve N and divide The effect of fractional (fractionalWdivision). In this embodiment, in steady state, the average time difference between the reference clock and the feedback clock FB (ie, the average value of the time difference signal buckle) is still equal to zero' but the instantaneous time difference is not zero, and The maximum value can be almost 〇>/2. Among them, 7^0 is a time period in which the output clock τ is output, and the divisor value is arbitrarily set to a value. The instantaneous copper difference will cause the time difference signal TD to generate instantaneous noise, causing noise in the control code c, which will cause phase noise in the output clock OUT. In addition to generating phase noise by arbitrarily selecting the divisor value, the non-ideal time-to-digital converter 110 (in Figure 1A or Figure 1B) also contributes phase noise to the output clock. As shown in Figure lc, the 'time difference signal function' should be a ratio of the reference clock REF to the feedback clock four time difference, as shown in the figure, the broken line continues 6 200947873 No. However, in practice, the time-to-digital converter characteristics will deviate from the dashed line 170 as an arc 18 。. This problem of ideal linear deviation will cause the time difference signal TD to produce an error and produce unwanted phase noise to the output clock OUT. SUMMARY OF THE INVENTION One object of the present invention is to provide a fractional-N phase lock 1 loop that eliminates phase noise. * One of the objects of the present invention is to provide a fractional-N phase lock loop to reduce or avoid phase noise of the output clock due to instantaneous time difference. One of the objects of the present invention is to provide a fractional-N phase lock loop to reduce or avoid phase noise of the output clock due to non-ideal time to digital converters. One embodiment of the present invention provides a digital fractional_N phase locked loop. The digital fraction-N phase lock loop includes: a time to digital converter for converting a time difference between a reference clock and a feedback clock into a time difference signal; and a cancellation circuit for receiving time a difference signal, and generating a residual error signal according to the time difference signal and the instantaneous error signal; - a digital loop filter for filtering the residual error signal to generate a control code; a digital control An oscillator for generating an output clock according to a control code of the control code; a dividing circuit for receiving a fractional value (Fractional - number) to generate the instantaneous error signal; and controlling the output according to the fractional value The pulse is divided by a divide value to generate a feedback clock. - An embodiment of the present invention provides a method for reducing digital fractional-N phase lock loop phase noise, comprising the following steps: first, quantizing a reference clock and a back Giving a time difference of the clock to generate a time difference signal; generating a residual error signal according to the time difference signal and the instantaneous error signal; and then filtering the residual error signal to generate a control 7 200947873 code; use an control code to control an oscillator to generate an output clock; receive a 0 and! The sub-values ' are used to generate an instantaneous error signal; thereafter, the output clock is divided by a divisor value according to the fractional value. [Embodiment] The following description of the preferred embodiment of the present invention will be understood by those skilled in the art. It should be understood that the present invention may be implemented in various possible ways, and is not limited to the following examples. Or features in the examples. In addition, details that are known to others are not repeated or described in detail to avoid obscuring the invention. Still referring to FIG. 1B, in a typical fractional-N phase lock loop (fractional PLL) 100B, the function of dividing fractional AMivision can effectively set the dual-modulus divider (Dual-modulus divider, arbitrarily). DMD) The divisible value of 150 is executed. However, setting the divisor value arbitrarily will cause an instantaneous error in the time difference between the reference clock REF and the feedback clock FB. The instantaneous error of the time difference is measured by the time to digital converter 11 and digitized. However, the 'time to digital converter 11' is typically non-ideal and, therefore, produces distortion to the digital converter 110 as previously described. The present invention will eliminate the transient error of the time difference and the distortion of the time-to-digital converter 110 due to non-ideality. DETAILED DESCRIPTION OF THE INVENTION Embodiments of the present invention utilize a series expansion of a set of basis functions to describe the non-ideal characteristics of a time-to-digital converter. In a non-limiting exemplary embodiment, a Lei Jiande polynomial (Legendre polynomials series) can be implemented. The Lei Jiande polynomial contains a linear combination of Lei Jiande polynomials. The first few terms of the polynomial are listed as follows: Λ)(χ) = 1 Ο) Ρι(λ:) = X (2) Pi{x) = (3χ2-1)/2 (3) 8 200947873
Pi(x) = (5χ3-3χ)/2 (4) 户4(x) = (35χ4-30χ2+3)/8 (5) 户 5(x) = (63x5-70jc3+1 5jc)/8 ⑹ 雷建德多項式在區間[-1，1]為正交(Orth〇g〇nal)。詳細的說可適用 於下列關係式： lj Pm(x)p„(x)dx = - δ— 2η + ί ⑺ 其中各1”為克羅内克爾函數(Kronecker-delta fiinction)，即Pi(x) = (5χ3-3χ)/2 (4) Household 4(x) = (35χ4-30χ2+3)/8 (5) Household 5(x) = (63x5-70jc3+1 5jc)/8 (6) The Lei Jiande polynomial is orthogonal (Orth〇g〇nal) in the interval [-1,1]. In detail, it can be applied to the following relationship: lj Pm(x)p„(x)dx = - δ— 2η + ί (7) where each 1” is a Kronecker-delta fiinction, ie
雷建德多項式可被使用來作為一組基本方程式，以表示時間至數位 轉換器之轉換特性。令參考時脈REF與回授時脈FB間之時間差值之 瞬間誤差為ff，可使用雷建德多項式之序列展開(即雷建德多項式的線 性組合)表示時間差訊號TD(即時間至數位轉換器TDC之輸出）： TD = c0P0 (ε) + (ε) + 〇2Ρ2 (ε) + c3P3(e) + c,PA (ε) + ο5Ρ5(ε) + · · · (9) 〇 於數位分數-Ν相鎖迴路中利用一三角積分調變器(delta_sigma modulator)任意設定除數值，^•的值(即參考時脈與回授時脈FB 時間差之瞬間誤差)可被準確地預測。若展開係數(C{)，Cl，C2, C3, _.)也為 已知’則時間差值訊號TD之誤差亦可準確地預估並予以消除。 第2A圖顯示本發明一實施例之數位分數_]^相鎖迴路2〇〇a之示 意圖。數位分數-N相鎖迴路200A包含有一時間至數位轉換器 (time-to-digital converter，TDC) 210、一消除電路(Cancellation circuit) 215、一數位迴路濾波器(Digital loop filter)220、一數位控制震盪器 (Digitally controlled oscillator，DCO) 230、以及一除法電路(Divider circuit)240。一實施例，消除電路215包含有一加總電路(summation 9 200947873 circuit)270與一適應性級數展開函數單元28〇A。一實施例，除法電路 24〇包含有一雙模數除法器(dual-modulus divider，DMD) 250與一個 三角積分調變器(Delta-sigma modulator，DSM)260。 一實施例，時間至數位轉換器210用以量測參考時脈與回 授時脈FB之時間差值，且相應地產生用以表示該時間差值之一時間 差值訊號TD (為數位訊號)。加總電路27〇係用以將時間差值訊號TI) 減去一預設誤差訊號ρΕ，以產生一餘值誤差訊號(Residual efr〇r signal)RE。而數位迴路濾波器22〇係用以濾波餘值誤差訊號拙，且 產生控制碼C。數位控制震盪器230係用以依據控制碼c產生輸出時 脈OUT。雙模數除法器250係用以將輸出時脈〇υτ除以一除數值， 以產生回授時脈FB。其中，除數值係由一個進位訊號CARRY所控 .j而一角積分調變器260係用以將一分數數值^；調變至該進位訊號 CARRY ’且依據回授時脈FB提供之時脈產生一時間瞬間誤差訊號 左。適應性級數展開函數單元280A係用以接收瞬間誤差訊號e與餘值 誤差訊號RE，且產生預設誤差訊號PE。預設誤差訊號pE可用雷建 德多項式級數展開表示： pE = S〇P0(e) + 〇λΡχ (f) + e2P2(s) + 〇Ά{ε) + dA(£) + +...⑼） 其中’該些具有小帽(hat)之係數表示方程式(9)巾雷建德多項式級 數之估計絲。-實補，㈣估計絲可制以最小均平方(_ mean square，LMS)為基礎的演算法： £(^) = £(〇ld) +μ.ρη(ε).^{〇ΐη = 〇Λ2χ (1 ^ 其中，//為一適應性常數(adaptati〇n c〇nstant)。該常數必須足夠 小以確保適應性運算的收敛。上標“(〇ld)”表示適應性運算前的一舊 的數值(oldvalue)，而上標“(new)”表示適應性運算後的一新數值。實 200947873 際上’假若時間差值訊號XD被標準化(n〇rmalized)與y^c〇/2有關(即 TD=±1當參考時脈REF與回授時脈FB之時間差為±JW2 (其中Γ⑽ 表不輸出時脈OUT之一周期(cycle period))且瞬間誤差訊號^亦被標準 化(在區間[-1，1])，則#的典型數值為〇 〇卜須注意，#越大收斂的速 度越快’但適應性雜訊(adaptation noise)越大；相反地，On the ec)ntrar^，"越小收斂的速度越慢，但適應性雜訊(adaptation noise)越小。 實際上，"可在初始狀態時設定為較大的值以幫助收斂；而在收斂之 後將//設定為較小的值以減少適應性雜訊。一實施例，在初始狀態 時’將所有的估計係數設為零且將不會被適應性調整(adapted)直到 數位分數-N相鎖迴路達到穩態狀態(steady state condition)。此穩態狀 態可由計時器暫停(time-out)來確認(其係依據一預設時間來設置，此 預設時間為數位分數-N相鎖迴路達到穩態的時間）、或是由確認時間 差值訊號TD已完全落入標準時間區間[_1，1]來確認。該適應性運算 可連續或間歇地執行。 簡言之’於一典型實施例中，第2A圖顯示之適應性級數展開函 數單元280A係接收瞬間誤差訊號^與餘值誤差訊號re，且依據方程 式(10) ' (11)與方程式(1)〜(6)定義之雷建德多項式來產生預設誤差訊 號PE。當雷建德多項式展開(方程式(10》之項次之數值依據使用者之 判定選擇時，通常係選擇4-6個項次即足夠得到滿意的準確度。再 者’熟悉本領域之技術者可以各種方式、形式實施所有的方程式，只 要保有數學上的等效(mathematical equivalence)即可。舉例而言，可轉 換雷建德多項式級數至泰勒級數(Taylor series)藉由荒集瞬間誤差^同 階(order of power)之項(即蒐集所有£：的項、所有的^項、所有的y 項、…）。 11 200947873 第2B圖顯示本發明另—實施例之數位分數则目鎖迴路 200B 之 示意圖。該級數展開係以時間差值訊號TO為基礎(替代餘值誤差訊 號RE)。於此，一替換的適應性級數展開函數單元28〇B係用來替代 第2A圖之適應性級數展開函數單元2·。相同的雷建德多項式級 數(方程式⑽)仍然用來估算預測誤差訊號pE，但其係數部份則採用 下列公式： ^(new) _ 其中，n=0, 1，2, 3，...，且㈣表示a乘以B(A ti_ B)的統計 平均(statistical average)。簡言之，於本替換之實施例中，第2b圖之 適應性級數制函料S 28GB雜㈣酿^訊動麵間差值訊 號TD，且依據方乘式(10)、⑽與由方程式(如6)定義之雷建德多項 式來產生_誤差魏PE。須注意，再次聲明誠本賴之技術者 可依據其需求以各種方式、形式實施所有的方程式，只要财數學上 的等效(mathematical equivalence)即可。再者，須注意方程式(12)之單 位係預先得知㈣數’不需要根據數？估算丨。假若瞬_差訊號係 ❹ 被標準化且落於預設關，例如[丨，]]，如此便可預先知道，而不須 執行下列數字的估算 {P„(e),Pn(e)) 2n + l (13) 根據方程式(7)之正交特性。一實施例，於初始狀態下所有估測 係數係設定為零，且將不會使用於適應性運算(adapted)直到數位分數 -N相鎖迴路達到穩態狀態(stea(jy statee〇n(jiti〇n)。須注意，適應性運 算(adaptation)(方程式(12))可連續或間歇地實施。 本發明第2A、2B圖實施例之時間至數位轉換器21〇與數位控制 震盪器230為本領域技術者所熟悉之技術，因此不再贅述其細節。而 12 200947873 右不熟悉時間至數轉懸，可參考美國彻服2_4號。若不 熟悉數位控制震廬器可參考美國專利第US718386〇號。 數位迴路狀n 22〇可由電路設計者欺鋪所需讀波響應 來選擇。於~"示例性之實施例中，數位迴路齡器22G可執行下列離 散時間系統響應式： Η{ζ) = ΚΡζι+ΚιΖΛ/{\-ζΛ) (14) 其中，ΚΡ與&兩參數可由電路設計者指定。 雙模數除法H 250可為-計數式除法器(_时七_咖祝）， ® 其採用之除數值可為Νίι«(當CARRY為1)或Nint+1 (當CARRY為〇)。 其中’ Nint為數位分數N型相鎖迴路(2〇〇A或2〇〇B)之數位分數除算 比例(fractional division rati0)之整數部份。本領域之技術者只要熟悉相 鎖迴路便會熟悉計數式雙模數除法電路之實施方式，因此不再贊述其 細節。 第3圖顯示本發明一實施例之三角積分調變器3〇〇之示意圖。三 角積分調變器300適用於實施第2A或2B圖中的三角積分調變器 260。調變器3⑻係與回授時脈FB同步運作。調變器3〇〇包含有一 ◎ 第一加總電路310、一積分器320、舍入運算器⑽如出％ 〇perat〇r) 330、一第二加總電路340、以及一增益/延遲(gain/delay)元件35〇。調 -變器300基本上為一累積器(accumulat〇r)，其利用積分器32〇累加分 ' 數<其中〇<α<1)。舍入運算器330將累加量進行舍入運算，以產生 進位訊號CARRY。當累加量超過〇.5，進位訊號CARRY為丨，且第 -加總電路310將累加器之數值_1 ;而當累加量未超過〇5，進位訊 號CARRY為0，此時不須將累加器之數值減去任何數值。依此方式， 累加量可被控制在區間[-0.5, 0.5]’且進位訊號CARRY僅可為〇或】。 13 200947873 瞬間誤差訊號係利用第二加總電路340計算舍入運算器330之 輸入輸出時間差’且由增益/延遲元件350對該時間差進行延遲及/或 縮放產生。如第3圖所示，增益/延遲元件350標記之因子(factor)z-l 表示一單位延遲’而因子2為增益因子用以確認瞬間誤差£之結果是 否被標準化落於區間[-1，1]中。 - 只要不脫離本發明之精神與範圍，本發明之技術可以各種替換的 實施例來實現。舉例而言’較高階的三角積分調變器(pSM)亦可使用 於本發明。依此方式，進位訊號CARRY不為二進制訊號，而會變為 © 多階整數訊號(Multi-level integer signal) ’且雙模數除法器須要以多模 數除法器來替換。 另外’各種類的級數展開式亦可用來替換雷建德多項式級數。舉 例而言，可利用泰勒級數(Taylor series)、傅利葉級數(Fourier series)、… 來替換。熟悉本領域之技術者在不脫離本發明之精神與範_下，可依 據其需求自行判定，以選擇適當的數學級數展開式來應用。例如，選 擇泰勒級數來替換時，只須分別將定義於方程式(1)〜(6) (n=〇〜5)之雷 建德多項式之方程式Pn(x)替換為Λ 〇〇 = Y(n=〇〜5)。然而，須注意， ❹ 方程式之幂次(power functions)彼此不為正交。也就是說，尺„〇〇 = X" 不與= x正交，假設n不等於m。（兩方程式正交係必須在兩方 程式之間沒有統計相關性(zero statistical correlation)才成立。依此方 . 式’第2B圖之實施例200B與方程式(12)合併使用來進行適應性運算 (adaptation)並不適當，因為方程式〇2)係以正交特性為基礎，方程式 (12)的合併使用只有在基礎方程式之展開為正交時才適當。然而，第 2B圖之實施例200B仍然可以使用，只要替換之適應性運算包含有格 萊姆一施密特正交化方法(Gram-Schmidt orthgonalization)即可。格萊 姆一施密特正交化方法為本領域之技術者所熟悉，不再贅述其細節； 14 200947873 若不熟悉者，可參考標準的數學教科書。無論如何，在選擇使用第 2B圖之實施例2〇〇B時，可採用作為級數展開的該些正交方程式。 以上雖以實施例說明本發明，但並不因此限定本發明之範圍，只 要不脫離本發明之要旨，熟悉本領域之技術者可進行各種變形或變 更’均落入本發明之申請專利範圍之範疇。 ' 【圖式簡單說明】 • 第1A圖顯示習知數位相鎖迴路之示意圓。 第1B圖顯示習知數位分數N型相鎖迴路之示意圖。 ® 第1C圖顯示一時間至數位轉換器之轉換特性。 第2A圖顯不本發明一實施例之數位分數n翻鎖迴路之示意 圖。 第2B圖顯示本發明另一實施例之數位分數N型相鎖迴路之示意 圖。 第3醜不第2A、2B圖中三角積分調變器之實施例之示意圖。 【主要元件符號說明】 100A、100B、200A、200B 相鎖迴路 ❹ 110、210轉換器 120、220濾波器 130、230壓控震盪器 140A、140B、240 除法電路 150、250除法器 160、260調變器 270、310、340加總電路 280A、280B適應性級數展開函數單元 320積分器 15 200947873 330舍入運算器 350增益/延遲元件The Lei Jiande polynomial can be used as a set of basic equations to represent the conversion characteristics of a time-to-digital converter. Let the instantaneous error of the time difference between the reference clock REF and the feedback clock FB be ff, and the sequence expansion of the Lei Jiande polynomial (ie, the linear combination of Lei Jiande polynomials) can be used to represent the time difference signal TD (ie, time to digital conversion) Output of TDC): TD = c0P0 (ε) + (ε) + 〇2Ρ2 (ε) + c3P3(e) + c,PA (ε) + ο5Ρ5(ε) + · · · (9) 〇 in digital score - In the Ν phase lock loop, a delta_sigma modulator is used to arbitrarily set the divisor value, and the value of ^• (ie, the instantaneous error between the reference clock and the feedback clock FB time difference) can be accurately predicted. If the expansion coefficients (C{), Cl, C2, C3, _.) are also known, then the error of the time difference signal TD can also be accurately estimated and eliminated. Fig. 2A shows the intention of the digital fraction _]^ phase lock loop 2〇〇a according to an embodiment of the present invention. The digital fraction-N phase lock loop 200A includes a time-to-digital converter (TDC) 210, a cancellation circuit 215, a digital loop filter 220, and a digital bit. A Digitally Controlled Oscillator (DCO) 230, and a Divider circuit 240. In one embodiment, the cancellation circuit 215 includes a summation circuit (summation 9 200947873 circuit) 270 and an adaptive series expansion function unit 28A. In one embodiment, the divide circuit 24A includes a dual-modulus divider (DMD) 250 and a delta-sigma modulator (DSM) 260. In one embodiment, the time-to-digital converter 210 is configured to measure the time difference between the reference clock and the feedback clock FB, and correspondingly generate a time difference signal TD (which is a digital signal) for indicating the time difference. . The summing circuit 27 is configured to subtract a predetermined error signal ρΕ from the time difference signal TI) to generate a residual error signal (Residual efr〇r signal) RE. The digital loop filter 22 is used to filter the residual error signal 拙 and generate the control code C. The digitally controlled oscillator 230 is operative to generate an output clock OUT in accordance with the control code c. The dual modulus divider 250 is configured to divide the output clock τ by a divide value to generate a feedback clock FB. Wherein, the divide value is controlled by a carry signal CARRY. The angle integral modulator 260 is used to adjust a fractional value ^; to the carry signal CARRY ' and generate a clock according to the clock provided by the feedback clock FB. Time instant error signal left. The adaptive series expansion function unit 280A is configured to receive the instantaneous error signal e and the residual error signal RE, and generate a preset error signal PE. The preset error signal pE can be expressed by the Lei Jiande polynomial series expansion: pE = S〇P0(e) + 〇λΡχ (f) + e2P2(s) + 〇Ά{ε) + dA(£) + +... (9)) where the coefficients of the hats represent the estimated filaments of the equation (9) of the Lei Jiande polynomial series. - Real complement, (iv) Estimate the silk based on the least mean square (_ mean square, LMS) based algorithm: £(^) = £(〇ld) +μ.ρη(ε).^{〇ΐη = 〇 Λ2χ (1 ^ where // is an adaptive constant (adaptati〇nc〇nstant). The constant must be small enough to ensure convergence of the adaptive operation. The superscript "(〇ld)" indicates an old before the adaptive operation The value (oldvalue), and the superscript "(new)" represents a new value after the adaptive operation. Actually 200947873, if the time difference signal XD is standardized (n〇rmalized) and y^c〇/2 (ie TD=±1 when the time difference between the reference clock REF and the feedback clock FB is ±JW2 (where Γ(10) indicates the output of the clock period cycle) and the instantaneous error signal ^ is also normalized (in the interval [ -1,1]), then the typical value of # is 〇〇 须 须 须 # # # # # # # # # # # 越大 越大 越大 越大 越大 越大 越大 越大 越大 越大 越大 越大 越大 越大 越大 越大 越大 越大 越大 越大 越大 越大 越大 越大 越大 越大 越大 越大 越大"The smaller the convergence, the slower the response, but the smaller the adaptation noise. In fact, " can be set to a larger value in the initial state to help convergence; After convergence, // is set to a smaller value to reduce adaptive noise. In one embodiment, 'all estimated coefficients are set to zero in the initial state and will not be adaptively adjusted until the digital score The -N phase lock loop reaches a steady state condition. This steady state state can be confirmed by a timer time-out (which is set according to a preset time, the preset time is a digital score - N The phase of the phase-locked loop reaches the steady state, or is confirmed by the confirmation time difference signal TD has completely fallen into the standard time interval [_1, 1]. The adaptive operation can be performed continuously or intermittently. In an exemplary embodiment, the adaptive series expansion function unit 280A shown in FIG. 2A receives the instantaneous error signal ^ and the residual error signal re, and according to equation (10) '(11) and equations (1) to (6) The defined Lei Jiande polynomial is used to generate the preset error signal PE. When the Lei Jiande polynomial is developed (the value of the equation (10) is selected according to the user's judgment, it is usually sufficient to select 4-6 items. Get satisfactory accuracy. Again, 'cooked Those skilled in the art can implement all the equations in various ways and forms, as long as mathematical equivalence is maintained. For example, the Lei Jiande polynomial series can be converted to Taylor series. By the moment of error, the order of power (that is, the collection of all items of £:, all items, all y items, ...). 11 200947873 Figure 2B shows a schematic diagram of the digital score of the other embodiment of the present invention. The series expansion is based on the time difference signal TO (instead of the residual error signal RE). Here, an alternative adaptive series expansion function unit 28 〇 B is used instead of the adaptive series expansion function unit 2· of Fig. 2A. The same Lei Jiande polynomial series (equation (10)) is still used to estimate the prediction error signal pE, but the coefficient part uses the following formula: ^(new) _ where n=0, 1, 2, 3,.. And (4) represents the statistical average of a multiplied by B (A ti_ B). In short, in the alternative embodiment, the adaptive series system of the 2b figure is S 28GB (4), and the difference between the signals is TD, and according to the square multiplication formulas (10), (10) and The Lei Jiande polynomial defined by the equation (such as 6) produces _error Wei PE. It should be noted that once again, the technicians who rely on the company can implement all the equations in various ways and forms according to their needs, as long as the mathematical equivalence is sufficient. Furthermore, it should be noted that the unit of equation (12) is known in advance (four) number does not need to be based on the number? Estimate 丨. If the instantaneous signal signal system is standardized and falls within the preset level, such as [丨,]], it can be known in advance without performing the estimation of the following numbers {P„(e), Pn(e)) 2n + l (13) According to the orthogonality of equation (7). In one embodiment, all the estimated coefficients are set to zero in the initial state and will not be used for adaptive operations until the digital fraction-N phase The lock loop reaches a steady state (stea (jy statee〇n (jiti〇n). It should be noted that the adaptation (equation (12)) can be implemented continuously or intermittently. Embodiments 2A, 2B of the present invention The time-to-digital converter 21 and the digitally controlled oscillator 230 are familiar to those skilled in the art, so the details are not described again. And 12 200947873 is unfamiliar with the time-to-number suspension, and can refer to the US 2_4 If you are unfamiliar with the digital control shaker, refer to US Pat. No. US718386. The digital loop shape n 22〇 can be selected by the circuit designer to trick the desired read wave response. In the exemplary embodiment, the digit The loop age device 22G can perform the following discrete time system responsiveness: Η{ζ ) = ΚΡζι+ΚιΖΛ/{\-ζΛ) (14) where ΚΡ and & parameters can be specified by the circuit designer. The dual modulus division H 250 can be a -counting divider (_7 _ _ _) ® The divisor value can be Νίι« (when CARRY is 1) or Nint+1 (when CARRY is 〇). where 'Nint is a digital fractional N-type phase-locked loop (2〇〇A or 2〇〇B) The digital fraction divides the integer part of the fractional division rati0. Those skilled in the art will be familiar with the implementation of the counting dual-modular division circuit as long as they are familiar with the phase-locked loop, and therefore the details are not mentioned. A schematic diagram of a delta-sigma modulator 3〇〇 according to an embodiment of the present invention. The delta-sigma modulator 300 is suitable for implementing the delta-sigma modulator 260 in the 2A or 2B diagram. The modulator 3(8) and the feedback clock FB Synchronous operation. The modulator 3 includes a first summing circuit 310, an integrator 320, a rounding operator (10) such as % 〇perat〇r) 330, a second summing circuit 340, and a gain. /delay (gain/delay) element 35. The modulator-changer 300 is basically an accumulator (accumulat〇r), which benefits The integrator 32 〇 accumulates the number ', < 〇 < α < 1). The rounding operator 330 rounds the accumulated amount to generate the carry signal CARRY. When the accumulated amount exceeds 〇.5, the carry signal CARRY is丨, and the first-to-sum total circuit 310 will accumulate the value _1; and when the accumulated amount does not exceed 〇5, the carry signal CARRY is 0, and it is not necessary to subtract the value of the accumulator by any value. In this way, the accumulated amount can be controlled in the interval [-0.5, 0.5]' and the carry signal CARRY can only be 〇 or 】. 13 200947873 The instantaneous error signal is calculated by the second summing circuit 340 to calculate the input/output time difference ' of the rounding operator 330 and is delayed and/or scaled by the gain/delay element 350. As shown in Fig. 3, the factor z1 of the gain/delay element 350 indicates a unit delay' and the factor 2 is a gain factor to confirm whether the result of the instantaneous error £ is normalized to the interval [-1, 1]. in. The technology of the present invention can be implemented in various alternative embodiments without departing from the spirit and scope of the invention. For example, a higher order triangular integral modulator (pSM) can also be used in the present invention. In this way, the carry signal CARRY is not a binary signal, but becomes a © Multi-level integer signal and the dual modulus divider needs to be replaced by a multi-modulo divider. In addition, the various types of series expansion can also be used to replace the Lei Jiande polynomial series. For example, it can be replaced with a Taylor series, a Fourier series, .... Those skilled in the art can apply themselves according to their needs without having to deviate from the spirit and scope of the present invention to select an appropriate mathematical progression. For example, when selecting a Taylor series to replace, it is only necessary to replace the equation Pn(x) of the Lei Jiande polynomial defined in equations (1) to (6) (n=〇~5) with Λ 〇〇 = Y ( n=〇~5). However, it should be noted that the power functions of the equations are not orthogonal to each other. That is to say, the rule 〇〇 X = X " is not orthogonal to = x, assuming that n is not equal to m. (The two-equation orthogonal system must be established without statistical correlation between the two equations. The combination of the embodiment 200B of the formula 2B and the equation (12) for adaptive operation is not appropriate because the equation 〇 2) is based on the orthogonal characteristic and the equation (12) is combined. It is only appropriate when the expansion of the basic equation is orthogonal. However, the embodiment 200B of Fig. 2B can still be used as long as the adaptive operation of the replacement includes the Gram-Schmidt orthgonalization method (Gram-Schmidt orthgonalization) The Gram-Schmidt orthogonalization method is familiar to those skilled in the art and will not be described in detail; 14 200947873 If you are not familiar, you can refer to the standard mathematics textbook. In any case, choose to use In the second embodiment of Fig. 2B, the orthogonal equations can be used as the series expansion. Although the invention has been described above by way of examples, the scope of the invention is not limited thereby It is to be understood that those skilled in the art can make various modifications and changes within the scope of the patent application of the present invention. ' [Simple description of the drawing] • Figure 1A shows the schematic of a conventional digital phase locking circuit Figure 1B shows a schematic diagram of a conventional digital fractional N-type phase-locked loop. ® Figure 1C shows the conversion characteristics of a time-to-digital converter. Figure 2A shows a digital fraction n-locking loop of an embodiment of the present invention. Figure 2B is a schematic diagram showing a digital fractional N-type phase-locked loop according to another embodiment of the present invention. Figure 3 is a schematic diagram of an embodiment of a triangular-integral modulator in Figures 2A and 2B. 100A, 100B, 200A, 200B phase locked loop ❹ 110, 210 converter 120, 220 filter 130, 230 voltage controlled oscillator 140A, 140B, 240 division circuit 150, 250 divider 160, 260 modulator 270, 310 340 plus total circuit 280A, 280B adaptive series expansion function unit 320 integrator 15 200947873 330 rounding operator 350 gain / delay element