TWI397076B - Method and system for decoding data in non-volatile storage using reliability metrics based on multiple reads - Google Patents

Description

Decoded data method and system using multi-read based reliability measurement in non-volatile storage

This invention relates to non-volatile memory.

This application is the following application for co-delivery in the same application: a non-volatile storage for use in the use of multiple reading-based reliability measurements, filed on March 29, 2007 US Patent Application No. 11/693,649 (Method for Decoding Data in Non-Volatile Storage Using Reliability Metrics Based On Multiple Reads) (file number SAND-1223US0) (approved on March 8, 2011) U.S. Patent No. 7,904,793; the application entitled "Non-Volatile Storage With Decoding of Data Using Reliability", which was filed on March 29, 2007. "Metrics Based On Multiple Reads"" (file number SAND-1223US1) US Patent Application No. 11/693,672 (now abandoned); filed on March 29, 2007, entitled "Using Pre-Adjusted Waveforms and Method of Reading Non-Volatile Storage Using Pre-Conditioning Waveforms And Modified Reliability Metrics" (file number SAND-1224US0) US Patent Application No. 11/693,663 (issued US Patent No. 7,797,480 on September 14, 2010); and filed on March 29, 2007 entitled "Using Pre-Adjusted Waveforms and Modified Reliability Metering to Read U.S. Patent Application Serial No. 11/693,668 (Non-Volatile Storage With Reading Using Pre-Conditioning Waveforms and Modified Reliability Metrics) (file number SAND-1224US1), each of which is abandoned One is incorporated herein by reference.

Semiconductor memory has become increasingly popular for use in a variety of electronic devices. For example, non-volatile semiconductor memory is used in cellular phones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices, and other devices. The most popular non-volatile semiconductor memory There is an electric eraseable programmable read only memory (EEPROM) and flash memory. In the case of flash memory (also EEPROM type), the content of the entire memory array or the contents of a portion of the memory can be erased in one step as compared to a conventional fully characterization EEPROM.

Both conventional EEPROM and flash memory utilize a floating gate that is positioned above the channel region in the semiconductor substrate and insulated from the channel region. The floating gate is positioned between the source region and the drain region. The control gate is provided above the floating gate and insulated from the floating gate. The threshold voltage (V _TH ) of the thus formed transistor is controlled by the amount of charge remaining on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before the transistor is turned on to allow conduction between its source and drain is controlled by the charge level on the floating gate.

Some EEPROM and flash memory devices have floating gates for storing two charge ranges, and thus, memory elements can be programmed between two states (eg, erased and stylized) / erase. This flash memory device is sometimes referred to as a binary flash memory device because each memory element can store one data bit.

Multi-state (also referred to as multi-level) flash memory devices are implemented by identifying a plurality of distinct allowable/effective programmed threshold voltage ranges. Each distinct threshold voltage range corresponds to a predetermined value of the set of data bits encoded in the memory device. For example, when each memory element can be placed in one of four discrete charge bands corresponding to four distinct threshold voltage ranges, the element can store two data bits.

Typically, the program voltage V _PGM applied to the control gate during program operation is applied as a series of pulses that increase in magnitude over time. In one possible approach, the magnitude of the pulse is increased by a predetermined step size, for example, 0.2-0.4 V, with each successive pulse. V _PGM can be applied to the control gate of the flash memory component. The verification operation is performed during the period between the program pulses. That is, the stylized level of each of the components in the parallel stylized component group is read between consecutive stylized pulses to determine whether it is equal to or greater than the verify level to which the component is programmed. For a multi-state flash memory device array, a verification step can be performed for each state of the component to determine if the component has reached its data association verification level. For example, a multi-state memory element capable of storing data in four states may need to perform a verify operation for three comparison points.

In addition, when programming an EEPROM or flash memory device (such as a NAND flash memory device in a NAND string), V _PGM is typically applied to the control gate and the bit line is grounded, resulting in a Electrons of the channels of the memory elements (eg, storage elements) are injected into the floating gates. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the memory component rises, making the memory component considered to be in a stylized state. It can be found in U.S. Patent No. 6,859,397, entitled "Source Side Self Boosting Technique For Non-Volatile Memory", and U.S. Patent Application Publication No. 2005/0024939, entitled "Detecting Over Programmed Memory", published on February 3, 2005. More information on this stylization; the entire contents of which are incorporated herein by reference.

Once the non-volatile storage element has been programmed, the important system can be high Reliability to read back its stylized state. However, the sensed stylized state may sometimes be different from the expected stylized state due to trap site noise and other factors. Perhaps the most important source of noise is 1/f noise (including random telegraph noise), which is the result of electronic interception and de-interception to intercept sites located in tunnel oxides or elsewhere.

The present invention addresses these and other problems by providing a method for decoding data stored in non-volatile memory using multiple read operations.

In one embodiment, a method for decoding data in a non-volatile storage device includes performing a multiple sensing operation on at least one non-volatile storage element and utilizing iterative probability decoding to determine at least one non-volatile storage element The stylized state in which iterative probability decoding utilizes reliability metering based on multiple sensing operations. For example, the reliability measure can include a logarithmic approximation ratio.

The method can further include determining an initial set of reliability measures for iterative probability decoding based on the multiple sensing operations. Alternatively, iterative probability decoding may initially iterate using a first reliability measure based on the first sensing operation. The first reliability measure is adjusted to obtain an adjusted reliability measure when the probability decoding is further iterated. The adjusted reliability measure is then further adjusted based on subsequent sensing operations while the probability decoding further iterates.

In another embodiment, a method for decoding data in a non-volatile storage device includes performing a first sensing operation on at least one non-volatile storage element Providing, based on the first sensing operation, the first codeword, performing the decoding process for the first codeword by using the first reliability metering set based on the first codeword, and not satisfying the decoding process The second sensing operation is performed on the at least one non-volatile storage element and the decoding process is adjusted based on the second sensing operation in a condition. For example, the first condition may include a decoding process that converges or satisfies a given number of parity checks within a given time period or within a given number of iterations.

In another embodiment, a method for decoding data in a non-volatile storage device includes performing a first sensing operation on at least one non-volatile storage element, providing at least one representation based on the first sensing operation The first data of the sensed stylized state of the non-volatile storage element and the probability data based on the first data are used to initiate an iterative decoding process for the first data. The method further includes performing a second sensing operation on the at least one non-volatile storage element, providing a second material indicative of the sensed stylized state of the at least one non-volatile storage element based on the second sensing operation, and The iterative decoding process continues by adjusting the recently utilized value of the probabilistic meter based on the second data.

In another embodiment, a method for decoding data in a non-volatile storage device includes performing a first sensing operation on at least one non-volatile storage element, providing at least one representation based on the first sensing operation The first data of the sensed stylized state of the non-volatile storage element, using the probability data based on the first data to initiate an iterative decoding process for the first data, and providing a measure indicative of the progress of the iterative decoding process. If the measurement indicates that the progress is not satisfactory, the method further includes based on the second sensing operation A second data representative of the sensed stylized state of the at least one non-volatile storage element is provided, and the iterative decoding process is restarted using probability measurements based on the first data and the second data.

In another embodiment, a method for operating a non-volatile storage includes performing a plurality of sensing operations on a set of non-volatile storage elements, providing a set of reliability measurements based on sensing operations, and storing reliability The set of measurements is for an iterative probability decoding process for determining a stylized state of at least one non-volatile storage element of the set of non-volatile storage elements based on at least the first and second subsequent sensing operations.

The present invention provides a method for decoding data stored in a non-volatile storage using multiple read operations.

One example of a memory system suitable for use in practicing the present invention utilizes a NAND flash memory structure that includes a plurality of transistors arranged in series between two select gates. The series connected transistors and select gates are referred to as NAND strings. Figure 1 is a top plan view showing a NAND string. Figure 2 is its equivalent circuit. The NAND string depicted in FIGS. 1 and 2 includes four transistors 100, 102, 104, and 106 that are connected in series and sandwiched between a first select gate 120 and a second select gate 122.

The NAND string connection of the gate 120 gate to the bit line 126 is selected. The NAND string connection of the gate 122 gate to the source line 128 is selected. The selection gate 120 is controlled by applying an appropriate voltage to the control gate 120CG. The selection gate 122 is controlled by applying an appropriate voltage to the control gate 122CG. Each of the transistors 100, 102, 104, and 106 has a control gate and a floating gate. The transistor 100 includes a control gate 100CG and a floating gate 100FG. Electricity The crystal 102 includes a control gate 102CG and a floating gate 102FG. The transistor 104 includes a control gate 104CG and a floating gate 104FG. The transistor 106 includes a control gate 106CG and a floating gate 106FG. The control gate 100CG is connected to the word line WL3, the control gate 102CG is connected to the word line WL2, the control gate 104CG is connected to the word line WL1, and the control gate 106CG is connected to the word line WL0. The control gate is also provided as part of the word line. In one embodiment, transistors 100, 102, 104, and 106 are each a storage element, also referred to as a memory unit. In other embodiments, the storage element may comprise a plurality of transistors, or may be different than the storage elements depicted in Figures 1 and 2. The selection gate 120 is connected to the selection line SGD (drain selection gate). The selection gate 122 is connected to the selection line SGS (source selection gate).

Figure 3 is a circuit diagram depicting three NAND strings. A typical architecture of a flash memory system utilizing a NAND structure would include several NAND strings. For example, three NAND strings 320, 340, and 360 are shown in a memory array with more NAND strings. Each of the NAND strings includes two select gates and four storage elements. Although four storage elements are illustrated for simplicity, modern NAND strings can have, for example, up to 32 or 64 storage elements.

For example, NAND string 320 includes select gates 322 and 327 and storage elements 323-326, NAND string 340 includes select gates 342 and 347 and storage elements 343-346, NAND string 360 includes select gates 362 and 367 and storage Elements 363-366. Each NAND string is connected to the source line by its select gate (eg, select gate 327, 347, or 367). The selection line SGS is used to control the source side selection gate. Various NAND strings 320, 340, and 360 by The selection transistors in the gates 322, 342, 362, etc. are selected to be connected to the respective bit lines 321, 341 and 361. These selective transistors are controlled by the drain select line SGD. In other embodiments, the select lines do not necessarily need to be common among the NAND strings; that is, different select lines can be provided for different NAND strings. Word line WL3 is coupled to the control gates for storage elements 323, 343, and 363. Word line WL2 is coupled to control gates for storage elements 324, 344, and 364. Word line WL1 is coupled to control gates for storage elements 325, 345, and 365. Word line WL0 is coupled to control gates for storage elements 326, 346, and 366. It can be seen that each bit line and each NAND string contains a row of storage element arrays or sets. The word lines (WL3, WL2, WL1, and WL0) contain arrays or sets of columns. Each word line connects the control gate of each of the storage elements in the column. Alternatively, the control gate can be provided by the word line itself. For example, word line WL2 provides control gates for storage elements 324, 344, and 364. In practice, there can be thousands of storage elements on a word line.

Each storage element can store data. For example, when storing a digital data bit, the range of possible threshold voltages (V _TH ) of the storage elements is divided into two ranges, which are assigned logical data "1" and "0". In one example of a NAND type flash memory, the _VTH is negative after erasing the storage element and is defined as a logical "1". The V _TH after the program operation is positive and is defined as a logic "0". When the _VTH is negative and an attempt is made to read, the storage element will turn on to indicate that the logical "1" is stored. When the _VTH is positive and an attempt is made to read, the storage element will not turn on, indicating that the logic "0" is stored. The storage element can also store multiple information levels, for example, multiple digital data bits. In this case, the range of V _TH values is divided into the number of data levels. For example, if four information levels are stored, there will be four _VTH ranges assigned to the data values "11", "10", "01", and "00". In one example of a NAND type memory, the _VTH after the erase operation is negative and is defined as "11". Positive V _TH values are used for states "10", "01", and "00". The particular relationship between the data programmed into the storage element and the threshold voltage range of the component depends on the data encoding mechanism used to store the component. For example, U.S. Patent No. 6,222,762, and U.S. Patent Application Publication No. 2004/0255090, the entire disclosure of each of which is incorporated herein by reference in its entirety, is incorporated herein.

Examples of NAND-type flash memory and its operation are provided in U.S. Patent Nos. 5,386,422, 5,522,580, 5,570,315, 5,774,397, 6,046,935, 6,456,528 and 6,522,580, each of which Both are incorporated herein by reference.

When the flash storage component is programmed, a program voltage is applied to the control gate of the storage component and the bit line associated with the storage component is grounded. The electrons from the channel are injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the _{VTH of the} storage element rises. To apply a program voltage to the control gate of the programmed storage element, the program voltage is applied to the appropriate word line. As discussed above, one of the storage elements of each of the NAND strings shares the same word line. For example, when the storage element 324 of FIG. 3 is programmed, a program voltage is also applied to the control gates of the storage elements 344 and 364.

Figure 4 depicts a system for encoding and decoding data in non-volatile storage System. Data stored in non-volatile memory can be encoded and decoded in a manner that mitigates noise effects. Perhaps the most important source of noise is 1/f noise (including random telegraph noise), which is the result of electronic interception and de-interception to intercept sites located in tunnel oxides or elsewhere. The noise is not a complete result of the loss of the channel electrons entering the interception site, because it is due to the fact that the electron/hole in the charged intercept site is applied to the channel in the vicinity by the charged intercept site. The electric field on the area affects the flow of other electrons in the channel. In addition, the area of the channel under the influence of a single intercept site will form a larger portion of the channel as the storage element is scaled down.

Many of the noise storage elements are subject to a single intercept site, and this conclusion is based on the binary nature of their current values, ie, the storage element has a current /V _TH value if the intercept is occupied and is not intercepted. In the case of being occupied, there is another different current /V _TH value. Thus, when the storage element is biased under DC conditions equivalent to the read conditions, many of the storage elements exhibit a bimodal distribution of current values, wherein the two narrow distributions have peaks that are substantially separated from each other. However, some storage elements are subject to more than a single noise interception site. In addition, not every intercepting site can cause noise behavior because there may be intercepting sites that are consistently empty or consistently occupied during reading conditions. Moreover, an interception site that is easily communicable with an electrode and results in a large number of transitions between empty and occupied during a single integration time (eg, read cycle) will indicate little or no noise because of its average effect. More or less the same for any integration time/measurement operation. This can be explained by the averaging concept or more precisely by the central limit theorem. Moreover, the probability of occupancy of the intercepting site can be modulated by the intercepting site to immerse the electric field itself. In addition, those intercepting sites that are more detrimental to the read operation are intercepted sites with longer occupied/non-occupied lifetimes. These intercepting sites can be thought of as parasitic memory devices that interfere with the normal operation of the memory. The write/erase cycle can and does generate additional intercept sites and cause more noise.

As a result, the read operation can be affected by noise in the storage element. Although error correction coding and decoding mechanisms can handle some of the errors caused by noise and other factors, additional advantages can be achieved by performing multiple read operations as explained herein. An example method is depicted in the encoding/decoding system of FIG. 4, which includes an encoder 402, a non-volatile storage 404, an LLR (Logarithmic Likelihood Ratio) table 406, and a decoder 408. The encoder 402 receives the information bits stored in the non-volatile storage 404, also referred to as user data. The information bits are represented by the matrix i=[1 0]. Encoder 402 implements an error correction encoding process in which a parity bit is added to the information bit to provide data represented by a matrix or codeword v = [1 0 1 0], which indicates that two parity bits have been attached to the data Bit. This is a simplified example of the cost of additional items that result in high parity bits. In practice, codes with lower additional items can be utilized. For example, a low density parity check (LDPC) code, also known as a Gallager code, can be utilized. These codes are typically applied to a plurality of codewords that are encoded across a plurality of storage elements such that the co-located bits are distributed among the storage elements. Additional information about LDPC can be found in D. MacKay's Information Theory, Inference and Learning Algorithms (Cambridge University Press 2003, Chapter 47). Data bits can be mapped by stylizing non-volatile storage elements into a stylized state (eg, X=6, which corresponds to v (see Figure 9a)) The data is directed to the logical page and stored in the non-volatile storage 404. In the case of the four-bit data matrix v, 16 stylized states are available.

Then, when it is necessary to retrieve the stored data, the non-volatile storage is read. However, due to the noise as mentioned, the read status can sometimes be mistaken. In an example method, the first read Y1 results in a stylized state 7 represented by the codeword y1=[1 0 1 1], and the second read Y2 is obtained from the codeword y2=[1 0 1 0] Indicates the stylized state 6. In a possible embodiment, a iterative probability decoding process is utilized that implements error correction decoding corresponding to the error correction coding at encoder 402. Additional details regarding iterative probability decoding can be found in the D. MacKay article mentioned above. Iterative probability decoding attempts to decode the codeword by assigning an initial probability measure to each bit in the codeword. The probability measure indicates the reliability of each bit, that is, the probability that the bit is not mistaken. In one method, the probability measure is the log likelihood ratio (LLR) obtained from the LLR table 406. The LLR value is a measure of reliability, which we use to know the values of the various binary bits read from the storage element.

LLR for bits Given, where P(v=0│Y) is the probability that the bit is 0 given the read state is Y, and P(v=1│Y) is the bit in the given read state. The probability of 1 under the condition of Y. Thus, based on one or more parity checks of the error correction code, LLR > 0 indicates that the bit is more likely to be 0 instead of 1, and LLR < 0 indicates that the bit is more likely to be 1 instead of 0. In addition, a larger magnitude indicates a greater probability or reliability. Therefore, a bit having LLR = 20 is more likely to be 0 than a bit having LLR = 10, and a bit having LLR = -20 is more likely to be 1 than a bit having LLR = -10. LLR=0 indicates that the bit may also be 0 or 1.

The LLR table 406 can be provided for each of the four bit positions in the codeword Y1 such that the LLRs can be assigned to each of the bits 1, 0, 1, and 1 of y1, respectively. In addition, the LLR table can illustrate multiple read results such that LLRs with larger magnitudes are utilized when bit values are consistent across different codewords. Therefore, an LLR having a larger magnitude can be assigned to the first bit in y1 than in the case where only one read operation is performed. To illustrate, the first bit in y2 is 1, which is consistent with the first bit in y1. Similarly, LLRs with smaller magnitudes are utilized when bit values are inconsistent in different codewords. For example, the fourth bit in y2 is 0, which is inconsistent with the fourth bit in y1. Therefore, an LLR having a smaller magnitude can be assigned to a fourth bit in y1 as compared to a case where only one read operation is performed. Since more information is obtained from the extra read operation, the decoding process can be improved, for example, such that it converges faster or converges in situations where it may otherwise not converge with only one read operation. In another approach, the second read operation or other additional read operation is not performed unless the decoding process, for example, does not successfully converge within a given amount of time or a given number of iterations.

The decoder 408 receives the codeword y1 and the initial LLR. As explained further below (see also Figures 12 and 13), decoder 408 iterates in successive iterations, where it determines if the parity check of the error coding process has been met. If all co-location checks are initially satisfied, the decoding process has converged and the codewords have not been mistaken. If one or more parity checks have not been met, the decoder will perform error correction by adjusting the LLR of one or more of the bits that are inconsistent with the parity check, and then reapply the parity check to determine if it has been satisfied. . Lift For example, the magnitude and/or polarity of the LLR can be adjusted. If the co-location check is still not met, the LLR can be adjusted again in another iteration. Adjusting the LLR can cause the bit to be flipped in some, but not all, conditions (eg, from 0 to 1 or from 1 to 0). Once the co-location check has been satisfied, the next parity test is applied to the codeword if applicable. The process continues to attempt to satisfy all co-location checks. Therefore, the decoding process of y1 is completed to obtain decoded information and parity bits v and decoded information bits i.

Note that in the example discussed, the codeword y1 from the first read operation is decoded with assistance from one or more subsequent read operations. However, other methods are possible. For example, a codeword from a given read operation can be decoded with assistance from one or more previous read operations. Alternatively, three read operations can be taken that determine two consistent results (eg, both read state Y1) and an inconsistent result (eg, state Y2), and can be decoded with assistance from inconsistent results. The code word for the consistent result. The LLR table can be set accordingly.

In another option, the codeword for the consistent result is directly decoded without assistance from the inconsistent result.

Thus the examples discussed include performing two or more reads to mitigate noise effects, and combining the results of such reads to modify the number of LLRs for each storage element. Another read operation can be performed when the iterative process of the ECC decoder takes too much time to reach convergence. When an additional read is performed, the decoding may continue or may be suspended. Or, additional readings can be performed automatically regardless of the progress of the decoding. After the second read operation is completed, the LLR flag amount from the first read operation may be updated based on the second read operation value. In one method, LLR values can be added or otherwise combined from different read operations. For example, a noise storage element having an LLR value of 10 and -10 is considered for the positioning element of the first read operation and the second read operation. This table receives the read status as an input and outputs an LLR value indicating the read status for each bit in the codeword. After obtaining these two contradictory results, an LLR of, for example, 0 can be used for decoding. The decoding engine sets this bit high or low to achieve convergence.

It is also possible to perform more than two read operations. One method adds or takes an average or average from all read LLR results. For example, the LLR values may be 20, 10, and -10 for the first, second, and third read operations, respectively, in which case the average is 6.6. This is a simplified method of convenience. Other methods may consider the fact that the LLR of 20 indicates more than twice the probability of a given result compared to an LLR of 10, such that LLRs of, for example, 10 and 20 are combined closer to 10 20 LLR.

Another method constructs the LLR values based on the probability density functions f1(u│X) and f2(v), as further described below.

Also, as the results of the second read operation have become available, the iterative process may have advanced and many LLR values may have been updated to attempt to converge. The result of the second reading may thus be combined with the currently available first iterative result of the first reading or with the original result of the first reading, or a hybrid method may be utilized.

Additionally, if each of the read operations produces the same result, then for a given location, we can assign a higher magnitude LLR to the bit. This peak LLR (LLRpeak) may be slightly higher than the LLR that can be obtained from a single read (LLRsingle). If the reading series gets different results, it can produce lower and most Final LLR. One of the methods of the aggregated read series is to take a single read LLR average and multiply it by a normalization factor (such as LLRpeak/LLRsingle) so that the final LLR = multi-read averaged LLR × │ LLRpeak / LLRsingle .

In a practical embodiment, the iteration for convergence based on the first read result may begin before the second read result is obtained. Once the second read result and (generally) all subsequent read results are obtained, one of the strategies used to incorporate subsequent read results into the iterative process assumes that all raw results read from the storage element are still available . In this case, we can simply interrupt the current iteration and start again with the final LLR as calculated above. Another strategy for aggregating LLR values is to combine the re-acquired read results with the current iterative LLR values. This can be done, for example, by weighting the nth read result with 1/(n-1) relative to the previous result such that all read results are equally weighted.

It can be determined by how good the current iteration is to determine which strategy is more appropriate.

The "goodness" of the iterations can be measured by a quality measure, such as whether the iterative decoding process approaches convergence for a given time period and/or a given number of iterations, and/or a certain number of parity checks have been met. In addition, metering can be used for immediate adaptive decision making during decoding, for example, by selecting to continue the current decoding process without performing additional reads, continuing to decode when the recently utilized LLR is adjusted based on additional reads, or The decoding is resumed with the new initial LLR based on the extra read.

The LLR or other probabilistic measure can be developed, for example, by obtaining a probability density function of the programmed state of the non-volatile storage element set, as follows.

Figure 5a is a flow diagram of a process for obtaining a first probability density function f1 for a non-volatile storage element set. Step 500 includes staging the random data to all of the storage elements in the set of M storage elements. That is, assuming that the storage element is a multi-level storage element having n stages or stylized states, after programming, about M/n of the storage elements are programmed to the first state, and M/n are stylized. To the second state, and so on. For example, in one possible approach, n = 16 states, each of which is represented by a four-bit codeword. At step 502, the index k representing the kth stylized state is initialized to zero. Step 506 includes performing N repeated measurements of the _VTH for each of the storage elements that are written to state k, where N is a large number such as 100.

These are measurements made in the test environment at a higher accuracy compared to the accuracy utilized during production utilization of the storage device.

Step 508 includes obtaining a noise free _VTH for each storage element by averaging N measurements for each storage element. The no-noise _VTH refers to a threshold voltage that is essentially free of noise that is specifically incurred during a read operation. This results in approximately M/n non-noise _VTH values on the set of storage elements. For example, Figure 6a depicts the distribution of voltage threshold readings. For, for example, state 0, histogram 600 shows the number of readings that fall into different ranges or buckets of the _VTH for the first storage element of the example. The histogram 602 is for state 1 for the example second storage element and the histogram 604 is for state 15 for the example third storage element. A histogram for the intermediate state is not depicted. Figure 6b depicts the noise-free threshold reading. For example, V _TH-NF0 , V _TH-NF1 , ..., V _TH-NF15 represent the noise-free voltages of states 0, 1, ..., 15 for the first, second, and third storage elements, respectively. Limit reading. Note that the original _VTH reading can also be averaged instead of using the histogram of Figure 6a. In addition, statistical techniques other than averaging can be utilized.

Step 510 (Fig. 5a) includes constructing a histogram of the distribution of all memory elements programmed into the set of non-noise _VTHs across the set to state k using the noise-free _VTH from each of the storage elements. For example, Figure 6c depicts the distribution of no noise voltage threshold readings (eg, readings without reading noise). There may still be other noise. For, for example, state 0 for the example first storage element, histogram 650 shows the number of readings that fall into different ranges or buckets of the _VTH . The histogram 652 is for state 1 for the example second storage element, and the histogram 654 is for state 15 for the example third storage element. A histogram for the intermediate state is not depicted. These histogram storage elements M indicating the number of units within the specified range has a bar graph of V _TH. Step 512 includes normalizing and curve fitting the histogram to obtain f1 (u│X=state k), which is a probability density function indicating that the storage element will have a probability of _VTH =u when the storage element is programmed to state k. (pdf). For example, in the case of k=0, the function f1(u│X=0) is in the case where we randomly select a storage element from the memory chip (where the storage element has been programmed (written) to the state) 0) Its noise-free V _TH will be the probability of u. Normalizing the histogram (eg, one of the histograms 650, 650, ... 654) may include dividing the height of the bar graph by M such that the sum of the heights of each of the bars for a given state is one.

At step 514, the result is stored, for example, including data defining a function f1 (u│X = state k). If the next state is to be analyzed at decision step 516, the state index is incremented at step 504 and the process is again at steps 506-514. get on. This process is repeated for all memory states. The process ends at step 518, at which point pdf f1(u│X=0), f1(u│X=1), f1(u│X=2), f1(u∣X=3), ...f1(u│X=n), where n+1 is the number of states. Figure 6d depicts the probability distribution of voltage thresholds for different states of a non-volatile storage element set. Here, an instance distribution 660 for f1 (u│X=0), an instance distribution 662 for f1 (u│X=0), and an instance distribution 664 for f1(u│X=15) are depicted, where 16 states. The distribution for the intermediate state is not depicted.

Figure 5b is a flow diagram of a process for obtaining a second probability density function f2 for a non-volatile storage element set. Steps 520, 522, and 526 correspond to steps 500, 502, and 506 of Figure 5a. Alternatively, the steps may be repeated with respect to the corresponding steps of Figure 5a, or the results from steps 500, 502, and 506 of Figure 5a may be used to begin at step 528 of Figure 5b. Step 528 includes subtracting the noise-free _VTH from each measurement to obtain a shifted measurement. For example, Figure 7a depicts a histogram of such shifted measurements or deviations from a no-noise _VTH . Step 530 includes constructing a histogram that shifts the distribution across all of the storage elements programmed to state k. Figure 7b depicts an example of this histogram. Step 532 includes normalization and curve fitting function to obtain a histogram f2 (v), which is indicative of the time k to the state storage element having the read noiseless deviation v of V _TH V _TH of the storage element via stylized The probability of pdf. Function f2 (v) is obtained with the V _TH is "true" or "noiseless" V _TH at a distance "v" at the probability I randomly selected from the storage element of memory chips and for the case where a single measurement. Figures 7c to 7e depict examples of f2(v) for different states. In particular, Figure 7c depicts the probability distribution for the voltage threshold deviation for state 0, Figure 7d depicts the probability distribution for the voltage threshold deviation for state 1, and Figure 7e depicts the voltage threshold for state 15 The probability distribution of the value deviation. Note that these figures indicate that the distributions may be slightly different. The distribution of f1 can be similarly different.

At step 534, the result is stored, for example, including information defining the function f2(v). If the next state is to be analyzed at decision step 536, the state index is incremented at step 524 and processing proceeds again at steps 526-534. This process is repeated for all memory states. The process ends at step 538, at which point pdf f2(v) for all states has been obtained.

Note that pdf can vary with the lifetime/cycle of the memory device when the noise-free _VTH distribution can be changed. Measurements of _{VTH that} can be used to obtain pdf can be performed and averaged over different device lifetimes, for example, to obtain pdf and resulting LLR (which represents average device life).

8 is a flow diagram of a process for obtaining a logarithmic power ratio (LLR) for decoding read data from a non-volatile storage element. At step 800, based on f1(u) and f2(v), we calculate the conditional probability P(Y ₁ , Y ₂ │X). This is the probability that in the case where a state X is given when writing to the storage element, the first reading yields Y ₁ , the second reading yields Y ₂ , and so on. This probability can be expressed in the form P(Y ₁ , Y ₂ │X) when there are two read operations, or in the form P (Y ₁ , Y ₂ ,..., Y _N when there are N read operations). │X) to express. The probability can be determined for measurement in the test environment. At step 810, based on such odds and Bayes rules, we calculate P(X│Y1, Y2) when there are two read operations, or generally P when there are N read operations ( X│Y1, Y2, Y3, Y4...Y _N ). P(X│Y1, Y2) is a probability that, given the first reading result Y1 and the second reading result Y2, the stylized state is X. Step 820 includes calculating the LLR for each bit given all of the possible y values for the N reads, and step 830 includes storing the results in, for example, one or more tables. That is, the LLR is assigned to each bit in each codeword used to represent the programmed state. During operation of the memory device, the provided table can be used to find the initial number of LLRs for decoding in the case of a given multiple read operation in a possible method.

Note that the technique outlined here assumes the independence between reading noise and "no noise" _VTH . The technology can be extended to cover situations where the read noise value is not independent of the "no noise" _VTH . This essentially involves constructing the joint pdf f(u, v ₁ , v ₂ , ... v _n ) from the experimental data.

Figure 9a depicts a table providing multi-bit codewords for different programmed states of non-volatile storage elements. As mentioned previously, each stylized state of the storage element can be represented by a codeword. For example, in the case of 16 states, a four-bit codeword can be utilized. In addition, the LLR or other reliability measure is associated with each bit of the probability that the bit is not mistaken (the higher magnitude LLR indicates a higher probability that the bit was not mistaken). Figure 9a depicts the bit value or codeword in a row below the stylized states 0-15. The bit positions are depicted as top, upper, upper, and lower. The lower part element is the most significant bit and the top bit is the least significant bit. Therefore, the codeword for state 0 is 1111, the codeword for state 1 is 1110, and so on. As indicated in Figure 9b, the LLR is associated with each bit.

Figure 9b depicts each bit of the codeword based on the first read result A table for the initial values of LLRs. LLR is represented by values M1, M2, and M3, where M1 < M2 < M3. As mentioned previously, a positive LLR indicates 0 bits, a negative LLR indicates 1 bit, and a larger magnitude indicates a greater reliability or correctness probability. For example, for a location element below state 0 to 5, LLR = -M3, which indicates that these bits have a high probability of being one. This can be seen visually because the probability of reading state Y1 being far away from the stylized state (eg, several states are far) is small. Therefore, the LLR used for the location element below state 5 is -M3 (higher probability of correctness) because the read state may have to be self-programmed (eg, state 8 (where the lower part is 0 instead of 1) )) Leave three states. However, the LLR used for the location element below state 6 is -M2 (intermediate correctness probability) because the read state may have to leave both states for the bit to be missed. Similarly, the LLR for the location element below state 7 is -M1 (lower probability of correctness) because the read state may have to leave only one state for the bit to be misplaced. Similar reasoning applies to other bit positions. For example, the LLR for the top bit indicates a relatively low probability of correctness, since only one state error may result in the bit being incorrect.

Figure 9c depicts a table providing adjustments to the current value of the LLR utilized by the decoder for each bit of the codeword based on the second read result. The LLR value can be adjusted when performing a second or other additional read operation. In a possible method, after the first read result has been decoded, the LLR value currently utilized by the decoder is adjusted. As explained further in connection with, for example, Figures 12 and 13, the iterative probability decoding involves applying a parity check of the error correction code to the read codeword. If the parity check fails, the decoder adjusts the LLR value in the direction that satisfies the parity check. This can be repeated in successive iterations Cheng. Sometimes, the adjustment ends when the incorrect bit is flipped and the parity check is satisfied. In this case, the next parity check is performed if applicable. Therefore, the current (most recently utilized) value of the LLR can be adjusted while decoding is in progress.

Generally, if the second read value coincides with the first read value, based on each bit, the current LLR may be added in terms of magnitude to indicate that the bit has greater reliability. For example, if the first read is Y1=state 7 (codeword 1011) and the second read is Y2=state 6 (codeword 1010), the LLR can be adjusted for the top bit to indicate that the bit is 1 A greater chance. Note that based on the first read (Fig. 9b), the initial LLR for the bit is -M1, but the decoding process may have changed this value to another negative or even positive value. In this embodiment, the adjustment is applied to the current value. For example, the LLR can currently be -M2, in which case it may be adjusted to a negative value greater than M2 in magnitude. Or, the LLR can currently be +4, in which case it may be adjusted to +1.

Note that the adjustment can be expressed in different ways, for example, by adding or subtracting a constant, or by a function. No need to use the table. For example, the adjustment can be made based on the magnitude of the LLR. It may not be necessary to use a higher magnitude to adjust the LLR, or a relatively small adjustment can be made under this condition. Conversely, a relatively large adjustment can be made when the LLR has a small magnitude. In general, the adjustment can be based on factors such as how close the decoding process is to convergence (eg, based on the number of iterations and/or the number of parity checks satisfied), the current value of the LLR, and/or the second Or other extra read status. Different adjustment tests can also be performed to determine a satisfactory adjustment. The specified adjustments utilized may be adapted to a particular memory device embodiment.

Figures 10a through 10d depict a table that provides an initial value of LLR for each bit of a codeword based on the first read result and the second read result. In one method, the initial value of the LLR used in the decoding process can be set based on the result of the multiple read operation. A separate table can be provided for each bit position of the codeword. For example, FIGS. 10a, 10b, 10c, and 10d provide LLR values for the top bit, the upper bit, the upper part, and the lower part, respectively. For example, each table can be read based on two read results Y1 and Y2. After reading each table, the initial LLR for each bit is provided to the decoding process. Note that the table can have three or more dimensions with three or more read operations.

Figure 11a is a flow diagram of a process for decoding a codeword representing the state of a non-volatile storage element, wherein an initial probability meter is obtained based on a first read operation and a second read operation. Step 1100 includes initiating a first read operation. The reading operation can include sensing whether the _VTH of the storage element is above or below a plurality of comparison points (step 1102). Some of the comparison points may result in a hard bit, for example, a comparison point for separating the _VTH range of the stylized state, and some of the comparison points may result in a soft bit, for example, The comparison point of the V _TH range of the stylized state. In one method, the read operation may utilize a first set of comparison points, followed by a second set of comparison points that bisect the first set.

Each comparison point decision can be considered a sensing operation, which can be a read operation in general. In practice, many storage elements can be read during a read operation. For example, an error correction code can be applied over a number of storage elements, in which case the read results are obtained from the storage elements for use in decoding. Based on the sensing, the stylized state of the storage element is determined (step 1104) and the codeword is assigned based on the stylized state (step 1106). For example, the codeword or bit assignment of Figure 9a can be utilized in the presence of 16 states. A second read operation is initiated at step 1108, such as by again sensing whether the _VTH of the storage element is above or below the comparison point (step 1110). Based on the sensing, the stylized state of the storage element is again determined (step 1112).

Step 1114 includes assigning an initial probability measure to each bit in the codeword, wherein the metering indicates the reliability of the bit based on the first read result and the second read result. For example, this step may involve reading the tables of Figures 10a through 10d to obtain LLRs, but may also utilize other probabilistic measurements. Step 1116 includes performing iterative decoding using the initial probability metering and adjusting the probability metering in successive iterations. After the iteration of step 1116, if the decoding converges at decision step 1118 (eg, all co-located checks satisfying the error correction code), the decoded codeword is stored as the final read result (step 1120).

Note that the codeword associated with the error correction process can be decoded while the parity check extends over the codeword. Alternatively, it is possible for a single codeword to be decoded by itself when one or more parity checks involve only one codeword. If the decoding does not converge, then an error is declared, for example, at step 1122 or an additional read operation can be performed.

Figure 11b is a flow diagram of a process for decoding a codeword representing a state of a non-volatile storage element, wherein an initial probability meter is obtained based on a first read operation, and then further adjusted based on the second read operation It is measured by the probability of adjustment. As discussed, in an embodiment, the decoding process may be temporarily suspended such that the current LLR value adjusted relative to the initial LLR value is further adjusted based on one or more additional read results. Step 1130, 1132, 1134, and 1136 correspond to steps 1100, 1102, 1104, and 1106 of Figure 11a, respectively. Step 1138 includes assigning an initial probability measure to each bit in the codeword, wherein the metering indicates the reliability of the bit based on the first read result. For example, this step may involve reading the table of Figure 9b to obtain an LLR, but may also utilize other probabilistic measures. Step 1140 includes performing iterative decoding with initial probability metering and adjusting the probability metering in successive iterations. If the decoding converges at decision step 1142 for a given time period (e.g., elapsed time) and/or a given number of iterations, the decoded codeword is stored as the final read result (step 1144). If the decoding progresses toward convergence, such as by satisfying a specified number of parity checks, the decoding continues. Appropriate software, hardware and/or firmware may be provided in the decoder to enhance this supply.

If the decoding does not converge or the convergence progresses, the decoding is adjusted. The current value of the probability meter is stored at step 1146 and the second read operation begins at step 1148. Steps 1150 and 1152 correspond to steps 1132 and 1134, respectively. Step 1154 includes adjusting the current value of the probability meter based on the second reading. For example, this can include applying an LLR adjustment as depicted by the table of Figure 9c. At step 1156, the iterative decoding continues with the adjusted value of the probability measure that can be further adjusted in subsequent iterations. The decoding process is improved due to the information provided by the second reading. For example, the decoding process may converge faster than if only the result from a single read is used, or the decoding process may converge if the single read condition may not converge. At decision step 1158, the decoding status is checked again, similar to the check of decision step 1142. If the decoding converges within a given time period (eg, elapsed time) and/or a given number of iterations at step 1158, it will be decoded The codeword is stored as the final read result (step 1160). Note that the metering used to converge toward convergence in step 1158 may be less stringent than at step 1142. If the decoding progresses toward convergence, such as by satisfying a specified number of parity checks, the decoding continues. If the decoding does not satisfy the second condition, an error may be declared or an additional read operation may be performed (step 1162), and the result of the read operation is used to adjust the decoding process again.

Note that instead of starting an additional read operation in response to the decoding not satisfying certain conditions, it is possible to automatically perform an additional read operation after the decoding process has started on the basis of the first read operation. In this case, the decoding process may be suspended to update the LLR when the second read operation has completed, regardless of whether the decoding satisfies certain conditions or, if necessary, the result of the second operation may be stored for use in the decoding process. Subsequent use.

Figure 11c is a flow diagram of a process for decoding a codeword representing a state of a non-volatile storage element, wherein an initial probability meter is obtained based on a first read operation, followed by a first read operation and a second read Based on the operation to obtain a new initial probability measurement. In this method, decoding essentially restarts from the beginning based on the initial LLR obtained from the first read when it does not satisfy the particular condition. However, the new initial LLR is based on a first read operation and a second read operation or other additional read operation. Steps 1170, 1172, 1174, 1176, 1178, 1180, 1182, and 1184 correspond to steps 1130, 1132, 1134, 1136, 1138, 1140, 1142, and 1144 of FIG. 11b, respectively. At step 1186, when the decoding does not satisfy the first condition at decision step 1182, an error may be declared or an additional read may be performed. If the second read operation is to be utilized (step 1188), then at step 1190, the decoding is aborted. The current value of the probability measure (eg, LLR) utilized by the device. Steps 1192 and 1194 correspond to steps 1150 and 1152 of Figure 11b, respectively. At step 1196, a new initial probability meter is assigned to each of the codewords (eg, the codeword assigned in step 1176). These new probabilities are based on the first and second read operations to indicate the reliability of the bit.

Figure 12 depicts a sparse parity check matrix. As mentioned previously, the storage element stores data representing the information bits and the parity bits, wherein the parity bits are provided in accordance with the error correction encoding process. This process involves adding a parity bit to the information bit. In one possible approach, a low density parity check (LDPC) code is utilized. In practice, these codes are typically applied to multiple codewords that are encoded across a number of storage elements. The LDPC code is required because it incurs a relatively low additional item cost. In addition, the LDPC code exhibits an approach to the Shannon limit under an iterative message passing decoding algorithm. However, this is merely an example embodiment as any type of error correction code can be utilized. For example, other linear block codes can be utilized.

The LDPC code is a linear block code characterized by a sparse parity check matrix, for example as depicted by matrix H 1200. The matrix includes K information bits and M co-located bits, and the code length is N=K+M. Additionally, the parity bits are defined such that M parity check equations are satisfied, where each column of the matrix represents a parity check equation. In particular, the matrix is identified by checking nodes cn1 through cn10 and the line is identified by variables v1 through v13, which indicate the data (eg, codeword bits) stored in the storage element. This information includes the information bit i and the parity bit p, based on the following equation: , where H is a sparse parity check matrix, For the data matrix, It is an information bit matrix, and p is a parity matrix. In one method, information bits can be taken from different bit positions of different codewords. The data matrix v can be determined by solving the above equation. In addition, if the matrix H is a lower triangle, this can be efficiently performed using a Gaussian elimination program.

Figure 13 depicts a sparse diffractogram corresponding to the sparse parity check matrix of Figure 12. Diagram 1300 indicates in more detail how the LDPC code works. The variable nodes v1 to v13 represent codeword bits, and the check nodes cn1 to cn10 represent co-located check constraints on the bit.

During decoding, the decoder attempts to satisfy the parity check. In this example, there are ten parity checks as indicated by check nodes cn1 through cn10. The first parity test at cn1 determines whether v2 V4 V11 V13=0, where Represents a mutually exclusive or (XOR) logical operation. This check is satisfied in the case where an even number of "1" bits exist in v2, v4, v11, and v13. This check is represented by the fact that the arrows from nodes v2, v4, v11, and v13 point to node cn1 in graph 1300. The second parity check at cn2 determines whether v1 V7 V12=0, which is satisfied if there is an odd number of "1" bits. The third parity check at cn3 determines whether v3 V5 V6 V9 V10=0, which is satisfied if there is an odd number of "1" bits. Similarly, the fourth parity check at cn4 determines whether v2 V8 V11=0, the fifth parity check at cn5 determines whether v4 V7 V12=0, the sixth parity check at cn6 determines whether v1 V5 V6 V9=0, the seventh parity check at cn7 determines whether v2 V8 V10 V13=0, the eighth parity check at cn8 determines whether v4 V7 V11 V12=0, the ninth parity check at cn9 determines whether v1 V3 V5 V13=0, and the tenth parity check at cn10 determines whether v7 V8 V9 V10=0.

The decoding process for LDPC is an iterative probability decoding process called iterative message passing decoding. Iteration involves continuously traversing the check node and updating the LLR values of the bits involved based on each parity check. In one method, an attempt is made to satisfy the first parity check of cn1. Once the peer check is satisfied, an attempt is made to satisfy the first parity check of cn2, and so on. If necessary, the LLR values are adjusted for each iteration in a manner known to those skilled in the art. This iterative algorithm is in the form of belief propagation.

Use of pre-adjusted waveforms

The sensed stylized state of the storage element can be varied within different read operations based on the history of the stored component. For example, the state of the storage element will sometimes change between two read operations, and the number of storage elements that change state can depend on the history of the control gate voltage. The tendency for the read state to change is based on a number of factors, including the _VTH width for each state, the spacing between states, the interception site noise, and other factors.

Therefore, it may be useful to intentionally generate different short-term histories when performing two or more sensing operations. In one approach, different short-term histories are utilized at the same voltage level or at adjacent voltage levels. For example, the selected word line can be grounded just prior to the first read operation. In order to make the short-term history of the second read operation different, we can, for example, read the read pass voltage (eg, V _READ = 5.5 V) just before the start of the second read operation. The pre-regulated waveform is applied to the selected word line. V _READ is the voltage that is typically applied to an unselected word line when the storage element on the selected word line is read. However, this is one of many possible embodiments. For example, in addition to the time interval between the end of the pre-adjusted waveform and the beginning of the sensing integration time, the amplitude, duration, and shape are all operative, for example, using the RC time constant of the word line and other lines of interest. Optimized parameters.

Some noise on the storage element of V _TH is applied to depending on its various terminals (such as CP and the control gate well) and short-term history of bias voltage set, the short term history of different noise behavior there should be increased, and this increase Will help us identify more suspicious bits. This additional information should improve the iterative decoding process by identifying the noise storage element and confirming the uncertainty about the value of a particular bit. This ignorance confirmation can be used to help focus the decoding process on more troublesome bits that require more attention. In short, the better system knows that we don't know the value of some bits rather than pretending to be known.

The utilization of the pre-conditioning waveform prior to the sensing operation allows the history of the read operation to be more closely similar to the verify operation performed during the stylization because the short-term history of the verify operation includes the program (V _PGM ) pulse. An example V _PGM pulse whose amplitude varies between, for example, 13-20 V is depicted in FIG. The amplitude of the pre-conditioned waveform need not be as high as the amplitude of the program pulse, but it can still repeat the short-term history that the storage element is subjected to when the verification operation is performed as part of the stylized operation. Thus, the effect of the program pulse on the storage element prior to the verify operation is partially replicated by the effect of the pre-conditioning pulse on the storage element prior to the read operation. For embodiments in which an additional read operation is only performed when necessary (eg, when the decoding process based on a read operation does not converge), in a possible approach, the first read may be in a sensing operation Previously used pre-adjusted waveforms.

Additionally, probability measurements (such as LLR) used in the decoding process can account for the effects of the pre-conditioned waveform. Thus, the initial LLR assigned to a bit can vary based on the history of the associated storage element. For example, if the same bit value in the codeword is obtained from a read operation with and without a pre-adjusted waveform, the magnitude and bit value of the LLR for the bit are independent of the pre-adjusted waveform or Even the case where the read operation with the pre-adjusted waveform is obtained is higher to indicate a more confident measurement of the value of the bit.

In particular, the pre-conditioning waveform can affect the probability distribution function (pdf) of various stylized states. This effect is measurable by comparing the pdf of the _VTH distribution with and without the pre-adjusted waveform of the set of storage elements. In general, mathematical methods for multiplying aggregated LLR results are provided on the basis of the behavior of storage elements that can be used for a particular technique, using pre-conditioned waveforms. For example, if each of the reads yields the same result, then we can assign a high value LLR representing the state for the bits of the codeword. This peak LLR (LLRpeak) may be higher than the LLR for single read only (LLRsingle). On the other hand, if the reading series yields different results, a lower final LLR may result. One of the methods of the aggregated read series is to take the average of the single read LLR and then multiply the average by a normalization factor (such as LLRpeak/LLRsingle).

The examples below depict one or more pre-conditioning pulses that occur prior to the sensing operation of the read operation, but in general, any pre-conditioned waveform can be utilized. Additionally, a pre-conditioning waveform can be applied to the terminals of the storage element (eg, control gates, sources, and/or drains), and/or to the substrate on which the storage elements are formed. For example, the first pre-conditioning waveform can be applied to the non-volatile storage element via the body of the substrate on which the non-volatile storage element is formed, and the second pre-conditioning waveform can be applied to the control gate, source of the storage element. Extreme and bungee jumping. Alternatively, a second pre-conditioning waveform can be applied to the non-volatile storage element via the body and a first pre-conditioning waveform can be applied to the control gate, source and/or drain of the storage element. Additionally, pre-conditioned waveforms having different characteristics can be applied during a read operation or during different read operations.

In addition, the pre-conditioning waveform can be used in single read methods as well as in multiple read methods. Additionally, the pre-conditioned waveform can be utilized with any type of error correction decoding or without error correction decoding.

Figure 14a is a timing diagram illustrating the behavior of a particular waveform during a read/verify operation, where a pre-conditioned waveform is applied to a selected word line prior to correlating the read pulses. Waveforms in this and other timing diagrams are not necessarily to scale.

As mentioned, a pre-conditioning waveform can be applied to the storage element as part of a read operation. This may involve, for example, applying a pre-conditioned waveform (such as a pulse) to the read storage via the associated selected word line prior to applying the sense voltage to the word line for comparing the _{VTH of the} storage element with the comparison point. The control gate of the component. In addition, the pre-conditioned waveform can be applied just prior to any reading or just prior to some of the read operations. It can be combined with soft reading at various levels. It can also be combined with multiple reads at the same voltage level.

In general, during a read and verify operation, a selected word line or other control line is connected to a voltage whose level is specified for each read and verify operation to determine if the threshold voltage of the associated storage element has Reach this level. After the word line voltage is applied, the conduction current of the storage element is measured to determine if the storage element is on. If the conduction current is measured to be greater than a particular value, then the storage element is turned on and the voltage applied to the word line is greater than the threshold voltage of the storage element. If the conduction current is not measured to be greater than a particular value, then the storage element is not turned on and the voltage applied to the word line is not greater than the threshold voltage of the storage element.

There are many ways to measure the conduction current of a storage element during a read or verify operation. In one example, the conduction current of the storage element is measured by the rate at which it allows (or fails to allow) the NAND string including the storage element to discharge the bit line. The charge on the bit line is measured after a period of time to see if it has been discharged. In another embodiment, conduction of the selected storage element allows current to flow or not flow on the bit line, which is measured by whether the capacitor in the sense amplifier is charged due to current flow. Discuss two examples.

In particular, waveform 1400 depicts the drain side select gate voltage (SGD), waveform 1402 depicts the unselected word line voltage, and waveform 1404 depicts (to read/verify the selected word line) the selected word line voltage, waveform 1410 Depicting the source side select gate (SGS) voltage (option 1), waveform 1412 depicting the SGS voltage (option 2), and waveform 1414 depicting (for reading/verifying the selected bit line) the selected bit line (BL) Voltage (option 1), waveform 1418 depicts the selected BL voltage (option 2), and waveform 1419 depicts the source voltage. In addition, the time point t0-t4 is at the level Expand in the direction.

Note that there are two versions of the depicted SGS and the selected BL. Option 1 depicts a read/verify operation for a storage element array for measuring the conduction current of the storage element by determining whether the bit line has been discharged. Option 2 depicts a read/verify operation of the array of storage elements for measuring the conduction current of the storage element by the rate at which the storage element discharges the dedicated capacitor in the sense amplifier.

First, the behavior of the sensing circuit and the array of storage elements involved in measuring the conduction current of the storage element by determining whether the bit line has been discharged will be discussed with respect to Option 1.

Prior to t0, the voltage begins at a steady state voltage Vss of approximately 0 V.

Between t0 and t1, a pre-conditioning waveform 1406 is applied to the selected word line prior to reading pulse 1408. Note that in another method, the pre-conditioning waveform may overlap with the sensing operation (read pulse 1408). At t2, SGD and SGS (option 2) rise to V _SGD and V _SGS (for example, 3.5 V), respectively. The unselected word line rises to V _READ (eg, 6 V), which acts as an overdrive voltage because the unselected storage element is turned on and acts as a pass gate. The pre-conditioning waveform 1406 can have an amplitude that is comparable to, for example, V _{READ that} is greater than V _CGR . V _READ is typically the highest voltage that can be applied without causing interference. The selected word line rises to V _CGR (control gate read voltage) for a read operation or rises to a verify level for a verify operation. The waveform on the selected word line between t2 and t4 is taken as the read pulse 1408 utilized during the sensing operation. In one method, the selected BL (option 1) is precharged to approximately 0.7V.

The process depicted in Figure 14a can then be repeated at the next read or verify level, where a different V _CGR is applied to sense whether the _VTH of the storage element associated with the selected word line is above or below the corresponding comparison point. In one method, a pre-conditioning pulse is provided prior to each sensing operation.

At t3, the NAND string can control the bit line. Also at t3, the source side select gate is turned on by raising SGS (option 1) to V _SGS . This provides a path to dissipate the charge on the bit line. If the _VTH for reading the selected storage element is greater than V _CGR or the verify level applied to the selected word line, the selected storage element will not turn on and the bit line will not discharge, as depicted by line 1415. If the threshold voltage for reading the selected storage element is below V _CGR or below the verify level applied to the selected word line, then the selected storage element will be turned on (conducted) and the bit line voltage will be read. Dissipation, as depicted by curve 1416. At some point after time t3 and before time t4 (as determined by the particular embodiment), the sense amplifier will determine if the bit line has been dissipated a sufficient amount. Between t3 and t4, the sense amplifier measures the evaluated BL voltage. At time t4, the depicted waveform will be reduced to Vss (or another value for inactivity or recovery).

Following the behavior of the sensing circuit and the array of storage elements discussed with respect to option 2, the conduction current of the storage element is measured by the rate at which the storage element discharges the dedicated capacitor in the sense amplifier. As previously mentioned, a pre-conditioning waveform 1406 is applied between t0 and t1. At time t2, SGD rises to V _SGD , the unselected word line rises to V _READ , and the selected word line rises to V _CGR for a read operation or rises to a verify level for a verify operation.

In this case, the sense amplifier keeps the bit line voltage constant regardless of what activity the NAND string is performing, so the sense amplifier uses the "clamp" to the bit line of the voltage to measure the current flow. After t2 and before t4 At some point (as determined by the particular embodiment), the sense amplifier will determine if the capacitor in the sense amplifier has dissipated a sufficient amount. At t4, the depicted waveform will be reduced to Vss (or another value for inactivity or recovery). Note that in other embodiments, the timing of some of the waveforms can be changed.

Figure 14b is a timing diagram illustrating the behavior of a particular waveform during a read/verify operation, wherein one or more pre-conditioned waveforms are applied to the selected word line prior to correlating the read pulses. Here, three sensing operations that form part of a read operation are depicted. For example, in the case of 16 states, there may be 15 sensing operations. Waveforms 1420, 1422, 1424, 1435, 1436, 1437, 1438, and 1439 represent waveforms 1400, 1402, 1104, 1410, 1412, 1414, 1418, and 1419 of Figure 14a, respectively, within three sensing operations. Waveform 1432 is similar to waveform 1424, but includes pre-conditioned waveform 1426 only prior to the first read pulse 1427 in the series of read pulses that make up the read operation. In waveform 1424, pre-conditioning waveforms 1426, 1428, and 1430 are applied to the selected word line prior to read pulses 1427, 1429, and 1431 associated with different _VTH comparison points, respectively. The read pulse amplitude is increased in each sensing operation, for example, from V _CGR-1 to V _CGR-2 to V _CGR-3 , and so on. The amplitude of the pre-adjusted waveform may be the same for each sensing operation or may vary, for example, with the amplitude of the associated read pulse. Regarding waveform 1432, it is noted that in general, the pre-conditioned waveform can be provided prior to one or more selected read pulses in the read operation. Additionally, read pulses with associated pre-conditioned waveforms can be randomly selected.

Figure 14c is a timing diagram depicting different pre-conditioning waveforms. As mentioned, the pre-conditioned waveform can have a variety of features. Waveform 1404 (also discussed in Figure 14a) includes a baseline pre-conditioning waveform 1406 as provided prior to reading pulse 1408 pulse. Note that waveform 1406 and pulse 1408 show the rise time and decay time that will vary for different memory devices. In an option, waveform 1440 includes pre-adjusted waveform 1441 as a pulse having a longer duration than pulse 1406. Waveform 1442 includes a pre-conditioned waveform 1443 that is closer to read pulse 1408 than pulse 1406. The time period in the debate extends from the end of the pre-conditioned waveform to the beginning of the read pulse. Waveform 1444 includes pre-conditioned waveform 1445 as a pulse having a lower amplitude than pulse 1406. Waveform 1446 includes a pre-conditioned waveform 1447 having a different shape than pulse 1406. Here, an oscillating waveform is utilized. Although this waveform does not replicate stylized pulses and even includes negative voltages, it can still be used, for example, to cause interception site activity. Other waveforms including ramps, steps, and the like can also be utilized. It is also possible to provide multiple pre-conditioned waveforms before reading the pulses.

Figure 14d is a timing diagram illustrating the behavior of a particular waveform during a read/verify operation, wherein the pre-conditioned waveform is applied to the drain of the selected storage element via the selected positioning element prior to correlating the read pulse. Typically, instead of applying a voltage waveform to the control gate of the storage element via the selected word line, a voltage waveform can be applied to or applied to any other terminal (such as a source or via a body bias). Bungee jumping). In this method, the 汲 terminal is accessed via a bit line associated with the NAND chain. As depicted by waveform 1450, the drain side select gate is turned on by raising V _SGD between t0 and t1, at which point preconditioning waveforms 1456 or 1460 are applied (waveforms 1454 and 1458, respectively) to the bit line. . The drain side selection gate can be turned on just before t0 until just after t1 to envelope the preconditioning waveform 1460. Read pulse 1408 occurs between t2 and t4 as previously discussed. The drain side selection gate is also opened between t2 and t4 during the read pulse. Note that the drain side selection gate can also be kept open continuously between t0 and t4.

Figure 14e is a timing diagram illustrating the behavior of a particular waveform during a read/verify operation, wherein a pre-conditioned waveform is applied to the source of the selected storage element via the source line prior to correlating the read pulse. In this method, the source terminal is accessed via a source line associated with the NAND chain. As depicted by waveform 1462 or 1464, the source side select gate is turned on by raising V _SGS between t0 and t1, at which point the preconditioned waveform 1468 in waveform 1466 is applied to the source line. The source side select gate can be turned on just before t0 until just after t1 to envelope the pre-conditioned waveform 1468. Read pulse 1408 occurs between t2 and t4 as previously discussed. The source side select gate is also turned on between t2 and t4 during the read pulse. Note that the source side selection gate can also be kept open continuously between t0 and t4.

Figure 14f is a timing diagram illustrating the behavior of a particular waveform during a read/verify operation, wherein the pre-conditioned waveform is applied to the selected storage element via a body bias prior to correlating the read pulses. In this method, the substrate bias voltage V _{B is} used to bias the substrate on which the storage element is formed. For example, V _B <0 can be used to bias the p-well of the substrate to increase the control gate to the body voltage. As depicted by waveform 1470, pre-conditioned waveform 1472 can be applied to the body between t0 and t1. Read pulse 1408 occurs between t2 and t4 as previously discussed.

Figure 14g is a flow diagram of a process for performing a read operation on a storage element, wherein a pre-conditioning waveform is applied to the storage element prior to correlating the read pulses. The read operation begins at step 1474. The index k representing the stylized state is initialized to zero at step 1475. A pre-conditioning waveform is applied at step 1476 and a read pulse is applied at step 1477. Step 1478 includes sensing whether the _VTH is above or below the read comparison point. If there is a next comparison point at decision step 1479, then the index is incremented at step 1480 and steps 1476-1478 are repeated. If there are no other comparison points, the read operation is complete and the result is stored at step 1481.

Figure 14h is a flow diagram of a process for performing a read operation on a storage element, wherein a pre-conditioning waveform is applied to the storage element prior to reading the series of pulses. The read operation begins at step 1482. At step 1485, the index k representing the stylized state is initialized to zero. A pre-conditioning waveform is applied at step 1484 and a read pulse is applied at step 1485. Step 1486 includes sensing whether the _VTH is above or below the read comparison point. If there is a next comparison point at decision step 1487, the index is incremented at step 1488 and steps 1485 and 1486 are repeated. If no other comparison points exist, the read operation is complete and the result is stored at step 1489. In this case, the pre-conditioning pulse is not used again for the read operation.

Figure 14i is a flow diagram of a process for utilizing a pre-conditioned waveform to obtain reliability measurements for subsequent utilization in decoding. See also Figure 5a, Figure 5b and Figure 8. Step 1490 includes staging the random data to the storage element, and step 1491 initializes index k to state 0. Step 1492 includes performing a _VTH measurement for each storage element written to state k, sometimes using a pre-conditioned waveform and sometimes without pre-conditioning the waveform, and/or utilizing different waveform characteristics (eg, amplitude, duration) And timing). In this manner, electrons in the storage element are affected to enter and exit the interception site, for example, to provide a more accurate _VTH distribution. Step 1493 includes obtaining a reliability measure (eg, LLR) for state k based on the measurement, and step 1494 includes storing the result. If there is a next state at decision step 1495, then k is incremented at step 1496 and steps 1492 and 1493 are repeated. If there is no next state, the process ends at step 1497.

Thus, the pre-conditioning waveform can be used in a test environment when developing reliability meters for non-volatile storage and/or in a production environment when reading non-volatile storage. In one approach, a table similar to that discussed in connection with Figures 9b through 10d can be developed with and without pre-conditioning pulses and/or with different pre-conditioning pulses. As discussed previously, these tables are then accessed during the production environment while the non-volatile storage is being read.

FIG. 15 illustrates an example of an array 1500 of NAND storage elements, such as the storage elements shown in FIGS. 1 and 2. Along each row, bit line 1506 is coupled to the drain terminal 1526 of the drain select gate of NAND string 1550. Along the NAND string, source line 1504 can be connected to all source terminals 1528 of the source select gate of the NAND string. The NAND string and storage elements are formed on p-well 1505, which in some embodiments can receive body bias _VB . Examples of NAND architecture arrays and their operation as part of a memory system are found in U.S. Patent Nos. 5,570,315, 5,774,397, and 6,046,935.

The storage element array is divided into a plurality of storage element blocks. As common to flash EEPROM systems, the block is the erase unit. That is, each block contains a minimum number of storage elements that are erased together. Each block is usually divided into a number of pages. The page is a stylized unit. In an embodiment, Individual pages can be divided into segments, and the segments can contain a minimum number of storage elements that are written once as a basic stylized operation. One or more data pages are typically stored in a storage element column. One page can store one or more sections. The section includes user data and additional item information. The additional item data typically includes an error correction code (ECC) that has been calculated from the user data for the segment. One portion of the controller (described below) calculates the ECC when the data is programmed into the array and also checks the data as it is read from the array. Alternatively, the ECC and/or other additional item data may be stored in a page or even a block other than the user profile associated with it.

The section of user data is typically 512 bytes, which corresponds to the size of the section in the disk drive. The additional item data is usually an additional 16 to 20 bytes. A large number of pages form a block, from 8 pages (for example) to any number of 32, 64, 128 or more pages. In some embodiments, a NAND string comprises a block.

In one embodiment, the selected well is made by raising the p-well 1505 formed with the NAND string and the storage element to an erase voltage (eg, 20 V) for a sufficient period of time and while the source line and the bit line are floating. The word line of the block is grounded to erase the memory storage element. Due to capacitive coupling, the unselected word lines, bit lines, select lines, and common source (c-source) also rise to a significant portion of the erase voltage. Thus, when the electrons of the floating gate are typically emitted to the substrate side by the Fowler-Nordheim tunneling mechanism, a strong electric field is applied to the tunnel oxide layer of the selected storage element and the data of the selected storage element is erased. When the electrons are transferred from the floating gate to the p-well region, the threshold voltage of the selected storage element is reduced. Can be used for the entire memory array, individual blocks or another storage component The unit performs the erase.

Figure 16 is a block diagram of a non-volatile memory system utilizing a single column/row decoder and a read/write circuit. The figure illustrates a memory device 1696 having read/write circuits for reading and programming memory element pages in parallel, in accordance with an embodiment of the present invention. Memory device 1696 can include one or more memory dies 1698. The memory die 1698 includes a two-dimensional array of storage elements 1500, a control circuit 1610, and a read/write circuit 1665. In some embodiments, the array of storage elements can be three dimensional. Memory array 1500 is accessible by word lines via column decoder 1630 and can be accessed by bit lines via row decoder 1660. The read/write circuit 1665 includes a plurality of sensing blocks 1600 and allows the storage of component pages in parallel. Typically, controller 1650 is included in a memory device 1696 (e.g., a removable memory card) that is identical to one or more memory dies 1698. Controller 1650 can include the ECC decoding capabilities discussed herein. Commands and data are transferred between the host and controller 1650 via line 1620 and transferred between the controller and one or more memory dies 1698 via line 1618.

Control circuit 1610 cooperates with read/write circuit 1665 to perform a memory operation on memory array 1500. Control circuit 1610 includes state machine 1612, on-chip address decoder 1614, boost control 1615, and power control module 1616. State machine 1612 provides wafer level control of memory operations. The on-wafer address decoder 1614 provides the address interface between the addresses utilized by the host or memory controller to the hardware addresses utilized by the decoders 1630 and 1660. The boost controller 1615 can be used to set a boost mode, including determining a timing for initializing the source side and the drain side, such as The article discusses. Power control module 1616 controls the power and voltage supplied to the word lines and bit lines during memory operation.

In some embodiments, some of the components of FIG. 16 may be combined. In various designs, one or more components (alone or in combination) in the assembly other than the storage element array 1500 can be considered a management circuit. For example, one or more management circuits may include control circuit 1610, state machine 1612, decoder 1614/1660, power controller 1616, sensing block 1600, read/write circuit 1665, controller 1650, and the like. Any one or combination.

17 is a block diagram of a non-volatile memory system utilizing a dual column/row decoder and a read/write circuit. Here, another configuration of the memory device 1696 shown in FIG. 16 is provided. Access to the memory array 1500 by various peripheral circuits is performed symmetrically on opposite sides of the array such that the density of access lines and circuitry on each side is reduced by half. Therefore, the column decoder is divided into column decoders 1630A and 1630B, and the row decoder is divided into row decoders 1660A and 1660B. Similarly, the read/write circuit is divided into a read/write circuit 1665A connected from the bottom of the array 1500 to the bit line and a read/write circuit 1665B connected from the top of the array 1500 to the bit line. In this way, the density of the read/write modules is essentially reduced by half. As described above with respect to the device of Figure 16, the device of Figure 17 may also include a controller.

18 is a block diagram depicting one embodiment of a sensing block. The individual sensing blocks 1600 are segmented into a core portion (referred to as sensing module 1680), and a common portion 1690. In one embodiment, there will be a separate sensing module 1680 for each bit line and a common portion 1690 for the collection of multiple sensing modules 1680. In an example, a sensing block will include a common portion 1690 and eight sensing modules 1680. Each of the sensing modules in the group will communicate with the associated common portion via data bus 1672. For further details, reference is made to U.S. Patent Application Publication No. 2006/014, the entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire The manner is incorporated herein.

The sensing module 1680 includes a sensing circuit 1670 that determines whether the conduction current in the connected bit line is above or below a predetermined threshold level. The sensing module 1680 also includes a bit line latch 1682 for setting a voltage condition on the connected bit line. For example, a predetermined state latched in the bit line latch 1682 will cause the connected bit line to be pulled to a state (eg, V _dd ) that the specified program is disabled.

The common portion 1690 includes a processor 1692, a data latch set 1694, and an I/O interface 1696 coupled between the data latch set 1694 and the data bus 1620. The processor 1692 performs the calculation. For example, one of its functions determines the data stored in the sensed storage element and stores the determined data in a set of data latches. The data latch set 1694 is used to store the data bits determined by the processor 1692 during the read operation. It is also used to store data bits entered from the data bus 1620 during program operation. The entered data bit represents the written data intended to be programmed into the memory. I/O interface 1696 provides an interface between data latch 1694 and data bus 1620.

During reading or sensing, the operation of the system is under the control of state machine 1612, which controls different control gate voltages to the addressed storage elements. Supply. Since it is stepped through various predetermined control gate voltages corresponding to various memory states supported by the memory, the sensing module 1680 can trip under one of the voltages and the output will be via the busbar The self-sense module 1680 is provided to the processor 1692. At this time, the processor 1692 determines the obtained memory state by considering the tripping event of the sensing module and the information about the control gate voltage applied from the state machine via the input line 1693. It then computes the binary code (codeword) for the memory state and stores the resulting data bit into data latch 1694. In another embodiment of the core portion, bit line latch 1682 provides dual use, both as latches for latching the output of sensing module 1680 and also as a bit line lock as described above. Save.

It is contemplated that some embodiments will include multiple processors 1692. In an embodiment, each processor 1692 will include an output line (not depicted) such that each of the output lines is wired-OR together. In some embodiments, the output line is inverted before being connected to a line or line. This configuration enables a quick determination of when the stylization process has completed during the program verification process because the receive line or state machine can determine when all of the stylized bits have reached the desired level. For example, when each bit has reached its desired level, a logic 0 for that bit will be sent to the line or line (or data 1 is inverted). When all bits output data 0 (inverted data 1), the state machine knows to terminate the stylization process. Because each processor communicates with eight sensing modules, the state machine needs to read the lines or lines eight times, or add logic to the processor 1692 to accumulate the result of the associated bit lines, so that the state machine only needs to read Line or line once. Similarly, by properly selecting the logical level, the whole domain The state machine can detect when the first bit changes its state and change the algorithm accordingly.

The data to be programmed is stored in the data latch set 1694 from the data bus 1620 during stylization or verification. Program operations under the control of the state machine include a series of stylized voltage pulses applied to the control gates of the addressed storage elements. Each stylized pulse is then read back (verified) to determine if the storage element has been programmed to the desired memory state. The processor 1692 monitors the read back memory state with respect to the desired memory state. When the two agree, the processor 1692 sets the bit line latch 1682 to cause the bit line to be pulled to a state where the specified program is disabled. This storage element, which is prohibited from coupling to the bit line, is further programmed, even if a stylized pulse appears on its control gate. In other embodiments, during the verification process, the processor initially loads the bit line latch 1682 and the sensing circuit sets it to a disable value.

The data latch stack 1694 contains a data latch stack corresponding to the sense module. In one embodiment, there are three data latches per sensing module 1680. In some embodiments, but not required, the data latch is implemented as a shift register such that parallel data stored therein is converted to serial data for data bus 1620, and vice versa . In a preferred embodiment, all of the data latches corresponding to the read/write blocks having m storage elements can be coupled together to form a block shift register so that it can be transferred by serial transfer. Enter or output data blocks. In particular, a group having r read/write modules is adapted such that each of its data latch sets sequentially shifts data into or out of the data bus as if it were used for One of the shift registers of the read/write block is generally.

Additional information regarding the structure and/or operation of various embodiments of non-volatile storage devices can be found in the following: (1) U.S. Patent Application Publication No. 2004/0057287, issued March 25, 2004 "Non-Volatile Memory And Method With Reduced Source Line Bias Errors"; (2) US Patent Application Publication No. 2004/0109357, published on Jun. 10, 2004, "Non-Volatile Memory And Method with Improved Sensing" (3) US Patent Application No. 11/015,199, entitled "Improved Memory Sensing Circuit And Method For Low Voltage Operation", filed on December 16, 2004; (4) Application filed on April 5, 2005 U.S. Patent Application Serial No. 11/099,133, entitled "Compensating for Coupling During Read Operations of Non-Volatile Memory"; and (5) "Reference Sense Amplifier For Non-Volatile Memory", filed on March 28, 2005 U.S. Patent Application Serial No. 11/321,953. All of the five patent documents listed immediately above are hereby incorporated by reference.

Figure 19 illustrates an example of a memory array to organization for a full bit line memory architecture or a block for a parity memory architecture. An illustrative structure of memory array 1500 is depicted. As an example, a NAND flash EEPROM that is partitioned into 1,024 blocks is described. The data stored in each block can be erased at the same time. In one embodiment, the block is the smallest storage element unit that is simultaneously erased. In this example, there are 8,512 rows corresponding to bit lines BL0, BL1, ... BL8511 in each block. Full bit line In one embodiment of the (ABL) architecture (architecture 1910), all of the bit lines of the block can be selected simultaneously during read and program operations. Storage elements along a common word line and connected to any bit line can be programmed simultaneously.

In the example provided, 64 storage elements and two dummy storage elements are connected in series to form a NAND string. There are 64 data word lines and 2 dummy word lines WL-d0 and WL-d1, wherein each NAND string includes 64 data storage elements and 2 dummy storage elements. In other embodiments, the NAND string can have more or less than 64 data storage elements and 2 dummy storage elements. The data memory unit stores user or system data. Dummy memory cells are typically not used to store user or system data.

One terminal of the NAND string is connected to the corresponding bit line via the drain select gate (connected to the select gate drain line SGD), and the other terminal is connected to the select gate source line SGS via the source select gate ) and connected to a common source.

In one embodiment, referred to as an odd-even architecture (architecture 1900), the bit lines are divided into even bit lines (BLe) and odd bit lines (BLo). In this case, the storage elements along the common word line and connected to the odd bit lines are programmed at one time, while the storage elements along the common word line and connected to the even bit lines are programmed at another time. The data can be programmed into different blocks and data can be read from different blocks at the same time. In this example, there are 8,512 rows divided into even rows and odd rows in each block.

During the configuration of one of the read and program operations, 4,256 storage elements are selected simultaneously. The selected storage elements have the same word line and the same bit line (eg, even or odd). Therefore, 532 data bytes of the logical page can be simultaneously read or programmed, and one block of the memory can be stored. At least eight logical pages (four word lines, each with odd and even pages). For multi-state storage elements, one block stores sixteen logical pages when each storage element stores two data bits (where each of the two bits is stored in a different page). Other sizes of blocks and pages can also be utilized.

For an ABL or parity architecture, the storage element can be erased by raising the p-well to an erase voltage (eg, 20 V) and grounding the word line of the selected block. The source and bit lines are floating. Erasing can be performed on the entire memory array, in a separate block, or as another storage element unit that is part of a memory device. The floating gate of the electron self-storage element is transferred to the p-well region such that the _{VTH of the} storage element becomes negative.

In the read and verify operations, the select gates (SGD and SGS) are connected to voltages in the range of 2.5 to 4.5 V, and the word lines are not selected (eg, WL0, WL1, and WL3 when WL2 is the selected word line) Rising to the read pass voltage V _READ (typically a voltage in the range of 4.5 to 6V) to operate the transistor as a pass gate. The selected word line WL2 is coupled to a voltage whose level is designated for each read and verify operation to determine if the _VTH of the associated storage element is above or below this level. For example, in a read operation for a secondary storage element, the selected word line WL2 can be grounded such that the _VTH is detected to be above 0V. In the verify operation for the secondary storage element, the selected word line WL2 is connected to, for example, 0.8 V, such that it is verified whether the _VTH has reached at least 0.8 V. The source and p wells are at 0 V. The selected positioning element line (assumed to be an even bit line (BLe)) is precharged to a level of, for example, 0.7 V. If the _{VTH is} above the read or verify level on the word line, the potential level of the bit line (BLe) associated with the storage element of interest maintains a high level due to the non-conductive storage element. On the other hand, if the _{VTH is} lower than the read or verify level, since the conductive storage element discharges the bit line, the potential level of the relevant bit line (BLe) is lowered to a low level (for example, less than 0.5 V). . The state of the storage element can thereby be detected by a voltage comparator sense amplifier connected to the bit line.

The erase, read and verify operations described above are performed in accordance with techniques known in the art. Thus, many of the details of the details explained can be changed by those skilled in the art. Other erase, read, and verify techniques known in the art can also be utilized.

Figure 20 depicts an example set of threshold voltage distributions. The condition of storing two data bits for each storage element provides an example _VTH distribution for storing the array of elements. A first threshold voltage distribution E is provided for erasing the storage element. Three threshold voltage distributions A, B, and C for the stylized storage elements are also depicted. In one embodiment, the threshold voltage in the E distribution is negative and the threshold voltage in the A, B, and C distributions is positive. Note that this simplified example refers to four states. However, additional states (eg, 16, 32, 64 or more) may be utilized.

Each distinct threshold voltage range corresponds to a predetermined value of the set of data bits. The particular relationship between the data programmed into the storage element and the threshold voltage level of the storage element depends on the data encoding mechanism used to store the component. For example, U.S. Patent No. 6,222,762 and U.S. Patent Application Publication No. 2004/0255090, the entire contents of each of Various data encoding mechanisms for storage components. In one embodiment, the data value is assigned to the threshold voltage range using a Gray code assignment such that if the floating gate is present If the voltage limit is incorrectly moved to its neighboring entity state, only one bit will be affected. An example assigns "11" to the threshold voltage range E (state E), "10" to the threshold voltage range A (state A), and "00" to the threshold voltage range B (state B), And assign "01" to the threshold voltage range C (state C). However, in other embodiments, the Gray code is not utilized. Although four states are shown, the invention may also be utilized with other multi-state structures including structures that include more or less than four states.

Three read reference voltages Vra, Vrb, and Vrc are also provided for reading data from the storage element. By testing whether the threshold voltage of a given storage element is above or below Vra, Vrb, and Vrc, the system can determine the state in which the storage element is located (eg, stylized conditions). In the case of four states, three read reference voltages or comparison points are utilized. In the case of 16 states, 15 comparison points are utilized, and so on. These are the comparison points of the types referenced at steps 1102, 1110, 1132, 1150, 1172, 1192, 1478, and 1486 previously discussed.

In addition, three verification reference voltages Vva, Vvb, and Vvc are provided. Additional verification points can be used to store storage elements that indicate additional stylized status.

When the storage elements are programmed to state A, the system will test whether their storage elements have a threshold voltage greater than or equal to Vva. When the storage element is programmed to state B, the system will test whether the storage element has a threshold voltage greater than or equal to Vvb. When the storage element is programmed to state C, the system will determine if the storage element has its threshold voltage greater than or equal to Vvc.

In one embodiment referred to as full sequence stylization, the storage component can be straight The erase state E is stylized to any of the stylized states A, B, or C. For example, the population of storage elements to be programmed may be erased first such that all storage elements in the population are in erased state E. A series of stylized pulses, such as depicted by the control gate voltage sequence of Figure 24, will then be used to program the storage elements directly into state A, B or C. When staging some of the storage elements from state E to state A, the other storage elements are programmed from state E to state B and/or from state E to state C. When staging from state E to state C on WLn, the parasitic coupling amount from WLn-1 to the adjacent floating gate is maximized because it is stylized from state E to state A or from state E to The amount of charge on the floating gate at WLn changes the most compared to the voltage change in state B. When staging from state E to state B, the amount of coupling to the adjacent floating gate is reduced, but still significant.

When staging from state E to state A, the amount of coupling is even further reduced.

Therefore, the amount of correction required to subsequently read each state of WLn-1 will vary depending on the state of the adjacent storage elements on WLn. The process shown can also be extended to an extra state.

Figure 21 illustrates an example of a two-pass technique for a stylized multi-state storage element that stores data for two different pages: a lower page and an upper page. Four states are depicted: state E (11), state A (10), state B (00), and state C (01). The process shown can also be extended to an extra state. For state E, both pages store "1". For state A, the lower page stores "0" and the upper page stores "1". For state B, both pages store "0". For state C, the lower page stores "1" and the upper page stores "0". Note that although a specific bit pattern has been assigned to Each of the states, but different bit patterns can also be assigned.

In the first stylization process, the threshold voltage level of the storage element is set according to the bit to be programmed into the lower logical page. If the bit is a logical "1", the threshold voltage does not change because it is in an appropriate state because it has been erased earlier. However, if the bit to be programmed is a logic "0", then as indicated by arrow 2100, the threshold level of the storage element is increased to state A. He ended the first stylization process.

In the second stylization process, the threshold voltage level of the storage element is set according to the bits that are programmed into the upper logical page. If the upper logical page bit will store a logic "1", no stylization will occur, because depending on the stylization of the lower page bit, the storage element is in one of the states E or A, which carry the upper page bit. "1". If the upper page bit will be a logic "0", the threshold voltage is shifted. If the first process causes the storage element to remain in the erased state E, then in the second phase, as depicted by arrow 2120, the storage element is programmed such that the threshold voltage is increased to be in state C. If the storage element has been programmed into state A due to the first stylization process, the storage element is further stylized in the second process such that, as depicted by arrow 2110, the threshold voltage is increased to be in state B. . The result of the second process is to program the storage element into the specified state to store the logic "0" for the upper page without changing the data for the lower page. In Figures 20 and 21, the amount of coupling to the floating gates on adjacent word lines depends on the final state.

In one embodiment, if enough data is written to fill the entire page, the system can be set up to perform a full sequence of writes. If sufficient data is not written for the full page, the stylization process can be stylized using the received data to be stylized. Lower page. When subsequent data is received, the system will then program the upper page. In yet another embodiment, the system can begin writing in the mode of the programmed lower page, and the system can convert if sufficient data is subsequently received to fill the storage elements of the entire word line (or a majority of the word lines). To full sequence stylized mode. Further details of this embodiment are disclosed in U.S. Patent Application Publication No. 2006/0126390, the entire disclosure of which is incorporated herein to The manner of reference is incorporated herein.

22a-22c disclose another process for programming non-volatile memory that is written to a particular page after being written to a neighboring storage element for a previous page for any particular storage element The specific storage element reduces the floating gate to floating gate coupling effect. In an example embodiment, the non-volatile storage element stores two data bits on each storage element using four data states. The process shown can also be extended to an extra state. For example, assume that state E is the erased state and states A, B, and C are stylized. State E stores data 11. State A stores data 01. State B stores data 10. State C stores data 00. This is an example of non-Gray coding because both bits change between adjacent states A and B. Other codes for the status of the data can also be used. Each storage element stores two data pages. For the purposes of this reference, such material pages will be referred to as upper and lower pages; however, they may be given other indicia. Referring to state A, the upper page stores bit 0 and the lower page stores bit 1. Referring to state B, the upper page stores bit 1 and the lower page stores bit 0. Referring to state C, both pages store bit data 0.

The stylization process is a two-step process. In the first step, the lower page is programmed. If the lower page will hold data 1, the storage element state remains in state E. If the data is programmed to zero, the voltage threshold of the storage element rises, causing the storage element to be programmed to state B'. Figure 22a thus shows the stylization of the storage element from state E to state B'. State B' is intermediate state B; therefore, the verification point is depicted as Vvb', which is lower than Vvb.

In one embodiment, after the storage element is programmed from state E to state B', its adjacent storage element (WLn+1) in the NAND string will then be programmed relative to its lower page. For example, referring to FIG. 2, after staging the lower page of storage element 106, it is possible to program the lower page of storage element 104. After staging the storage element 104, the floating gate to floating gate coupling effect will raise the apparent threshold voltage of the storage element 106 when the storage element 104 causes the threshold voltage to rise from state E to state B'. ). This will have the effect of widening the threshold voltage distribution for state B' to the threshold voltage distribution depicted as threshold voltage distribution 2250 of Figure 22b. The apparent widening of the threshold voltage distribution will be corrected when the upper page is programmed.

Figure 22c depicts the process of stylizing the upper page. If the storage element is in the erased state E and the upper page will remain at 1, the storage element will remain in state E. If the storage element is in state E and its upper page data is programmed to zero, then the threshold voltage of the storage element will rise, causing the storage element to be in state A. If the storage element is in the intermediate threshold voltage distribution 2250 and the upper page data will remain at 1, the storage element will be programmed to final state B. If the storage element is in the middle threshold voltage distribution 2250 and the upper page data will become Feed 0, the threshold voltage of the storage element will rise, causing the storage element to be in state C. The process depicted by Figures 22a through 22c reduces the floating gate to floating gate coupling effect because only the top page stylization of adjacent storage elements will have an effect on the apparent threshold voltage of a given storage element. An example of an alternate status code is to move from state 2250 to state C when the upper page data is 1, and to state B when the upper page data is zero.

Although Figures 22a through 22c provide examples of four data states and two data pages, the concepts taught can be applied to other embodiments having more or less than four states and different from two pages.

23 is a flow chart depicting one embodiment of a method for staging non-volatile memory. In one embodiment, the storage element is erased (in blocks or other units) prior to stylization. In step 2300, a "data load" command is issued by the controller and input is received by control circuit 1610. In step 2305, the address data specifying the page address is input from the controller or host to the decoder 1614. In step 2310, the program data page for the addressed page is entered into the data buffer for stylization. The data is latched into the appropriate set of latches. In step 2315, the "program" command is issued by the controller to state machine 1612.

Triggered by a "program" command, the data latched in step 2310 will be programmed to the selected memory controlled by state machine 1612 using the stepped program pulse of pulse train 2400 applied to the appropriately selected word line in FIG. In the component. In step 2320, the program voltage V _{PGM is} initialized to a start pulse (eg, 12 V or other value) and the program counter (PC) maintained by state machine 1612 is initialized to zero. In step 2330, a first V _PGM pulse is applied to the selected word line to begin programming the storage elements associated with the selected word line. If a logic "0" is stored in a particular data latch indicating that the corresponding storage element should be programmed, the corresponding bit line is grounded. On the other hand, if a logic "1" is stored in a particular latch indicating that the corresponding storage element should remain in its current data state, the corresponding bit line is connected to V _dd to disable stylization.

In step 2335, the status of the selected storage element is verified. If it is detected that the target threshold voltage of the selected storage element has reached the appropriate level, the data stored in the corresponding data latch is changed to logic "1". If it is detected that the threshold voltage has not reached the appropriate level, the data stored in the corresponding data latch is not changed. In this way, the bit line storing the logic "1" in the corresponding data latch does not need to be programmed. When all data latches store a logic "1", the state machine (via the line or type mechanism described above) knows that all selected storage elements have been programmed. In decision step 2340, a check is made as to whether all of the data latches store a logical "1". If all data latches store a logic "1", the stylization process is complete and successful because all selected storage elements are programmed and verified. The "PASS" status is reported in step 2345.

If it is determined in step 2340 that not all of the data latches store a logic "1", the stylization process continues. In decision step 2350, the program counter PC is checked against the program limit value PCmax. An example of one of the program limits is 20; however, other numbers may be utilized. If the program counter PC is not less than PCmax, the program process has failed and the "FAIL" status is reported in step 2355. If the program counter PC is less than PCmax, V _{PGM is} incremented by the step size and the program counter PC is incremented in step 2360. The process then returns to step 2330 to apply the next V _PGM pulse.

Figure 24 depicts an example pulse train 2400 applied to a control gate of a non-volatile storage element during stylization. Pulse train 2400 includes program pulse trains 2405, 2410, 2415, 2420, 2425, 2430, 2435, 2440, 2445, 2450, ... applied to selected word lines. In one embodiment, the stylized pulses have a voltage V _PGM that begins at 12 V and increases in increments (eg, 0.5 V) for each successive stylized pulse until a maximum of 20 V is reached. A system verification pulse between program pulses. For example, the set of verification pulses 2406 includes three verify pulses. In some embodiments, there may be a verify pulse for each state (eg, states A, B, and C) that the data is programmed to. In other embodiments, there may be more or fewer verification pulses. The verify pulses in each set may have amplitudes of, for example, Vva, Vvb, and Vvc (Fig. 21) or Vvb' (Fig. 22a).

As mentioned, the voltage applied to the word line to implement the boost mode is applied when stylization occurs (eg, before and during the program pulse). In practice, the boost voltage of the boost mode can be initiated slightly before each program pulse and removed after each program pulse. On the other hand, no boost voltage is applied during the verification process, for example, occurring between program pulses. The reality is that a read voltage, typically less than the boost voltage, is applied to the unselected word lines. The read voltage has an amplitude sufficient to maintain the previously programmed storage element in the NAND string open when comparing the threshold voltage of the currently programmed storage element to the verify level.

The foregoing detailed description of the present invention has been presented for purposes of illustration and description. Said. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in light of the above teachings. The embodiments described are chosen to best explain the principles of the invention and the application of the invention in the The invention is best utilized in the context of various modifications of the use. The scope of the invention is intended to be defined by the scope of the appended claims.

100‧‧‧Optoelectronics

100CG‧‧‧Control gate

100FG‧‧‧ floating gate

102‧‧‧Optoelectronics

102CG‧‧‧Control gate

102FG‧‧‧ Floating Gate

104‧‧‧Optoelectronics

104CG‧‧‧Control gate

104FG‧‧‧Floating gate

106‧‧‧Optoelectronics

106CG‧‧‧Control gate

106FG‧‧‧ Floating Gate

120‧‧‧First choice gate

120CG‧‧‧Control gate

122‧‧‧Second selection gate

122CG‧‧‧Control gate

126‧‧‧ bit line

128‧‧‧ source line

320‧‧‧NAND strings

321‧‧‧ bit line

322‧‧‧Select gate

323‧‧‧Storage components

324‧‧‧Storage components

325‧‧‧Storage components

326‧‧‧Storage components

327‧‧‧Selected gate

340‧‧‧NAND string

341‧‧‧ bit line

342‧‧‧Select gate

343‧‧‧Storage components

344‧‧‧Storage components

345‧‧‧Storage components

346‧‧‧Storage components

347‧‧‧Selecting the gate

360‧‧‧NAND string

361‧‧‧ bit line

362‧‧‧Select gate

363‧‧‧Storage components

364‧‧‧Storage components

365‧‧‧Storage components

366‧‧‧Storage components

367‧‧‧Select gate

402‧‧‧Encoder

404‧‧‧Non-volatile storage

406‧‧‧LLR (logarithmic approximate ratio) table

408‧‧‧Decoder

600‧‧‧Histogram

602‧‧‧Histogram

604‧‧‧Histogram

650‧‧‧Histogram

652‧‧‧Histogram

654‧‧‧Histogram

660‧‧‧Instance distribution

662‧‧‧Instance distribution

664‧‧‧Instance distribution

1200‧‧‧Matrix

1300‧‧‧Sparse

1400‧‧‧ waveform

1402‧‧‧ waveform

1404‧‧‧ Waveform

1406‧‧‧Pre-adjusted waveform

1408‧‧‧Read pulse

1410‧‧‧ waveform

1412‧‧‧ waveform

1414‧‧‧ waveform

Line 1415‧‧

1416‧‧‧ Curve

1418‧‧‧ waveform

1419‧‧‧ waveform

1420‧‧‧ waveform

1422‧‧‧ waveform

1424‧‧‧ Waveform

1426‧‧‧Pre-adjusted waveform

1427‧‧‧Read pulse

1428‧‧‧Pre-adjusted waveform

1429‧‧‧Read pulse

1430‧‧‧Pre-adjusted waveform

1431‧‧‧Read pulse

1432‧‧‧ Waveform

1435‧‧‧ waveform

1436‧‧‧ waveform

1437‧‧‧ waveform

1438‧‧‧ waveform

1439‧‧‧ waveform

1440‧‧‧ waveform

1441‧‧‧Pre-adjusted waveform

1442‧‧‧ waveform

1443‧‧‧Pre-adjusted waveform

1444‧‧‧ waveform

1445‧‧‧Pre-adjusted waveform

1446‧‧‧ Waveform

1447‧‧‧Pre-adjusted waveform

1450‧‧‧ waveform

1454‧‧‧ waveform

1456‧‧‧Pre-adjusted waveform

1458‧‧‧ Waveform

1460‧‧‧Pre-adjusted waveform

1462‧‧‧ waveform

1464‧‧‧ Waveform

1466‧‧‧ waveform

1468‧‧‧Pre-adjusted waveform

1470‧‧‧ waveform

1472‧‧‧Pre-adjusted waveform

1500‧‧‧Array

1504‧‧‧Source line

1505‧‧‧p well

1506‧‧‧ bit line

1526‧‧‧汲 extremes

1528‧‧‧ source terminal

1550‧‧‧NAND string

1600‧‧‧Sensing block

1610‧‧‧Control circuit

1612‧‧‧ state machine

1614‧‧‧ on-chip address decoder

1615‧‧‧Supercharger controller

1616‧‧‧Power Control Module

1618‧‧‧ line

1620‧‧‧ line

1630‧‧‧ column decoder

1630A‧‧‧ column decoder

1630B‧‧‧ column decoder

1650‧‧‧ Controller

1660‧‧‧ row decoder

1660A‧‧ ‧ row decoder

1660B‧‧ ‧ row decoder

1665‧‧‧Read/Write Circuit

1665A‧‧‧Read/Write Circuit

1665B‧‧‧Read/Write Circuit

1670‧‧‧Sensor circuit

1672‧‧ ‧ busbar

1680‧‧‧Sensor module

1682‧‧‧ bit line latch

1690‧‧‧Common part

1692‧‧‧ processor

1693‧‧‧Input line

1694‧‧‧ Data Latches

1696‧‧‧Memory device/I/O interface

1698‧‧‧ memory grain

1900‧‧‧ architecture

1910‧‧‧ Architecture

2100‧‧‧ arrow

2110‧‧‧ arrow

2120‧‧‧ arrow

2400‧‧‧pulse

SGD‧‧‧ selection line

SGS‧‧‧Selection line

WL0‧‧‧ word line

WL1‧‧‧ word line

WL2‧‧‧ word line

WL3‧‧‧ word line

Figure 1 is a top view of the NANE string.

2 is an equivalent circuit diagram of the NAND string of FIG. 1.

3 is a block diagram of an NAND flash storage element array.

Figure 4 depicts a system for data encoding and decoding of non-volatile storage.

Figure 5a is a flow diagram of a process for obtaining a first probability density function f1 for a non-volatile storage element set.

Figure 5b is a flow diagram of a process for obtaining a second probability density function f2 for a non-volatile storage element set.

Figure 6a depicts the distribution of voltage threshold readings.

Figure 6b depicts the noise-free threshold reading.

Figure 6c depicts the distribution of noise-free threshold readings.

Figure 6d depicts the probability distribution of voltage thresholds for different states of the non-volatile storage element set.

Figure 7a depicts the distribution of voltage threshold deviations for example states of non-volatile storage elements.

Figure 7b depicts the distribution of voltage threshold deviations for example states of a non-volatile storage element set.

Figure 7c depicts the probability distribution of the voltage threshold deviation of state 0 of the non-volatile storage element set.

Figure 7d depicts the probability distribution of the voltage threshold deviation for state 1 of the non-volatile storage element set.

Figure 7e depicts the probability distribution of the voltage threshold deviation for state 15 of the non-volatile storage element set.

8 is a flow diagram of a process for obtaining a logarithmic power ratio (LLR) for decoding read data from a non-volatile storage element.

Figure 9a depicts a table providing multi-bit codewords for different programmed states of non-volatile storage elements.

Figure 9b depicts a table that provides an initial value of LLR for each bit of a codeword based on the first read result.

Figure 9c depicts a table providing adjustments to the current value of the LLR utilized by the decoder for each bit of the codeword based on the second read result.

Figures 10a through 10d depict a table that provides an initial value of LLR for each bit of a codeword based on the first read result and the second read result.

Figure 11a is a flow diagram of a process for decoding a codeword representing the state of a non-volatile storage element, wherein an initial probability meter is obtained based on a first read operation and a second read operation.

Figure 11b is a flow diagram of a process for decoding a codeword representing a state of a non-volatile storage element, wherein an initial probability meter is obtained based on a first read operation, and then further adjusted based on the second read operation Adjusted The whole rate is measured.

Figure 11c is a flow diagram of a process for decoding a codeword representing a state of a non-volatile storage element, wherein an initial probability meter is obtained based on a first read operation, followed by a first read operation and a second read Based on the operation to obtain a new initial probability measurement.

Figure 12 depicts a sparse parity check matrix.

Figure 13 depicts a sparse diffractogram corresponding to the sparse parity check matrix of Figure 12.

Figure 14a is a timing diagram illustrating the behavior of a particular waveform during a read/verify operation, where a pre-conditioned waveform is applied to a selected word line prior to correlating the read pulses.

Figure 14b is a timing diagram illustrating the behavior of a particular waveform during a read/verify operation, wherein one or more pre-conditioned waveforms are applied to the selected word line prior to correlating the read pulses.

Figure 14c is a timing diagram depicting different pre-conditioning waveforms.

Figure 14d is a timing diagram illustrating the behavior of a particular waveform during a read/verify operation, wherein the pre-conditioned waveform is applied to the drain of the selected storage element via the selected positioning element prior to correlating the read pulse.

Figure 14e is a timing diagram illustrating the behavior of a particular waveform during a read/verify operation, wherein a pre-conditioned waveform is applied to the source of the selected storage element via the source line prior to correlating the read pulse.

Figure 14f is a timing diagram illustrating the behavior of a particular waveform during a read/verify operation, wherein the pre-conditioned waveform is applied to the selected storage element via a body bias prior to correlating the read pulses.

Figure 14g is a flow chart of a process for performing a read operation on a storage element A diagram in which a pre-conditioning waveform is applied to a storage element prior to associating a read pulse.

Figure 14h is a flow diagram of a process for performing a read operation on a storage element, wherein a pre-conditioning waveform is applied to the storage element prior to reading the series of pulses.

Figure 14i is a flow diagram of a process for utilizing a pre-conditioned waveform to obtain reliability measurements for subsequent utilization in decoding.

Figure 15 is a block diagram of an array of NAND flash memory elements.

Figure 16 is a block diagram of a non-volatile memory system utilizing a single column/row decoder and a read/write circuit.

17 is a block diagram of a non-volatile memory system utilizing a dual column/row decoder and a read/write circuit.

18 is a block diagram depicting one embodiment of a sensing block.

Figure 19 illustrates an example of a memory array to organization for a full bit line memory architecture or a block for a parity memory architecture.

Figure 20 depicts an example set of threshold voltage distributions.

Figure 21 depicts an example threshold voltage distribution set.

Figures 22a through 22c show various threshold voltage distributions and describe the process for programming non-volatile memory.

23 is a flow chart depicting one embodiment of a process for programming non-volatile memory.

Figure 24 depicts an example pulse train applied to a control gate of a non-volatile storage element during stylization.

(no component symbol description)

Claims (16)

A method for decoding data in a non-volatile memory, comprising: performing a multiple sensing operation on at least one non-volatile storage element, the multiple sensing operations including a first sensing operation and at least a subsequent sense Using a iterative probability decoding to determine a stylized state of the at least one non-volatile storage element, the iterative probability decoding utilizing a reliability measure based on the multiple sensing operations, wherein the iterative probability decoding Iterating initially using a first reliability measure based on the first sensing operation rather than the at least one subsequent sensing operation; adjusting the first reliability meters to obtain an adjusted reliability at the iterative probability decoding iteration And metering; and based on the at least one subsequent sensing operation, adjusting the adjusted reliability metering when the iterative probability decoding further iterates. The method of claim 1, wherein the reliability measures comprise a logarithmic approximation ratio. The method of claim 1, wherein the sensing operations comprise a read operation. The method of claim 1, further comprising: providing, for each of the multiple sensing operations, a bit representing a sensed stylized state of one of the at least one non-volatile storage element, the reliable A measure is provided for each of the bits. The method of claim 4, further comprising: reading a cross-reference sensed stylized state and a bit and reliability meter The table of quantities. The method of claim 1, wherein the iterative probability decoding attempts to satisfy a parity check of an error correction code. The method of claim 6, wherein the error correction code comprises a low density parity check code applied to the set of non-volatile storage elements comprising the at least one non-volatile storage element. The method of claim 1, further comprising: determining, based on the multiple sensing operations, an initial set of reliability measurements to utilize in the iterative probability decoding. The method of claim 1, wherein the adjusted reliability measure is adjusted when one of the at least one subsequent sensing operations is consistent with the sensed stylized state by one of the first sensing operations Indicates a higher reliability. The method of claim 1, wherein the adjusted reliability measure is adjusted when one of the at least one subsequent sensing operations is inconsistent with the sensed stylized state by one of the first sensing operations Indicates a lower reliability. The method of claim 1, further comprising: restarting the iterative probability decoding process with probability metering based on the first sensing operation and the at least one subsequent sensing operation. The method of claim 1, further comprising: obtaining the at least one non-volatile for each of the plurality of stylized states based on a plurality of sensing operations performed on a set of non-volatile storage elements An overview of the voltage threshold of the storage element; Providing a set of reliability measures based on the voltage threshold profiles; and accessing the reliability measures used in the iterative probability decoding from the set of reliability meters. The method of claim 12, wherein the providing the reliability measurement set comprises: determining a conditional probability function f1(u|X) based on the plurality of sensing operations, wherein u indicates a sense threshold voltage, and X represents a programmed state of the plurality of stylized states; and a probability function f2(v) is determined for each stylized state based on the plurality of sensing operations, wherein v indicates a sensing threshold The voltage is one deviation from the threshold voltage of one of the read noises. A non-volatile storage system comprising: a set of non-volatile storage elements; and one or more control circuits in communication with the non-volatile storage element set, the one or more control circuits: for at least one non-volatile storage The component performs a multiple sensing operation, the multiple sensing operations including a first sensing operation and at least one subsequent sensing operation; determining, by using iterative probability decoding, a stylized state of the at least one non-volatile storage element, Iterative probability decoding utilizes reliability metering based on the multiple sensing operations, wherein the iterative probability decoding initially utilizes first reliability based on the first sensing operation rather than the at least one subsequent sensing operation Metering to iterate; adjusting the first reliability measure to obtain an adjusted reliability measure at the iterative probability decoding iteration; and using the at least one subsequent sense Based on the operation, the adjusted reliability measures are adjusted as the iterative probability decoding is further iterated. The non-volatile storage system of claim 14, wherein: the iterative probability decoding attempts to satisfy a parity check of an error correction code; and the error correction code includes a low density parity check code, the low density parity check code being applied to The non-volatile storage element set of the at least one non-volatile storage element is included. The non-volatile storage system of claim 14, wherein: when one of the at least one subsequent sensing operations is consistent with the sensed stylized state by one of the first sensing operations, the adjusted The metering is adjusted to indicate a higher reliability; and when one of the at least one subsequent sensing operations is inconsistent with the sensed stylized state by one of the first sensing operations, the adjusted The metering is adjusted to indicate a lower reliability.