TWI396162B - Pixel structures, display panels, display devices, and electronic devices - Google Patents

Description

Pixel structure, display panel, display device, and electronic device

The present invention relates to a pixel, and more particularly to a pixel suitable for an organic light emitting display panel.

Fig. 1 is a schematic diagram showing a pixel of a display array in a conventional organic light-emitting display panel. As shown in FIG. 1, the pixel 1 corresponds to the interleaved data line DL and the scanning line SL, and includes a switching transistor 10, a storage capacitor 11, a driving transistor 12, and an organic light emitting diode (OLED) 13. In Fig. 1, the driving transistor 12 is a PMOS transistor as an example.

Since the OLED 13 is a current-driven component, the value of the drive current Id provided by the drive transistor 12 determines the brightness of the light emitted by the OLED 13. The driving current Id is the driving current of the driving transistor 12, and its driving ability with respect to the driving transistor 12. The drive current Id can be expressed by the following equation: id = 1/2. k . ( vsg -∣ vt h∣) ²

Where id represents the value of the drive current Id, k represents the conduction parameter of the drive transistor 12, vsg represents the value of the source-gate voltage Vsg of the drive transistor 12, and vth represents the threshold voltage of the drive transistor 12.

However, due to the process factors of the thin film transistor, the driving transistors in different regions of the display array are electrically different, so that the threshold voltage values of the driving transistors are different. Therefore, when the plurality of display units of different regions receive the same video signal, due to the driving transistor The difference in threshold voltages makes the values of the drive currents supplied by the drive transistors inconsistent among these pixels. Therefore, the brightness emitted by the organic light-emitting diodes is different, resulting in unequal organic light-emitting diode light-emitting intensity in a frame period and uneven display on the display panel.

The present invention provides a pixel structure including a capacitor, a transfer circuit, first to third switching elements, and a driving element. The capacitor is coupled between the first node and the second node. The transmitting circuit is coupled to the first node and transmits the data signal or the reference voltage to the first node. The first switching element has a control end, a first end coupled to the second node, and a second end coupled to the third node. The second switching element has a first end coupled to the third node and a second end receiving the clock signal. The driving component has a control terminal coupled to the second node, a first end coupled to the supply voltage source, and a second end, wherein the second end of the driving component coupled to the first switching component is controlled by a fourth node. The third switching element has a control end for receiving the illumination signal, a first end coupled to the fourth node, and a second end. The fourth switching element is coupled between the second end of the third switching element and the ground.

In order to make the features and advantages of the present invention more comprehensible, the following detailed description of the preferred embodiments and the accompanying drawings.

Fig. 2 is a view showing a display panel according to an embodiment of the present invention. Referring to FIG. 2, the display panel 2 includes a data driver 20, a scan driver 21, a display array 22, sequentially arranged data lines DL ₁ to DL _n , and sequentially arranged scan lines SL ₁ to SL _m . The display array 22 is formed of interleaved data lines OL ₁ to DL _n and scan lines SL ₁ to SL _m . Each set of interleaved data lines corresponds to one pixel of the scan line. For example, the interleaved data line DL ₁ corresponds to the scanning line SL ₁ corresponding to the pixel 200. The data driver 20 supplies the data signals DS ₁ to DS _n through the data lines DL ₁ to DL _n , respectively. The scan driver 21 supplies scan signals SS ₁ to SS _m through scan lines SL ₁ to SL _m , respectively.

Referring to FIG. 2, the pixel 200 (other pixels are also included) includes a transfer circuit 209, switching elements 203-205, a storage capacitor 206, a driving element 207, and a light-emitting element 208. The transmission circuit 209 includes switching elements 201 and 202 and transmits a data signal or a reference voltage to the first node N21. In this embodiment, the light-emitting element 208 is implemented by the light-emitting diode L208, and the switching elements 201 and 203-205 and the driving element 207 are implemented by PMOS transistors P201, P203-P205, and P207, respectively, and the switching element 202 is NMOS. The transistor N202 is implemented. Each element 202-205 and 207 includes a control end, a first end, and a second end. According to the type of the transistor, the control end corresponds to the gate, the first end corresponds to the second end corresponds to the source/drain.

As shown in FIG. 2, in the pixel 200, PMOS transistor gate electrode 201 of the receive scan signals SS _1, a source receiving the data signals DS _1, and its drain coupled to the node N21. The gate of the NMOS transistor N202 receives the scan signal SS ₁ , the drain coupled to the node N21, and the source thereof is coupled to the reference voltage source VREF, wherein the reference voltage source VREF provides the reference signal vref. The storage capacitor 206 is coupled between the node N21 and the node N22. Referring to FIG. 2, the gate of the PMOS transistor P203 is coupled to the node N24, the source of which is coupled to the node N22, and the drain of which is coupled to the node N23. The gate of the PMOS transistor P204 receives the scan signal SS ₁ , the source of which is coupled to the node N23, and the drain of which receives the clock signal CLK ₁ . The gate of the PMOS transistor P207 is coupled to the node N22, the source of which is coupled to the supply voltage source PVDD, and the drain of which is coupled to the node N24. The gate of the PMOS transistor P205 receives the illuminating signal ES ₁ and its source is coupled to the node N24. The light emitting diode L208 is coupled between the drain of the PMOS transistor P205 and the ground GND. In this embodiment, the supply voltage source PVDD provides a high level of voltage. The clock signal CLK ₁ and the illumination signal ES _{1 are} provided by the scan driver 12 or an additional control circuit. In the embodiment of FIG. 2, the scan driver 12 is exemplified by the clock signal CLK ₁ and the illumination signal ES ₁ .

Fig. 3 is a timing chart showing a scanning signal, a clock signal, and an illuminating signal for one pixel in the embodiment of Fig. 2, wherein the scanning signal and the clock signal are mutually inverted. In Fig. 3, the scanning signal SS ₁ corresponding to the pixel 200, the clock signal CLK ₁ , and the lighting signal ES _{1 are taken} as an example.

Referring to Fig. 3, a picture frame FRAME (i.e., an operation cycle) is divided into three consecutive periods P31-P33. Referring to Figures 2 and 3, in period P31, scan signal SS ₁ and illumination signal ES ₁ are at a low logic level, and clock signal CLK _{1 is} at a high logic level. Therefore, the PMOS transistors P201, P204, and P205 are turned on, and the NMOS transistor N202 is turned off. In this embodiment, the high level of the voltage vclk of the clock signal CLK ₁ is equal to the voltage vpvdd supplied by the supply voltage source PVDD. Vn21 voltage of the node N21 is equal to the voltage of the data signals DS vdata (vn21 = vdata) of _1, in other words, the data signal DS ₁ 200 is written to the pixel. Since the PMOS transistor P205 is turned on, the voltage vn24 of the node N24 is discharged to a low logic level to turn on the PMOS transistor P203. Since the PMOS transistors P203 and P204 is turned on, the voltage of the node N22 vn22 equal to the high logic level voltage when the clock signal CLK ₁ vclk of (vn22 = vclk = vpvdd), to turn off the PMOS transistor P207.

In the period P32, referring to Figures 2 and 3, the scan signal SS _{1 is} maintained at a low logic level, the clock signal CLK _{1 is} maintained at a high logic level, and the illumination signal ES _{1 is} switched to a high logic level to turn off the PMOS power. Crystal P205. Vn21 voltage of the node N21 is still equal to the voltage of the data signals DS vdata (vn21 = vdata) of _1, and the node voltage vn22 N22 when the clock signal CLK remains equal to the voltage vclk _{1 (vn22 = vclk = vpvdd)} . The voltage vn24 of the node N24 is equal to the low logic level voltage vx (vn24=vx).

Subsequently, during the start time point T33 P33, the clock signal CLK ₁ is switched to a low logic level, and the node voltage vn22 N22 thus becomes low level to turn power crystals P207. Since the PMOS transistor P207 is turned on, the voltage vn24 of the node N24 becomes a high logic level to turn off the PMOS transistor P203. In addition, the scan signal SS _{1 is} switched to a high logic level to turn off the PMOS transistors P201 and P204 and turn on the NMOS transistor N202. The voltage vn21 is equal to (vdata - Δv), where Δv = vdata - vref. Therefore, the voltage vn21 is represented by the following equation: vn 21= vdata -Δ v = vdata -( vdata - vref )= vref

Since node N22 is floating, nodes N21 and N22 across storage capacitor 206 have the same voltage difference. The voltage vn22 is represented by the following equation: vn 22= vpvdd -| vth |-△ v = pvdd -| vth |-( vdata-vref )= vpvdd- | vth | vdata + vref

Where vth represents the threshold voltage of the PMOS transistor P207 .

In the period P33, the PMOS transistor P207 supplies the driving current Id, and the driving current Id is expressed by Equation 1:

Where id and k represent the value of the driving current Id and the conduction parameter of the PMOS transistor P207, respectively.

Referring to Figure 3, the starting point of time T33, light emission signal ES ₁ switches to a low logic level, and the drive current Id L208 driving light-emitting diodes emit light. In some embodiments, the illumination signal ES ₁ may be switched to a low logic level at a time later than the start time point T33 in time P33, and the light emitting diode L208 emits light after the start time point T33.

According to Equation 1, the threshold voltage of the PMOS transistor P207 does not affect the drive current Id. In other words, the display panel can provide a uniform picture because the difference in electrical characteristics of the driving transistor caused by the process does not affect the brightness of the light-emitting element.

In addition, in the conventional large display panel, the pixel that is far away from the sweep voltage input corresponds to the equivalent impedance of the power supply line of the larger supply voltage source PVDD, and receives a weaker voltage, resulting in uneven brightness. According to Equation 1, the voltage vpvdd from the supply voltage source PVDD does not affect the drive current Id, so that a long power line can be prevented from causing an uneven picture.

It should be noted that in the embodiment of FIG. 2, the gate of the PMOS transistor P204 receives the scan signal SS ₁ . In some embodiments, the gate of PMOS transistor 204 can receive a control signal CS ₁ that is provided by scan driver 21 or an additional circuit, as shown in FIG. Fig. 5 is a timing chart showing scanning signals, control signals, clock signals, and illuminating signals for one pixel in the embodiment of Fig. 4. In Fig. 5, the scanning signal SS ₁ corresponding to the pixel 200, the control signal CS ₁ , the clock signal CLK ₁ , and the illumination signal ES _{1 are taken} as an example.

Referring to Fig. 5, a picture frame FRAME (i.e., an operation cycle) is divided into five consecutive periods P51-P55. Referring to Figures 4 and 5, in period P51, scan signal SS ₁ , control signal CS ₁ , and illumination signal ES ₁ are at a low logic level, and clock signal CLK _{1 is} at a high logic level. Therefore, the PMOS transistors P201, P204, and P205 are turned on, and the NMOS transistor N202 is turned off. In this embodiment, the high level of the voltage vclk of the clock signal CLK ₁ is equal to the voltage vpvdd supplied by the supply voltage source PVDD. Vn21 voltage of the node N21 is equal to the voltage of the data signals DS vdata (vn21 = vdata) of _1, in other words, the data signal DS ₁ 200 is written to the pixel. Since the PMOS transistor P205 is turned on, the voltage vn24 of the node N24 is discharged to a low logic level to turn on the PMOS transistor P203. Since the PMOS transistors P203 and P204 is turned on, the voltage of the node N22 vn22 equal to the high logic level voltage when the clock signal CLK ₁ vclk of (vn22 = vclk = vpvdd), to turn off the PMOS transistor P207.

In the period P52, referring to Figures 4 and 5, the scan signal SS ₁ and the control signal CS _{1 are} maintained at a low logic level, and the clock signal CLK _{1 is} maintained at a high logic level. The illuminating signal ES _{1 is} switched to a high logic level to turn off the PMOS transistor P205. Vn21 voltage of the node N21 is still equal to the voltage of the data signals DS vdata (vn21 = vdata) of _1, and the node voltage vn22 N22 when the clock signal CLK remains equal to the voltage vclk _{1 (vn22 = vclk = vpvdd)} . The voltage vn24 of node N24 is equal to the low logic level voltage vx (vn24=vx).

Next, in period P53, the scan signals SS ₁ and the control signal CS ₁ is maintained at a low logic level, the light emission signal ES ₁ maintained at a high logic level. Vn21 voltage of the node N21 is still equal to the voltage of the data signals DS vdata (vn21 = vdata) of _1. The clock signal CLK ₁ switches to a low logic level at the start time T53, and the voltage vn22 of the node N22 thus becomes a low logic level to turn on the PMOS transistor P207. Since the PMOS transistor P207 is turned on, the voltage vn24 of the node N24 becomes a high logic level to turn off the PMOS transistor P203. After the PMOS transistor P207 is turned on, the voltage vn22 is equal to (vpvdd-vth), where vth represents the threshold voltage of the PMOS transistor P207 .

Then, during P54, the scan signals SS ₁ and clock signal CLK ₁ is maintained at a low logic level, the light emission signal ES ₁ maintained at a high logic level. The control signal CS _{1 is} switched to a high logic level to turn off the PMOS transistor P204. Vn21 voltage node N21 is still equal to the voltage data signal DS vdata (vn21 = vdata) of _1. The voltage vn22 of the node N22 is equal to (vpvdd-vth).

Then, during the starting time point T55 P55, the scan signal SS ₁ is switched to a high logic level to turn off the PMOS transistor P201 is turned on and the NMOS transistor N202. The voltage vn21 is equal to (vdata - Δv), where Δv = vdata = vref. Therefore, the voltage vn21 is represented by the following equation: vn 21= vdata -Δ v = vdata -( vdata - vref )= vref

Control signal CS _{1 is} maintained at a high logic level to turn off PMOS transistor P204. Since node N22 is floating, nodes N21 and N22 across storage capacitor 206 have the same voltage difference. The voltage vn22 is represented by the following equation: vn 22= vpvdd -| vth |-△ v = pvdd -| vth |-( vdata - vref )= vpvdd -| vth |- vdata + vref

In the period P55, since the PMOS transistor P207 maintains the on state, it supplies the driving current Id, and the driving current Id is expressed by Equation 2:

Where id and k represent the value of the driving current Id and the conduction parameter of the PMOS transistor P207, respectively.

Referring to Figure 5, the starting time point T55, the lighting signal ES ₁ switches to a low logic level, and the drive current Id L208 driving light-emitting diodes emit light. In some embodiments, the illumination signal ES ₁ may be switched to a low logic level at a time later than the start time point T55 in time P55, and the light emitting diode L208 emits light after the start time point T55.

According to Equation 2, the threshold voltage of the PMOS transistor P207 does not affect the drive current Id. In other words, the display panel can provide a uniform picture because the difference in electrical characteristics of the driving transistor caused by the process does not affect the brightness of the light-emitting element. In addition, the voltage vpvdd from the supply voltage source PVDD does not affect the drive current Id, thus avoiding longer power supplies Lines cause uneven images.

Fig. 6 shows a display device 6 having an upper display panel 2. In general, the display device 6 includes the controller 60, the display panel 2 of FIG. 2, and the like. The controller 60 is operatively coupled to the display panel 2 and provides a plurality of control signals (eg, initial pulse waves) or image data and the like to the display panel 2.

Fig. 7 shows an electronic system 7 having the above display device 6. The electronic system 7 can be a portable device (such as a personal digital assistant (PDA)), a digital camera, a notebook computer, a desktop computer, a mobile phone, a display screen device, and the like. In general, the electronic system 7 includes an input unit 70, a display device 6 of FIG. 6, and the like. In addition, the input unit 70 is operatively coupled to the display device 6 and provides a plurality of input signals (eg, image signals) to the display device 6. The controller 60 of the display device 6 provides a control signal to the display panel 2 based on these input signals.

The present invention has been disclosed in the above preferred embodiments, and is not intended to limit the scope of the present invention. Any one of ordinary skill in the art can make a few changes without departing from the spirit and scope of the invention. The scope of protection of the present invention is therefore defined by the scope of the appended claims.

1‧‧‧ pixels

10‧‧‧Switching transistor

11‧‧‧Storage capacitor

12‧‧‧Drive transistor

13‧‧‧Organic Luminescent Diodes

DL‧‧‧ data line

Id‧‧‧ drive current

SL‧‧‧ scan line

2‧‧‧ display panel

20‧‧‧Data Drive

21‧‧‧Scan Drive

22‧‧‧Display array

200‧‧ ‧ pixels

209‧‧‧Transmission circuit

203-205‧‧‧Switching elements

206‧‧‧Storage capacitor

207‧‧‧ drive components

208‧‧‧Lighting elements

CLK ₁ ‧‧‧ clock signal

DL ₁ ... DL _n ‧‧‧ data line

DS ₁ ...DS _n ‧‧‧ data signal

GND‧‧‧ Grounding

N21-N24‧‧‧ node

N202‧‧‧NMOS transistor

P201, P203-P205, P207‧‧‧ PMOS transistor

PVDD‧‧‧ supply voltage source

SL ₁ ...SL _m ‧‧‧ scan line

SS ₁ ...SS _m ‧‧‧scanning signal

VREF‧‧‧reference voltage source

CS ₁ ‧‧‧Control signal

6‧‧‧ display device

60‧‧‧ Controller

7‧‧‧Electronic system

70‧‧‧ input unit

Fig. 1 is a view showing a schematic diagram of a pixel of a display array in a conventional organic light-emitting display panel.

Fig. 2 shows a display panel according to an embodiment of the present invention.

Figure 3 is a timing chart showing the scanning signal, the clock signal, and the illuminating signal for one pixel in the embodiment of Fig. 2.

Figure 4 shows another display panel in accordance with an embodiment of the present invention.

Fig. 5 is a timing chart showing scanning signals, control signals, clock signals, and illuminating signals for one pixel in the embodiment of Fig. 4.

Fig. 6 shows a display device having the display panel of Fig. 2.

Fig. 7 shows an electronic device having the display device of Fig. 6.

2‧‧‧ display panel

20‧‧‧data zone

21‧‧‧Scan Drive

22‧‧‧Display array

200‧‧ ‧ pixels

209‧‧‧Transmission circuit

203-205‧‧‧Switching elements

206‧‧‧Storage capacitor

207‧‧‧ drive components

208‧‧‧Lighting elements

CLK ₁ ‧‧‧ clock signal

DL ₁ -DL _n ‧‧‧ data line

DS ₁ DS _n ‧‧‧ data signal

GND‧‧‧ Grounding

N21-N24‧‧‧ node

N202‧‧‧NMOS transistor

P201, P203-P205, P207‧‧‧ PMOS transistor

PVDD‧‧‧ supply voltage source

SL ₁ ...SL _m ‧‧‧ scan line

SS ₁ ...SS _m ‧‧‧scanning signal

VREF‧‧‧reference voltage source

Claims (20)

A pixel structure includes: a capacitor coupled between a first node and a second node; a transmitting circuit coupled to the first node and transmitting a data signal or a reference voltage to the first node a first switching element having a control end, a first end coupled to the second node, and a second end coupled to a third node; a second switching element having a first coupled to the third node And a second terminal that receives a clock signal; a driving component having a control terminal coupled to the second node, a first end coupled to a supply voltage source, and a second end, wherein the driving component is The second end is coupled to the control end of the first switching element to a fourth node; a third switching element has a control end for receiving an illumination signal, a first end coupled to the fourth node, and a second end; A light emitting component is coupled between the second end of the third switching component and a ground. The pixel structure of claim 1, wherein the transmitting circuit comprises: a fourth switching element having a control end for receiving a scan signal, receiving a first end of the data signal, and coupling the first a second end of the node; and a fifth switching element having a control end for receiving the scan signal, coupled to the first end of the first node, coupled to the second of the reference voltage end. The pixel structure of claim 2, wherein the second switching element further has a control end for receiving the scan signal. The pixel structure of claim 2, wherein an operation period of the pixel structure is divided into consecutive first, second, and third periods, and a voltage of the data signal is written during the first period. The pixel structure is entered, and the light emitting element emits light during the third period. The pixel structure of claim 4, wherein, in the first period, the second and fourth switching elements are turned on according to the scan signal, and the fifth switching element is turned off according to the scan signal, and The third switching element is turned on according to the illuminating signal. The pixel structure of claim 5, wherein the third switching element is turned off according to the illuminating signal during the second period. The pixel structure of claim 6, wherein at the first time of the third period, the second and fourth switching elements are turned off according to the scan signal, and the fifth switching element is The scan signal is turned on, and the third switching element is turned on according to the light emitting signal. The pixel structure of claim 6, wherein in the third period, the second and fourth switching elements are turned off according to the scan signal at a first time point, the fifth switching element Turning on according to the scan signal, and at a second time later than the first time point, the third switching element is turned on according to the illuminating signal. The pixel structure of claim 8, wherein the supply voltage source provides a high logic level voltage, and the clock signal is in the The first and second periods are at a high logic level and are at a low logic level during the third period. The pixel structure of claim 2, wherein the second switching element further has a control end for receiving a control signal. The pixel structure of claim 10, wherein an operation period of the pixel structure is divided into consecutive first, second, third, fourth, and fifth periods, and the voltage of the data signal The pixel structure is written to the pixel during the first period, and the light emitting element emits light during the fifth period. The pixel structure of claim 11, wherein, in the first period, the fourth and fifth switching elements are respectively turned on and off according to the scan signal, and the second switching element is turned on according to the control signal. And the third switch is turned on according to the illuminating signal. The pixel structure of claim 12, wherein the third switching element is turned off according to the illuminating signal during the second period. The pixel structure of claim 13, wherein the second switching element is turned off according to the control signal during the fourth period. The pixel structure of claim 14, wherein at the first time point of the fifth period, the fourth and fifth switching elements are respectively turned off and on according to the scan signal, and the third The switching element is turned on in accordance with the illuminating signal. The pixel structure of claim 14, wherein, in the fifth period, the fourth and fifth switching elements are respectively turned off and on according to the scan signal at a first time point, and Later than the second time point of the first time point, the third switching element is illuminated according to the third time The signal is turned on. A display panel includes: a data driver for providing a plurality of data signals through a plurality of data lines; and a scan driver for providing a plurality of scan signals through the plurality of scan lines, wherein the scan lines are interlaced with the data lines; A display array is formed by the data lines and the scan lines, and includes a complex pixel structure, wherein each pixel structure includes: a capacitor coupled between a first node and a second node a transmitting circuit coupled to the first node and transmitting a data signal or a reference voltage to the first node; a first switching element having a control end, a first end coupled to the second node, and a coupling a second terminal of the third node; a second switching element having a first end coupled to the third node and a second end receiving a clock signal; a driving component having a second node coupled thereto The control terminal is coupled to the first end of the power supply voltage source and the second end, wherein the second end of the driving component is coupled to the control end of the first switching component to a fourth node; a third switching element a control terminal for receiving an illumination signal, a first end coupled to the fourth node, and a second end; and a fourth switching element coupled between the second end of the third switching element and a ground . A display device comprising: The display panel of claim 17; and a controller operatively coupled to the display panel. An electronic device comprising: the display device of claim 18; and an input unit operatively coupled to the display device. The electronic device of claim 19, wherein the electronic device is a personal digital assistant (PDA), a digital camera, a notebook computer, a desktop computer, a mobile phone, or a display screen device. .