TWI395403B - Level shifter - Google Patents

Description

Converter

The invention relates to a pressure converter, in particular to a pressure converter capable of effectively reducing the layout area.

The converter can receive input signals with a small signal range and convert them correspondingly into output signals with a large signal range, which is an important building block in the interface circuit. For example, in the source driver chip that drives the display panel, the signal range of the original control signal in the chip can be 0 to 2 volts. However, when the output driving the display panel, the required signal range may be converted and expanded. To -5 to 0 volts. In order to convert between the two signal ranges, a transducer is needed to convert the 0 to 2 volt input signal to an output signal of -5 to 0 volts. Since this conversion is to convert the lower limit of the signal range of the input signal to the upper limit of the signal range of the output signal, it can be regarded as a operation of turning negative pressure.

Please refer to Fig. 1, which is a conventional converter 10 for achieving the purpose of turning negative pressure. In the prior art, if the input signal IN with a signal range of VSS to VPP is turned to a negative signal with an output signal OUT between the voltages VSSL and VSS, the conventional converter 10 must undergo three stages. In the rotary converter 10, the converter LS1, the inverter INV0 and the other converter LS2 respectively perform the three-stage conversion, wherein the voltage is applied to the voltage VPP to VSSH. The LS1 performs the first re-pressure, and converts the input signal IN into the signal OUTa, so that the signal range of the signal OUTa is between the voltages VSSH and VPP; and the inverter INV0 operating at the voltage VSS to VSSH performs the second re-pressure, Converting the signal OUTa to the signal OUTb, and causing the signal range of the signal OUTb to fall between the voltages VSSH to VSS; finally, the voltage converter LS2 operating at the voltage VSS to VSSL performs the third re-transfer, converting the signal OUTb into The output signal OUT is such that the signal range of the output signal OUT can be between the voltages VSSL and VSS. In the above various conversions, for example, the voltages VSSL, VSSH, VSS, and VPP may be -5, -2, 0, and 2 volts, respectively, for turning the input signal IN of 0 to 2 volts into a negative voltage - 5 to 0 volt output signal OUT.

Although the lower limit of the signal range of the input signal IN corresponds to the upper limit of the signal range of the output signal OUT (both voltage VSS), in each of the above-mentioned re-conversions, when the converters LS1, LS2 and the inverter INV0 are each in the input signal range When converting between, you can only convert based on the upper or lower limit of the same signal range. That is to say, the converter LS1 is converted based on the upper limit of the signal range of the input signal, and the upper limit of the signal range of the input signal IN is equal to the upper limit of the signal range of the signal OUTa (ie, the voltage VPP). The inverter INV0 is converted based on the common lower limit of the input signal range, and the lower limit of the signal range of the signal OUTa is equal to the lower limit of the signal range of the signal OUTb. The converter LS2 is switched between the input and output signals with the same upper limit of the signal range. The upper limit of the signal range of the signal OUTb must be equal to the upper limit of the signal range of the output signal OUT. In combination with the above three-fold conversion, the conventional pressure converter 10 can achieve the purpose of turning negative pressure.

One of the reasons why the conventional converter 10 has to perform triple conversion in three circuits (the converters LS1, LS2 and the inverter INV0) is to ensure that the transistors in each circuit are not caused by excessive voltage differences. Crash damage. When the signal is converted to a larger signal range, the voltage difference between the electrodes of each transistor also becomes larger, which in turn affects the reliability of the transistor. However, under the triple conversion architecture, the total layout area of the converters LS1, LS2 and the inverter INV0 is also large, so that the overall layout area of the conventional converter 10 cannot be effectively reduced.

An object of the present invention is to provide a voltage converter for driving a source driving circuit of a liquid crystal panel for using a first output terminal and a second output according to a first input signal and a second input signal. The terminal outputs a corresponding first output signal and a second output signal respectively; the converter comprises: a first transistor having a first first end, a first second end and a first control The first first end is coupled to the first voltage, the first control end receives the first input signal, and the second transistor has a second first end, a second second end, and a second a second control end, the second first end is coupled to the first voltage, the second control end receives the second input signal, and a third transistor has a third first end, a third second The third control end is coupled to a predetermined bias voltage, and the third first end and the third second end are respectively coupled to the first second end and the first output end; a fourth transistor having a fourth first end, a fourth second end and a fourth control end, the fourth control The second first end and the fourth second end are respectively coupled to the second second end and the second output end; a fifth transistor having a fifth first The fifth output end is coupled to the second output end, the fifth control end is coupled to the second output end, the fifth first end is coupled to the first output end, and the fifth second end is coupled a second voltage; and a sixth transistor having a sixth first end, a sixth second end, and a sixth control end, wherein the sixth control end is coupled to the first output end, the first The first input signal and the second input end are coupled to the second voltage; wherein the first input signal and the second input signal are in the first voltage and a third Between the voltages, and the first output signal and the second output signal are between the second voltage and the first voltage, wherein the first voltage is between the third voltage and the second voltage The preset bias is set to be when the first input signal is the third voltage, the first output is turned on to the first voltage, when the When an input signal is the first voltage, the first output terminal is turned on to stop the first voltage.

Another object of the present invention is to provide a voltage converter for driving a source driving circuit of a liquid crystal panel, comprising: an input circuit having a first input end, a second input end, and a first connection end; a second input end receives a first input signal and a second input signal from the first input end and the second input end, respectively, and causes the signal of the first connection end and the signal of the second connection end to follow respectively The first input signal and the second input signal; a buffer circuit having a third connection end, a fourth connection end, a first output end and a second output end, the third connection end and the fourth output end The connecting end is respectively coupled to the first connecting end and the second connecting end, wherein when the voltage difference between the signal of the first input end and a predetermined bias voltage is greater than a total threshold voltage, the buffer circuit applies the The third connection end is electrically connected to the first output end; otherwise, the buffer circuit stops conducting between the third connection end and the first output end, and when the signal of the second input end is between the preset bias voltage The voltage difference is greater than the total current limit The buffer circuit turns on the fourth connection end to the second output end; otherwise, the buffer circuit stops conducting between the fourth connection end and the second output end; and an output circuit is coupled to The first output end and the second output end determine whether to turn the second output end to a predetermined voltage according to the signal of the first output end, and determine whether to output the first output according to the signal of the second output end. The terminal is turned on to the preset voltage.

The detailed description of the present invention and the accompanying drawings are to be understood by the accompanying claims,

Referring to Figure 2, an embodiment 20 of the present invention is illustrated. The input signal IN is inverted by the inverter INV (operating between the voltages VPP and VSS) into the input signal INB, and the signal range of the signals IN and INB is between the voltages VSS and VPP; and the converter 20 of the present invention is used. According to the input signals IN and INB, the corresponding output signals OUT and OUTB are respectively outputted at the nodes N3 and N4, and the signal range of the output signals OUT and OUTB is transferred between the voltages VSSL and VSS. The magnitude of the voltage VSS may be between the voltages VPP and VSSL, that is, the voltage VSSL<VSS<VPP. The converter 20 operates between the voltage VSS and VSSL, and is provided with transistors MN1, MN2, MP1, MP2, MN3 and MN4; the gate of each transistor can be regarded as a control terminal, and the drain and the source are the other two. end. The transistors MN1 and MN2 may be a pair of matched n-channel MOS transistors, and the gates of the two may be regarded as two input ends of the converter 20 for receiving input signals IN and INB, respectively. The voltage is coupled to the VSS, and the source is coupled to the nodes N1 and N2, respectively. The transistors MP1 and MP2 may be a pair of matched p-channel MOS transistors, the sources of which are respectively coupled to the nodes N1 and N2, the gates of the gates are coupled to the bias voltage VB, and the drains are respectively coupled. Connect nodes N3 and N4. The nodes N3 and N4 are the two output ends of the converter 20, and output two output signals OUT and OUTB, respectively. The transistors MN3 and MN4 may be a pair of matched n-channel MOS transistors, the drains of which are respectively coupled to nodes N3 and N4, the sources are commonly coupled to the voltage VSSL, and the gates of the transistors MN3 and MN4 The poles are coupled to nodes N4 and N3, respectively.

As can be seen from Fig. 2, the voltage difference (IN-V1) between the input signal IN and the voltage V1 (that is, the voltage of the node N1) corresponds to the gate-to-source voltage difference VGSN1 of the transistor MN1; by the transistor MN1 The working principle shows that when the voltage difference VGSN1 is greater than the threshold voltage VTHN1 of the transistor MN1, the transistor MN1 can be turned on. In addition, the voltage difference (V1-VB) between the voltage V1 and the bias voltage VB corresponds to the source-gate voltage difference |VGSP1| of the transistor MP1, when the voltage difference |VGSP1| is greater than the threshold voltage of the transistor MP1 |VTHP1|, transistor MP1 can be turned on. It can be seen that in the architecture formed by the series connection of the transistors MN1 and MP1, the voltage difference (IN-VB) between the input signal IN and the bias voltage VB is equal to the voltage difference (VGSN1+|VGSP1|), when the voltage difference is When (VGSN1+|VGSP1|) is greater than the total threshold voltage (VTHN1+|VTHP1|) of the transistors MN1 and MP1, the transistors MN1 and MP1 can turn on the node N3 to the voltage VSS. On the other hand, if the voltage difference (VGSN1+|VGSP1|) is smaller than the total threshold voltage (VTHN1+|VTHP1|) of the transistors MN1 and MP1, the node N3 is not turned on to the voltage VSS. Symmetrically, for the threshold voltages VTHN2 and |VTHP2| of the transistors MN2 and MP2, if the voltage difference between the input signal INB and the bias voltage VB is greater than the total threshold voltage (VTHN2+|VTHP2|), the transistors MN2 and MP2 Node N4 is turned on to voltage VSS, otherwise node N4 is not turned on to voltage VSS.

According to the characteristics of the transistor MN1/MN2 and MP1/MP2 (such as the threshold voltage), the voltage value of the bias voltage VB is designed to control whether the nodes N3 and N4 can be turned on to the voltage according to the voltages of the input signals IN and INB, respectively. VSS. In order to realize the voltage conversion function of the present invention, the bias voltage VB is set such that the node N3 (N4) is turned on to the voltage VSS when the input signal IN (INB) is equivalent to the voltage VPP, and when the input signal IN (INB) is the voltage. At VSS, the node N3 (N4) is stopped from being turned on to the voltage VSS.

The operation of the converter 20 of the present invention is described below. When the input signals IN and INB are voltage VPP and voltage VSS, respectively, the transistors MN1 and MP1 are turned on, and then the node N3 is turned on to the voltage VSS, so that the signal size of the output signal OUT is equivalent to the voltage VSS; The crystals MN2 and MP2 are not turned on, but the voltage VSS of the node N3 turns on the transistor MN4, and the voltage of the node N4 is pulled down to the voltage VSSL, so that the output signal OUTB becomes the voltage VSSL. In this way, it is also possible to output the voltages VSS and VSSL output signals OUT and OUTB in response to the input signals IN and INB of the voltages VPP and VSS, thereby realizing the function of turning negative voltage. Wherein, in the series architecture of the transistor MN1 and the transistor MP1, the input signal IN is in phase with the output signal OUT, that is, when the voltage of the input signal IN is the upper limit of the signal range of the input signal, the voltage of the output signal OUT also arrives. The upper limit of the signal range of the output signal; when the voltage of the input signal IN is the lower limit of the signal range of the input signal, the voltage of the output signal OUT also reaches the lower limit of the signal range of the output signal. Similarly, in the series architecture of the transistors MN2 and MP2, the input signal INB and the output signal OUTB are also in phase.

The above is the operation of the converter 20 when the input signals IN/INB are voltages VPP/VSS, respectively. When the input signal IN/INB is the voltage VSS/VPP, the operation of the converter 20 can be inferred according to the principle of symmetry: the transistors MN2 and MP2 will be turned on, so that the output signal OUTB of the node N4 is the voltage VSS; the transistor MN1 It is not conductive with MP1, and the output signal OUT of the node N3 is moved to the voltage VSSL by the turned-on transistor MN3.

For example, if the converter 20 of the present invention is used to convert an input signal IN/INB of 0 to 2 volts into an output signal OUT/OUTB of -5 to 0 volts (that is, VSSL, VSS, and VPP are equal to -5, 0, respectively. With 2 volts, and the threshold voltages VTHN1 and VTHN2 of the transistors MN1 and MN2 are 0.5 volts, and the threshold voltages |VTHP1| and |VTHP2| of the transistors MP1 and MP2 are 0.7 volts, the bias voltage VB can be set at - About 1 volt. In this case, when the input signal IN(INB) is 2 volts, the voltage difference between the input signal IN(INB) and the bias voltage VB is 2-(-1)=3 volts, which is larger than the transistors MN1 and MP1 (MN2 and The total threshold voltage of MP2) (0.5 + 0.7) = 1.2 volts, so that node N3 (N4) can be turned on to a voltage VSS of 0 volts. Conversely, if the input signal IN (INB) is 0 volts, the voltage difference between the input signal IN (INB) and the bias voltage VB is 0-(-1) = 1 volt, which is smaller than that of the transistors MN1 and MP1 (MN2 and MP2). The total threshold voltage is 1.2 volts, so that the output signal OUT (OUTB) of the node N3 (N4) is not turned on to the voltage VSS, but is turned on to the voltage VSSL of -5 volts.

As can be seen from the above discussion, the transistors MP1 and MP2 can function as buffer transistors, and the gates of the two are coupled to the bias voltage VB as if a variable resistor is connected in series in the circuit. For example, in the series architecture of transistors MN1, MP1 to MN3, when the voltage difference (VGSN1+|VGSP1|) is smaller than the total threshold voltage of the transistors MN1 and MP1 (VTHN1+|VTHP1|), the transistor MP1 is as infinitely impedance Large resistance; conversely, when the voltage difference (VGSN1+|VGSP1|) is greater than the total threshold voltage of the transistors MN1 and MP1 (VTHN1+|VTHP1|), the transistor MP1 changes from a large resistance to a small resistance, and its effect is Resistive damper. Symmetrically, in the series arrangement of transistors MN2, MP2 to MN4, the function of transistor MP2 can be inferred from the function of transistor MP1.

When considering the reliability of the transistor to prevent the transistor from collapsing, the gate-to-source voltage difference of a transistor is usually considered |VGS|, gate-to-drain voltage difference |VGD|, drain and source voltage Poor|VDS|, source and bulk voltage difference |VSB|, and the voltage difference between the drain and the body |VDB|. For example, in a typical application of the converter 20, the above voltage differences |VGS|, |VGD|, |VDS|, |VSB| and | of the respective transistors MN1, MN2, MP1, MP2, MN3, and MN4 VDB| is less than 5 volts. If the present invention is used to convert the input signal IN/INB of 0 to 2 volts into an output signal OUT/OUTB of -5 to 0 volts (that is, the voltages VSSL, VSS, and VPP are equal to -5, 0, respectively). 2 volts, under the circuit architecture of the present invention, the voltage differences of each of the transistors MN1, MN2, MP1, MP2, MN3 and MN4 |VGS|, |VGD|, |VDS|, |VSB| and |VDB| Will be less than 5 volts without affecting the reliability of the transistor. Since the body terminals (not shown) of the transistors MN1 and MN2 can be coupled to the voltage VSSL, the gate-to-body voltage difference |VGB| of the transistor MN1 (MN2) may reach 7 volts. However, the voltage difference that can be tolerated between the gate and the body is inherently large and does not affect the reliability of the transistor MN1/MN2.

Equivalently, the converter 20 of the present invention is formed by an input circuit, a buffer circuit and an output circuit. In the embodiment of FIG. 2, the input circuit is formed by transistors MN1 and MN2, the gates of the transistors MN1 and MN2 are two input ends, and the nodes N1 and N2 can be regarded as two terminals, and the input circuit is respectively received by the two inputs. The signals IN and INB are input, and the signals of the nodes N1 and N2 follow the input signals IN and INB, respectively. The buffer circuit is formed by transistors MP1 and MP2, nodes N1 and N2 are two connection ends, and nodes N3 and N4 are two output terminals. Wherein, when the voltage difference between the signal IN of the input terminal and the bias voltage VB is greater than the total threshold voltage of the transistors MN1 and MP1, the buffer circuit can conduct the node N1 to the node N3; otherwise, the buffer circuit stops at the nodes N1 and N3. Symmetrically, when the voltage difference between the signal INB and the bias voltage VB of the other input terminal is greater than the total threshold voltage of the transistors MN2 and MP2, the buffer circuit will conduct the node N2 to the node N4, and vice versa, the buffer circuit Stopping is conducted between node N2 and node N4. The output circuit is formed by the transistors MN3 and MN4, which can determine whether to turn on the node N4 to the voltage VSSL according to the signal of the node N3, and determine whether to turn on the node N3 to the voltage VSSL according to the signal of the node N4.

Referring to Figure 3, illustrated is another embodiment 30 of the present invention. The input signal IN is inverted by the inverter INV (operating between the voltage VSS and VSSL) into the input signal INB, and the signal range of the input signal IN/INB is the voltage VSSL to VSS; and the converter 30 of the present invention receives the input signal IN and INB respectively output corresponding output signals OUT and OUTB at nodes N3 and N4, and convert the signal ranges of output signals OUT and OUTB into voltages VSS to VPPH. The voltage VSS may be between the voltages VPPH and VSSL such that the voltage VSSL<VSS<VPPH; for example, the voltages VSSL, VSS, and VPPH may be 0, 2, and 7 volts, respectively. The converter 30 operates between the voltages VPPH and VSS, and is provided with transistors MP1, MP2, MN1, MN2, MP3 and MP4; the gate of each transistor can be regarded as a control terminal, and the drain and source are the other two. end. Similar to the circuit architecture of the converter 20, in the transducer 30, the transistors MP1 and MP3 (MP2 and MP4) are the same channel type of transistors, and the transistors MN1 and MP1 (MN2 and MP2) are different channel types. The transistor. The transistors MP1 and MP2 may be a pair of matched p-channel MOS transistors, and the gates of the two may be regarded as the two input ends of the converter 30, respectively receiving the input signals IN and INB, and the drain electrodes are coupled. The voltage VSS and the source are coupled to nodes N1 and N2, respectively. The transistors MN1 and MN2 may be a pair of matched n-channel MOS transistors, the sources of which are respectively coupled to the nodes N1 and N2, the gates of the gates are coupled to the bias voltage VB, and the drains are respectively coupled. Nodes N3 and N4 are connected to form two output terminals of the voltage converter 30, and two output signals OUT and OUTB are respectively output. The transistors MP3 and MP4 can be a pair of matched p-channel MOS transistors. The drains of the two are respectively coupled to nodes N3 and N4, the sources are commonly coupled to the voltage VPPH, and the gates of the transistors MP3 and MP4. The poles are coupled to nodes N4 and N3, respectively.

The operation of the pressure converter 30 can be summarized as follows. When the input signals IN and INB are voltage VSS and VSSL, respectively, the voltage difference between the bias voltage VB and the input signal IN is smaller than the total threshold voltage of the transistors MN1 and MP1, and the transistors MN1 and MP1 are not turned on; and the bias voltage VB and The voltage difference between the input signals INB is greater than the total threshold voltage of the transistors MN2 and MP2, and the node N4 is turned on to the voltage VSS, so that the output signal OUTB is equal to the voltage VSS. The voltage of the node N4 is connected to turn on the transistor MP3, and the node N3 is turned on to the voltage VPPH, so that the output signal OUT is equal to the voltage VPPH.

In summary, compared with the prior art, the converter of the present invention can realize the operation of turning negative pressure by using six transistors, so that the total layout area of the converter can be effectively reduced.

In the above, although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention, and various modifications and refinements can be made without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

The components included in the diagram of this case are listed as follows:

10, 20, 30, LS1, LS2. . . Converter

MP1-MP4, MN1-MN4. . . Transistor

OUTa, OUTb. . . Signal

INV, INV0. . . inverter

VPP, VSS, VSSH, VSSL, VPPH, V1-V2. . . Voltage

IN, INB. . . Input signal

OUT, OUTB. . . Output signal

N1-N4, Nc. . . node

VB. . . bias

This case can be obtained through a more in-depth understanding of the following diagrams and descriptions:

Figure 1 illustrates a conventional converter.

Figure 2 illustrates an embodiment of the converter of the present invention.

Figure 3 illustrates another embodiment of the converter of the present invention.

20. . . Converter

MP1-MP2, MN1-MN4. . . Transistor

VPP, VSS, VSSL, V1-V2. . . Voltage

IN, INB. . . Input signal

OUT, OUTB. . . Output signal

N1-N4, Nc. . . node

INV. . . inverter

VB. . . bias

Claims (12)

A voltage converter for driving a source driving circuit of a liquid crystal panel for outputting a corresponding first by a first output end and a second output end according to a first input signal and a second input signal An output signal and a second output signal, the converter includes: a first transistor having a first first end, a first second end, and a first control end, the first first end The first control terminal receives the first input signal, and the second control terminal has a second first end, a second second end, and a second control end, the second The first end is coupled to the first voltage, the second control end receives the second input signal, and a third transistor has a third first end, a third second end, and a third control end. The third control end is coupled to a predetermined bias, the third first end and the third second end are respectively coupled to the first second end and the first output end; a fourth transistor having a fourth first end, a fourth second end, and a fourth control end, the fourth control end is coupled to the preset bias, the first The first end and the fourth second end are respectively coupled to the second second end and the second output end; a fifth transistor having a fifth first end, a fifth second end, and a first a fifth control end, the fifth control end is coupled to the second output end, the fifth first end is coupled to the first output end, the fifth second end is coupled to a second voltage, and a sixth transistor The sixth output end is coupled to the first output end, and the sixth first end is coupled to the second output end. The sixth input terminal is coupled to the second voltage, wherein the first input signal and the second input signal are between the first voltage and a third voltage, and the first output signal and the The second output signal is between the second voltage and the first voltage, wherein the first voltage is between the third voltage and the second voltage, and the preset bias is set to be When the first input signal is the third voltage, the first output end is turned on to the first voltage, and when the first input signal is the first When pressed, the first output terminal is turned on to stop the first voltage. The converter of claim 1, wherein the first transistor is matched with the second transistor, the third transistor is matched with the fourth transistor, and the fifth transistor and the sixth transistor are And matching, and the first transistor and the fifth transistor system are of the same channel type of the transistor, and the first transistor and the third transistor system are different channel type transistors. The pressure converter of claim 1, wherein the first transistor, the second transistor, the fifth transistor, and the sixth transistor system are n-channel MOS transistors, and the first The tri-crystal and the fourth electro-crystal system are p-channel MOS transistors, wherein the third voltage is greater than the first voltage, and the first voltage is greater than the second voltage. The pressure converter of claim 1, wherein the first transistor, the second transistor, the fifth transistor, and the sixth transistor system are p-channel MOS transistors, and the The tri-crystal and the fourth electro-crystal system are n-channel MOS transistors, wherein the second voltage is greater than the first voltage, and the first voltage is greater than the third voltage. A voltage converter, which is suitable for driving a source driving circuit of a liquid crystal panel, comprising: an input circuit having a first input end, a second input end, a first connecting end and a second connecting end, The first input end and the second input end respectively receive a first input signal and a second input signal, and the signal of the first connection end and the signal of the second connection end respectively follow the first input signal and the first a first input signal; a buffer circuit having a third connection end, a fourth connection end, a first output end and a second output end, the third connection end and the fourth connection end respectively coupled to the first a connecting end and the second connecting end, wherein when the voltage difference between the signal of the first input end and a predetermined bias voltage is greater than a total threshold voltage, the buffer circuit turns on the third connecting end to the first The output terminal, otherwise, the buffer circuit stops conducting between the third connection end and the first output end, and when the voltage difference between the signal of the second input end and the preset bias voltage is greater than the total threshold voltage The buffer circuit will be the first The connection end is electrically connected to the second output end; otherwise, the buffer circuit stops conducting between the fourth connection end and the second output end; and an output circuit coupled to the first output end and the second output end The terminal determines whether to turn the second output terminal to a predetermined voltage according to the signal of the first output end, and determines whether to turn the first output end to the preset voltage according to the signal of the second output end. The oscillating device of claim 5, wherein the input circuit comprises: a first transistor having a first first end, a first second end and a first control end, the first The control end is coupled to the first input end, the first a first end coupled to the first voltage, the first second end coupled to the first connection end, and a second transistor having a second first end, a second second end, and a second The second control end is coupled to the second input end, the second first end is coupled to the first voltage, and the second second end is coupled to the second connection end. The variator of claim 6, wherein the snubber circuit comprises: a third transistor having a third first end, a third second end and a third control end, the third The first end is coupled to the third connection end, the third control end is coupled to the predetermined bias voltage, the third second end is coupled to the first output end, and a fourth transistor having a fourth a first end, a fourth second end, and a fourth control end, the fourth first end is coupled to the fourth connection end, the fourth control end is coupled to the preset bias, the fourth second end The second output is coupled to the second output. The transducer of claim 7, wherein the output circuit comprises: a fifth transistor having a fifth first end, a fifth second end and a fifth control end, the fifth The control end is coupled to the second output end, the fifth first end is coupled to the first output end, the fifth second end is coupled to the preset voltage, and a sixth transistor having a sixth The sixth output end is coupled to the first output end, the sixth first end is coupled to the second output end, and the sixth second end is coupled to the second output end. Connect to the preset Pressure. The converter of claim 8, wherein the first transistor is matched with the second transistor, the third transistor is matched with the fourth transistor, the fifth transistor and the sixth transistor Matching, and the first transistor and the fifth transistor system are transistors of the same channel type, and the first transistor and the third transistor system are different channel type transistors. The converter of claim 8, wherein the signal of the first input signal and the second input signal is between a first voltage and a second voltage, the first output signal and the second output The signal of the signal ranges between the preset voltage and the first voltage, wherein the first voltage is between the preset voltage and the second voltage. The pressure converter of claim 8, wherein the first transistor, the second transistor, the fifth transistor, and the sixth transistor system are n-channel MOS transistors, and the first The tri-crystal and the fourth electro-crystal system are p-channel MOS transistors, wherein the second voltage is greater than the first voltage, and the first voltage is greater than the predetermined voltage. The pressure converter of claim 8, wherein the first transistor, the second transistor, the fifth transistor, and the sixth transistor system are p-channel MOS transistors, and the first The tri-crystal and the fourth electro-crystal system are n-channel MOS transistors, wherein the predetermined voltage is greater than the first voltage, and the first voltage is greater than the second voltage.