TWI395002B - Display panel and signal transmission method thereof - Google Patents

Description

Display panel and signal transmission method thereof

The present invention relates to a flat display technology, and more particularly to a power trace and a signal transmission method between a plurality of gate drive wafers disposed directly on a glass substrate of a liquid crystal display panel.

With the evolution of optoelectronics and semiconductor technology, it has also driven the development of flat panel displays. Among many flat panel displays, liquid crystal displays (LCDs) have high space utilization efficiency, low power consumption, no radiation, and low Superior characteristics such as electromagnetic interference have become the mainstream of the market.

In recent years, in order to effectively control the manufacturing cost of a liquid crystal display, some panel manufacturers have adopted a chip-on-glass (COG) process, and directly connected a plurality of gate drive chips. It is disposed on one side of a glass substrate of a panel, thereby suppressing the manufacturing cost of the liquid crystal display.

FIG. 1 is a schematic diagram showing a layout of a plurality of gate drive wafers 101a to 101n disposed directly on a glass substrate of a liquid crystal display panel 100. Referring to FIG. 1, each of the gate driving chips 101a-101n has a plurality of power receiving pads (ie, black squares in FIG. 1) for receiving a plurality of sets of system voltages generated by a control board ( For example: gate drive turn-on voltage V _GH , gate drive turn-off voltage V _GL and logic operating voltage V _DDA, etc., and controlled by the control chip on the control board (generally the timing controller), and then sequentially display The pixels of each scan line within unit 103.

In general, the number of the gate driving chips 101a to 101n disposed on the glass substrate of the liquid crystal display panel 100 increases as the resolution of the liquid crystal display panel 100 increases, and each group of system voltages is driven at the gate. The traces between the wafers 101a to 101n are all in series. Thus also also because, at the moment the switch liquid crystal display, an excessive inrush current (inrush current) is likely to receive will flow into the gate driver power supply voltage V _GH turn receiving pad P _GH, resulting in weld power receiver Pad P _GH burned. As a result, not only can the gate driving chips 101a-101n fail to open the pixels of each scanning line in the display unit 103, but also the display unit 103 can not display the image screen for viewing by the user.

In view of the above, the present invention provides a display panel directly disposed with a plurality of gate driving chips on a glass substrate, and the power receiving pads of each of the gate driving chips are not formed by the display at the moment of switching on and off. Excessive inrush current burned.

The invention further provides a signal transmission method between a plurality of gate driving chips disposed directly on a glass substrate of a display panel, thereby reducing the probability that the power receiving pad of each gate driving chip is burnt in an instant of the display switching machine .

The present invention provides a display panel including a substrate and at least one first and second driving wafers. The first and second driving wafers are directly disposed on one side of the substrate, and the first driving wafer has at least a first power receiving pad, first and second auxiliary pads, and a first auxiliary trace. and The second driver wafer has at least a second power receiving pad. Wherein the first power receiving pad and the first auxiliary pad are used to receive a system voltage at the same time, and the first auxiliary pad is further passed through the first auxiliary trace A second auxiliary pad is coupled together to transfer the system voltage from the second auxiliary pad to the second power receiving pad.

In an embodiment of the invention, the display panel of the present invention further includes a third driving chip, and has at least a third power receiving pad. Accordingly, the first driving wafer further has third and fourth auxiliary pads and a second auxiliary wiring, and the second driving wafer further has fifth and sixth auxiliary pads and a third auxiliary wiring. The third auxiliary pad is configured to receive the system voltage, and the third auxiliary pad is connected to the fourth auxiliary pad through the second auxiliary trace to The system voltage is transmitted to the fifth auxiliary pad. In addition, the fifth auxiliary pad is also electrically connected to the sixth auxiliary pad through the third auxiliary trace to transmit the system voltage to the third power receiving pad. .

The present invention also provides a display panel including a substrate, at least one first and second driving wafers, and a first trace. The first and second driving wafers are directly disposed on one side of the substrate, and the first driving wafer has at least a first power receiving pad and a first auxiliary pad, and the second driving wafer has at least The second power source receives the pad. The first trace is disposed on the substrate. Wherein the first power receiving pad and the first auxiliary pad are used to receive a system voltage at the same time, and the first auxiliary pad is further passed through the first trace Second power receiving pad electrical Connecting to transfer the system voltage to the second power receiving pad.

In an embodiment of the invention, the display panel further includes a third driving chip and a second trace, and the third driving wafer has at least a third power receiving pad. Accordingly, the first driving wafer further has a second auxiliary pad. The second trace is disposed on the substrate. The second auxiliary pad is configured to receive the system voltage, and the second auxiliary pad is connected to the third power receiving pad through the second wire to The system voltage is transmitted to the third power receiving pad.

The present invention further provides a signal transmission method, which is suitable for a display panel, the display panel includes a substrate and at least one first and a second driving wafer, and the first and the second driving wafers are directly disposed in the One side of the substrate, and the first driving wafer has at least a first power receiving pad and a first auxiliary pad, and the second driving chip has at least a second power receiving pad. The signal transmission method includes the following steps. First, a system voltage is simultaneously supplied to the first power receiving pad and the first auxiliary pad. The system voltage is then transferred from the first auxiliary pad to the second power receiving pad.

The liquid crystal display panel provided by the present invention mainly utilizes an auxiliary bonding pad and an auxiliary trace in each gate driving chip to transmit a gate driving turn-on voltage (V _GH ) and a gate. a combination of at least one of a pole drive turn-off voltage (V _GL ) and a logic operating voltage (V _DDA ) or a combination of the three, such that any of these system voltages appear in parallel between the gate drive wafers form. As a result, at the moment when the liquid crystal display is turned on and off, an excessive inrush current does not cause any of the power supply receiving pads of the gate driving chip to be burnt.

The above features and advantages of the present invention will be more apparent from the following description.

The present invention is mainly for the purpose of effectively suppressing the possibility of burning of the power receiving pad of any gate driving chip disposed directly on the glass substrate of the liquid crystal display panel at the moment of switching on and off the liquid crystal display, and the following The description of the technical features of the present invention and the functions to be achieved will be described in detail to provide a description of those skilled in the relevant art.

FIG. 2 is a schematic diagram showing the system architecture of a liquid crystal display 200 according to an embodiment of the invention. Referring to FIG. 2, a liquid crystal display (LCD) 200 includes a liquid crystal display panel (LCD panel) 201, a control board 203, a flexible printed circuit board (FPC) 205, and a backlight for providing A backlight module 207 used in the liquid crystal display panel 201.

In the present embodiment, the liquid crystal display panel 201 includes a plurality of gate driving chips. (In this embodiment, three are described as an example, but the invention is not limited thereto, and the number is determined according to the resolution of the liquid crystal display panel 201. The degree and the number of channels of the single gate drive chip are determined to be 201a to 201c and the display unit 201d. The gate driving chips 201a to 201c are directly disposed on one side of the glass substrate of the liquid crystal display panel 201 through a die-on-glass (COG) process. Display unit 201d There are a plurality of scan lines (not shown) and data lines (not shown), and the scan lines and the data lines are alternately defined with each other to define a plurality of pixels.

The control board 203 includes at least a power supply unit 203a and a timing controller (T-con) 203b. In this embodiment, the control board 203 is coupled to the liquid crystal display panel 201 through a flexible printed circuit board 205 made by a chip-on-film (COF) process, and the flexible printed circuit board 205 is coupled. A source driver 205a is further disposed.

In general, the timing controller 203b controls the operation of the gate driving chips 201a-201c and the source driver 205a through the flexible printed circuit board 205, so as to match the backlight module 207, causing the display unit 201d to display the image image to the user. Watch. However, the techniques of the present invention are not the focus of the present invention, and such techniques are well known to those of ordinary skill in the art, and therefore will not be further described herein, and the following will be directed to the present invention. Describe the technical focus to make a detailed description.

The power supply unit 203a is configured to provide a plurality of sets of system voltages required by the liquid crystal display panel 201, such as a common voltage V _COM , a gate drive turn-on voltage V _GH , a gate drive turn-off voltage V _GL , and a logic operating voltage. V _DDA , and each set of system voltages V _COM , V _GH , V _GL , V _DDA is conducted to the liquid crystal display panel 201 through the flexible printed circuit board 205.

It can be seen from the prior art that the traces of each set of system voltages between the gate drive wafers are in series. Also, at the moment when the liquid crystal display is turned on and off, an excessive inrush current may flow into each power receiving pad, especially a power receiving pad for receiving the gate driving turn-on voltage (V _GH ). Since the gate driving turn-on voltage is usually much larger than the receiving voltage of other power receiving pads, excessive inrush current will cause it to burn, which will cause the gate driving chip to fail to open each scan in the display unit 201d smoothly. The pixel corresponding to the line.

Herein, in order to effectively solve the disadvantages described in the prior art, FIG. 3A is a schematic enlarged view showing the arrangement of the gate driving chips 201a to 201c of FIG. 2 disposed on the glass substrate of the liquid crystal display panel 101. Referring to FIG. 2 and FIG. 3 together, the gate driving chip 201a has at least power receiving pads P _GH1 , P _GL1 , P _GL2 , P _DDA1 , P _DDA2 , auxiliary bonding pads DP ₁ ~ DP ₄ , and Auxiliary traces DT ₁ , DT ₂ . The gate driving chip 201b has at least power supply receiving pads P _GH2 , P _GL3 , P _GL4 , P _DDA3 , P _DDA4 , auxiliary pads DP ₅ , DP ₆ , and auxiliary traces DT ₃ . The gate driving chip 201c has at least power supply receiving pads P _GH3 , P _GL5 , P _GL6 , P _DDA5 , and P _DDA6 . The term "auxiliary pad" as used herein generally refers to a pad that does not use a driver chip to transmit signals under normal operation. In some cases, an auxiliary pad may not be provided on the driver wafer, and the purpose of the auxiliary pad is set. Usually, it is reserved for special operations or specific purposes. For example, the present invention utilizes the setting of the auxiliary pad to solve the problem that a large amount of current is poured so that the power receiving pad may be burnt; sometimes the auxiliary pad can also be called Dummy bonding pads, the number of auxiliary pads and their layout can be designed to drive the chip supplier according to actual needs.

What is worth mentioning here is the process based on the liquid crystal display panel 101. In consideration of factors, the structure of each of the gate driving chips 201a to 201c should be the same, but only the power receiving pads, the auxiliary pads, and the auxiliary wirings related to the present invention will be described in FIG. 3 as follows.

In this embodiment, the power receiving pad P _{GL1 is configured} to receive the gate driving turn-off voltage V _GL , and the traces between the gate driving chips 201a to 201c are connected in series to the power receiving pad P _{GL6 .} That is, the traces of the gate drive turn-off voltage V _GL between the gate drive wafers 20la to 201c are in series. Similarly, the power receiving pad P _{DDA1 is} used to receive the logic operating voltage V _DDA , and the traces between the gate driving chips 201 a - _{201 c are} also connected in series to the power receiving pad P _DDA6 , that is, logic operation The traces of the voltage V _DDA between the gate drive chips 201a to 201c are also in series.

The power receiving pad P _GH1 and the auxiliary pads DP ₁ and DP _{3 are} used to receive the gate driving turn-on voltage V _GH at the same time, and the auxiliary pad DP ₁ is connected to the auxiliary pad DP ₂ through the auxiliary trace DT ₁ . Together, the gate drive turn-on voltage V _{GH is} transmitted to the power supply receiving pad P _GH2 through the trace GT ₁ on the glass substrate. In addition, the auxiliary pad DP _{3 is} also connected to the auxiliary pad DP ₄ through the auxiliary trace DT ₂ , and transmits the gate driving turn-on voltage V _GH to the auxiliary pad DP through the trace GT ₂ on the glass substrate. ₅ . In addition, the auxiliary pad DP _{5 is} also connected to the auxiliary pad DP ₆ through the auxiliary trace DT ₃ , and transmits the gate driving turn-on voltage V _GH to the power receiving solder through the trace GT ₃ on the glass substrate. Pad P _GH3 . The auxiliary traces DT ₁ and DT ₂ are exemplified by the internal trace of the gate drive wafer 201a, and the auxiliary trace DT ₃ is exemplified by the internal trace of the gate drive wafer 201b.

Since it is known that the power receiving pads for receiving the gate drive turn-on voltage (V _GH ) are the most likely to burn out at the instant of switching the liquid crystal display, especially the first gate wafer (such as the gate) The power receiving pad for receiving the inter-polar driving turn-on voltage in the driving chip 201a) is most likely to be burned. Therefore, the gate driving turn-on voltage V _{GH of the} present embodiment is routed between the gate driving chips 201a to 201c. Instead, the layout form of the parallel arrangement, that is, the gate drive turn-on voltage V _GH is simultaneously shunted to the power supply receiving pad P _GH1 , the auxiliary pad DP ₁ and the auxiliary pad DP ₃ when being transferred to the driving wafer 201a. Also, at the moment when the liquid crystal display device 100 is turned on and off, the intensity of the inrush current actually felt by the power receiving pad P _GH1 is reduced to the power receiving pad P _GH disclosed in the prior art FIG. It is about one-third of the same, and the intensity of the inrush current felt by each power receiving pad P _GH1 ~ P _GH3 at the moment when the liquid crystal display 100 is _turned on and off will be nearly the same. As a result, the present embodiment will greatly reduce the possibility/probability of burning of the power receiving pads P _GH1 P P _GH3 at the instant of switching on and off of the liquid crystal display 100.

In addition, another layout may be further proposed according to the layout structure between the gate driving chips 201a to 201c. FIG. 3B is another layout of the gate driving chips 201a to 201c of FIG. 2 disposed on the glass substrate of the liquid crystal display panel 101. Zoom in on the schematic. In this embodiment, the power receiving pad P _GH1 and the auxiliary pads DP ₁ and DP ₃ are electrically coupled to each other through a conductive element CL (for example, a conductive line), wherein the conductive element CL may be on a glass substrate. A trace can be electrically coupled to the power receiving pad P _GH1 and the auxiliary pads DP ₁ and DP ₃ through an anisotropic conductive paste (ACF) or the like. Thereby, the gate driving turn-on voltage V _GH can be simultaneously transferred to the power receiving pad P _GH1 and the auxiliary pads DP ₁ , DP ₃ , so that the gate driving turn-on voltage V _{GH is} not concentrated only on the power receiving soldering at the same time. Pad P _GH1 , which in turn reduces the effects of inrush current.

In addition, the vacant soldering DP ₁ and DP ₃ do not necessarily transmit the gate driving turn-on voltage V _GH via the auxiliary traces DT ₁ and DT ₂ inside the driving chip 201a, and FIG. 3C shows the gate of FIG. Further layout of the pole drive wafers 201a to 201c disposed on the glass substrate of the liquid crystal display panel 101 is shown. Referring to FIG. 3A and FIG. 3C , the biggest difference is that in this embodiment, the gate drive is transmitted by the traces BT ₁ and BT ₂ on the glass substrate without passing through the auxiliary traces driving the inside of the wafer. Turn on the voltage V _GH . In the present embodiment, the auxiliary pads DP ₁ and DP ₃ are connected to the power receiving pads P _GH2 and P _GH3 via the traces BT ₁ and BT2 on the glass substrate, respectively. The power receiving pad P _GH1 and the auxiliary pads DP ₁ and DP _{3 are} used to receive the gate driving turn-on voltage V _GH at the same time. Preferably, in another embodiment, the power receiving pad P _GH1 and the auxiliary pad DP ₁ and DP ₃ can be electrically connected to each other through a design of a conductive element CL (for example, a conductive line on a glass substrate) as shown in FIG. 3B to simultaneously receive the gate drive turn-on voltage V _GH . In the embodiment, the auxiliary pad DP _{1 is} connected to the power receiving pad P _GH2 through the wire BT _{1 for} transmitting the gate driving turn-on voltage V _GH to the power receiving pad P _GH2 . The auxiliary pad DP _{3 is} connected to the power receiving pad P _GH3 through the wire BT _{2 for} transmitting the gate driving turn-on voltage V _GH to the power receiving pad P _GH3 . Thereby, the gate driving turn-on voltage V _GH can also be made in parallel between the gate driving chips 201a to 201c. In the embodiment of FIG. 3C, since the gate driving turn-on voltage V _GH is transmitted through the traces BT ₁ and BT ₂ on the glass substrate, the auxiliary pads DP ₂ and DP _{4 are} omitted from the embodiment of FIG. 3A. The design of DP ₅ and DP ₆ , however, in other embodiments, the auxiliary pads DP ₂ , DP ₄ , DP ₅ and DP ₆ can also be retained, so that the number of pads on the upper and lower sides of the wafer will be more symmetrical. When the driving wafer is adhered to the glass substrate, the pressing stress is evenly distributed; or the driving wafer is relatively easy to manufacture on the manufacturing process.

However, according to the spirit of the present invention, it is not limited to the embodiments of the above embodiments, that is, the traces of the gate driving turn-on voltage V _GH between the gate driving chips 201a to 201c may be in parallel form. The traces between the gate drive turn-off voltage V _GL and the logic operating voltage V _DDA between the gate drive chips 201a - 201c may be in a series connection. In other embodiments of the present invention, the user can determine the gate driving turn-on voltage V _GH , the gate drive turn-off voltage V _{GL ,} and the logic operating voltage V _DDA according to actual requirements, and each of the gate driving chips 201a Whether the traces between ~201c are to be in parallel form, and the embodiments of the variants are also one of the categories to be protected by the present invention.

So far, according to the disclosure of the above embodiments, it is mainly used to drive each of the gates to drive excess auxiliary pads, auxiliary traces, and traces on the glass between the wafers (or only on the glass substrate). The trace without using the auxiliary trace) to transmit at least one of the gate drive turn-on voltage (V _GH ), the gate drive turn-off voltage (V _GL ), and the logic operating voltage (V _DDA ) or a combination of the three In order to make any of these system voltages appear in parallel in all traces between the gate drive wafers. In other words, the design concept of the present invention is directed to any of the auxiliary pads, the auxiliary auxiliary traces, and the traces on the glass between the driving wafers when entering the first driving wafer for any system voltage having a large current (or The shunting action is performed only by using the layout on the glass substrate instead of the auxiliary traces, thereby reducing the inrush current effect of the system voltage instantaneously concentrated on a single receiving pad, and reducing the burning of the receiving pad. opportunity. Therefore, as long as it is based on such a concept, it is possible to achieve the possibility of suppressing the burning of the power receiving pad of any gate driving chip directly disposed on the glass substrate of the liquid crystal display panel at the moment of switching on or off the liquid crystal display. The solution is within the scope of the invention to be protected.

Furthermore, in accordance with the disclosure of the embodiments of FIGS. 3A and 3C, the following will summarize the signal transmission method of the present invention to those of ordinary skill in the art. FIG. 4A is a flow chart of a signal transmission method according to an embodiment of the invention. Referring to FIG. 4A, the signal transmission method of this embodiment is suitable for a display panel (for example, a liquid crystal display panel). The display panel includes a substrate and at least one first and second driving wafers, and the first and second driving wafers are directly disposed on a side of the substrate, and preferably, the first and second driving The wafer is adhered to the substrate by an anisotropic conductive paste (ACF) and a non-conductive paste (NCF). In addition, the first driving chip has at least a first power receiving pad, a first auxiliary pad and a first auxiliary trace, and the second driving chip has at least a second power receiving pad.

Therefore, the signal transmission method of this embodiment includes the following steps: First, as described in step S501, simultaneously providing a system voltage to the first power source Receiving the pad and the first auxiliary pad. Then, as described in step S502, the system voltage is transmitted from the first power receiving pad to the second power receiving pad, wherein the system voltage is passed from the first auxiliary wire by the first auxiliary wire Transmitting the pad to the second auxiliary pad, and connecting the second auxiliary pad and the second power receiving pad by a glass trace between the first and second driving wafers to transmit the system voltage to The second power source receives the pad.

In addition, when the display panel further includes a third driving chip and has at least a third power receiving pad, the first driving chip further has third and fourth auxiliary pads and a second auxiliary trace. And the second driving chip further has fifth and sixth auxiliary pads and a third auxiliary wiring, so that the signal transmission method of the embodiment further includes providing the system voltage to the first power receiving welding While the pad and the first auxiliary pad are simultaneously provided with the system voltage to the third auxiliary pad; then, transferring the system voltage from the third auxiliary pad to the third power receiving pad, wherein the system voltage is The transmission path is sequentially transmitted from the third auxiliary pad, the second auxiliary trace, the fourth auxiliary pad, the fifth auxiliary pad, and the third auxiliary trace to the sixth auxiliary pad, and the second and the second A glass trace between the three driver wafers connects the sixth auxiliary pad and the third power receiving pad such that the system voltage is finally transmitted to the third power receiving pad.

FIG. 4B is a flowchart of a signal transmission method according to another embodiment of the present invention. Referring to FIG. 4B, another signal transmission method of this embodiment is suitable for another display panel (also, for example, a liquid crystal display panel). The display panel includes a substrate and at least one first and second driving wafers, and the first and second driving wafers are directly disposed on one side of the substrate. In addition, the first The driving chip has at least a first power receiving pad and a first auxiliary pad, and the second driving chip has at least a second power receiving pad.

In the above, another signal transmission method of this embodiment includes the following steps: First, as described in step S510, a system voltage is simultaneously supplied to the first power receiving pad and the first auxiliary pad. Then, as described in step S511, the system voltage is transmitted from the first auxiliary pad to the second power receiving pad, wherein the system voltage is transmitted through a trace on the substrate to be transmitted from the first auxiliary pad. The second power source receives the pad.

In addition, when the other display panel further includes a third driving chip and has at least a third power receiving pad, the first driving chip further has a third auxiliary pad, so that the embodiment The signal transmission method further includes providing the system voltage to the first power receiving pad and the first auxiliary pad while providing the system voltage to the third auxiliary pad; and then, the system voltage is The third auxiliary pad is transferred to the third voltage source pad, wherein the system voltage is transmitted through the other trace on the substrate to be transferred from the third auxiliary pad to the third power receiving pad .

In this embodiment, the substrate is a glass substrate, and the first, second, and third driving wafers are gate driver chips. In addition, the system voltage includes at least one of a gate drive turn-on voltage (V _GH ), a gate drive turn-off voltage (V _GL ), and a logic operating voltage (V _DDA ).

In summary, the liquid crystal display panel provided by the present invention mainly utilizes each of the gates to drive excess auxiliary pads, auxiliary traces, and traces on the glass between the wafers (or only on the glass substrate). The trace without using the auxiliary trace) to transmit at least one of the gate drive turn-on voltage (V _GH ), the gate drive turn-off voltage (V _GL ), and the logic operating voltage (V _DDA ) or a combination of the three Therefore, any of these system voltages appear in parallel in all traces between the gate drive wafers. As a result, at the moment when the liquid crystal display is turned on and off, an excessive inrush current does not cause any of the power supply receiving pads of the gate driving chip to be burnt.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100, 201‧‧‧ LCD panel

101a~101n, 201a~201c‧‧‧ gate drive chip

103, 201d‧‧‧ display unit

V _GH ‧‧‧ gate drive turn-on voltage

V _GL ‧‧‧ gate drive turn-off voltage

V _DDA ‧‧‧Logical operating voltage

V _COM ‧‧‧shared voltage

200‧‧‧LCD display

203‧‧‧Control panel

203a‧‧‧Power supply unit

203b‧‧‧Sequence Controller

205‧‧‧Soft printed circuit board

205a‧‧‧Source Driver

207‧‧‧Backlight module

P _GH1 ~P _GH3 , P _GL1 ~P _GL6 , P _DDA1 ~P _{DDA6 ‧‧‧Power} receiving pad

BT ₁ , BT ₂ , GT ₁ , GT ₂ , GT ₃ ‧‧‧ Traces on the substrate

CL‧‧‧conductive components

DP ₁ ~DP ₆ ‧‧‧Auxiliary pads

DT ₁ ~ DT ₃ ‧‧‧Auxiliary trace

S501, S502, S510, S511‧‧‧ steps of the flow chart of the signal transmission method of the embodiment of the present invention

FIG. 1 is a schematic diagram showing the layout of a plurality of gate drive wafers disposed directly on a glass substrate of a panel.

FIG. 2 is a schematic diagram showing the system architecture of a liquid crystal display according to an embodiment of the invention.

FIG. 3A is a schematic enlarged plan view showing the layout of the gate driving wafer of FIG. 2 disposed on the glass substrate of the liquid crystal display panel.

FIG. 3B is an enlarged schematic view showing another layout of the gate driving wafer of FIG. 2 disposed on the glass substrate of the liquid crystal display panel.

FIG. 3C is a schematic enlarged view showing still another layout of the gate driving wafer of FIG. 2 disposed on the glass substrate of the liquid crystal display panel.

FIG. 4A is a flowchart of a signal transmission method according to an embodiment of the present invention; Figure.

FIG. 4B is a flowchart of a signal transmission method according to another embodiment of the present invention.

201a~201c‧‧‧Gate drive chip

V _GH ‧‧‧ gate drive turn-on voltage

V _GL ‧‧‧ gate drive turn-off voltage

V _DDA ‧‧‧Logical operating voltage

P _GH1 ~P _GH3 , P _GL1 ~P _GL6 , P _DDA1 ~P _{DDA6 ‧‧‧Power} receiving pad

DP ₁ ~DP ₆ ‧‧‧Auxiliary pads

DT ₁ ~ DT ₃ ‧‧‧Auxiliary trace

GT ₁ , GT ₂ , GT ₃ ‧‧‧ Traces on the substrate

Claims (32)

A display panel includes: a substrate; and at least one first and a second driving wafer, wherein the first and second driving wafers are directly disposed on a side of the substrate, and the first driving wafer has at least one a first power receiving pad, a first and a second auxiliary pad, and a first auxiliary trace, and the second driving chip has at least a second power receiving pad; wherein the first power receiving pad And the first auxiliary bonding pad is configured to receive a system voltage at the same time, and the first auxiliary bonding pad is electrically connected to the second auxiliary bonding pad through the first auxiliary bonding wire to The second auxiliary pad is transferred to the second power receiving pad. The display panel of claim 1, further comprising a first trace disposed on the substrate for electrically connecting the second auxiliary pad and the second power receiving pad. The display panel of claim 1, further comprising a first conductive component electrically connected to the first power receiving pad and the first auxiliary pad. The display panel of claim 3, wherein the first conductive element is a trace on the substrate. The display panel of claim 1, further comprising a third driving chip having at least a third power receiving pad. The display panel of claim 5, wherein the first driving chip further has a third and a fourth auxiliary bonding pad and a second auxiliary Assisting the trace, and the second driver chip further has a fifth and a sixth auxiliary pad and a third auxiliary trace; wherein the third auxiliary pad is for receiving the system voltage, and the third auxiliary solder The pad is electrically connected to the fourth auxiliary pad through the second auxiliary trace to transmit the system voltage to the fifth auxiliary pad; and the fifth auxiliary pad passes through the third auxiliary trace The sixth auxiliary pad is electrically connected to transmit the system voltage to the third power receiving pad. The display panel of claim 6, further comprising: a second trace disposed on the substrate for electrically connecting the fourth auxiliary pad and the fifth auxiliary pad; and a third The wiring is disposed on the substrate for electrically connecting the sixth auxiliary bonding pad and the third power receiving pad. The display panel of claim 6, further comprising a second conductive component electrically connected to the first power receiving pad, the first auxiliary pad and the third auxiliary pad. The display panel of claim 8, wherein the second conductive element is a trace on the substrate. The display panel of claim 1, wherein the substrate is a glass substrate. The display panel of claim 5, wherein the first, the second and the third driving wafer are a gate driving wafer. The display panel of claim 1, wherein the system voltage comprises a gate drive turn-on voltage and a gate drive turn-off voltage. And at least one of a logic operating voltage. The display panel of claim 1, wherein the display panel is a liquid crystal display panel. The display panel of claim 1, wherein the first and second driving wafers are directly bonded to the substrate by an isotropic conductive paste or a non-conductive paste. A display panel includes: a substrate; at least one first and a second driving wafer, wherein the first and second driving wafers are directly disposed on a side of the substrate, and the first driving wafer has at least one a power receiving pad, a first auxiliary pad, and the second driving chip has at least a second power receiving pad; and a first trace is disposed on the substrate; wherein the first power receiving pad The first auxiliary pad is used to receive a system voltage at the same time, and the first auxiliary pad is electrically connected to the second power receiving pad through the first wire. The display panel of claim 15 further comprising a first conductive component electrically connected to the first power receiving pad and the first auxiliary pad. The display panel of claim 16, wherein the first conductive element is a trace on the substrate. The display panel of claim 15, further comprising a third driving chip having at least a third power receiving pad. Such as the display panel described in claim 18, wherein The display panel further includes a second trace disposed on the substrate, and the first driver die further includes a second auxiliary pad; wherein the second auxiliary pad passes through the second trace and the third power The receiving pad is electrically connected. The display panel of claim 19, further comprising a second conductive component electrically connected to the first power receiving pad, the first auxiliary pad and the second auxiliary pad. The display panel of claim 20, wherein the second conductive element is a trace on the substrate. The display panel of claim 15, wherein the first and second driving wafers are directly bonded to the substrate by an isotropic conductive paste or a non-conductive paste. A signal transmission method is suitable for a display panel. The display panel includes a substrate and at least one first and a second driving chip. The first and second driving chips are directly disposed on a side of the substrate. And the first driving chip has at least one first power receiving pad, a first auxiliary pad, and the second driving chip has at least one second power receiving pad. The signal transmitting method comprises the following steps: simultaneously providing one System voltage to the first power receiving pad and the first auxiliary pad; and transmitting the system voltage from the first auxiliary pad to the second power receiving pad. The signal transmission method of claim 23, wherein the first driving chip further comprises a second auxiliary pad and a first auxiliary walking a line, and the system voltage is transmitted from the first auxiliary pad to the second auxiliary pad by the first auxiliary trace, and then transmitted from the second auxiliary pad to the second power receiving pad. The signal transmission method of claim 24, wherein the display panel further comprises a first trace disposed on the substrate, and the system voltage is transmitted through the first trace from the second auxiliary pad Transfer to the second power receiving pad. The signal transmission method of claim 23, wherein the display panel further comprises a first trace disposed on the substrate, and the system voltage is transmitted through the first trace from the first auxiliary pad Transfer to the second power receiving pad. The signal transmission method of claim 24, wherein the display panel further comprises a third driving chip having at least a third power receiving pad, and the first driving chip further has a third auxiliary bonding pad. The signal transmission method of claim 27, further comprising the steps of: providing the system voltage to the third auxiliary pad; transmitting the system voltage from the third auxiliary pad to the third power receiving and soldering pad. The signal transmission method of claim 28, wherein the first driving chip further has a fourth auxiliary bonding pad and a second auxiliary wiring electrically connected to the third and fourth auxiliary pads. The second driving chip further has a fifth and a sixth auxiliary pad and a third auxiliary line. Electrically connecting the fifth and sixth auxiliary pads, wherein the transmission path of the system voltage is sequentially followed by the third auxiliary pad, the second auxiliary trace, the fourth auxiliary pad, the fifth auxiliary pad, and the third The third auxiliary trace and the sixth auxiliary pad are transferred to the third power receiving pad. The signal transmission method of claim 26, wherein the display panel further comprises a third driving chip having at least a third power receiving pad, and the first driving chip further has a second auxiliary bonding a pad, and the method further comprises: providing the system voltage to the second auxiliary pad; transferring the system voltage from the second auxiliary pad to the third power receiving pad. The signal transmission method of claim 30, wherein the display panel further comprises a second trace disposed on the substrate, and the system voltage is transmitted through the second trace from the second auxiliary pad Transfer to the third power receiving pad. The signal transmission method of claim 23, wherein the system voltage comprises at least one of a gate drive turn-on voltage, a gate drive turn-off voltage, and a logic operating voltage.