CN116991006A - Display panel, display device and driving method of display panel - Google Patents
Display panel, display device and driving method of display panel Download PDFInfo
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- CN116991006A CN116991006A CN202310957166.1A CN202310957166A CN116991006A CN 116991006 A CN116991006 A CN 116991006A CN 202310957166 A CN202310957166 A CN 202310957166A CN 116991006 A CN116991006 A CN 116991006A
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- 238000000034 method Methods 0.000 title claims abstract description 12
- 239000002184 metal Substances 0.000 claims description 67
- 230000003287 optical effect Effects 0.000 claims description 10
- 238000010586 diagram Methods 0.000 description 12
- 230000008054 signal transmission Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000004069 differentiation Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13452—Conductors connecting driver circuitry and terminals of panels
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0202—Addressing of scan or signal lines
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Computer Hardware Design (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Mathematical Physics (AREA)
- Optics & Photonics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Theoretical Computer Science (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The application discloses a display panel, a display device and a driving method of the display panel, wherein the display panel comprises a flip chip film, a plurality of fan-out wires and a plurality of data wires; the data lines comprise a plurality of connection data lines and a plurality of output data lines, and the connection data lines comprise first connection data lines and second connection data lines; the flip chip film comprises a plurality of signal pins, one end of each fan-out wiring is correspondingly connected with the corresponding signal pins, the other end of each fan-out wiring is respectively connected with a first connection data line and a second connection data line, and each first connection data line and each second connection data line are respectively connected with one output data line through a layer-switching switch; the transfer switch controls the first connection data line or the second connection data line to be connected or disconnected with the output data line under the control of the control signal. So as to reduce the number of the flip chip films without reducing the number of the data lines and the charging efficiency.
Description
Technical Field
The present application relates to the field of display, and more particularly, to a display panel, a display device, and a driving method of the display panel.
Background
Along with the refinement of the manufacturing process and the yield, the cost price of the electronic product is continuously reduced, but the flip-chip film is still a high-price material, so that the cost can be better saved by reducing the use amount of the flip-chip film.
Currently, DRD technology is used to save the flip chip film; the principle is that two rows of pixels are controlled simultaneously by one data line, and the display of the picture is completed by changing the time sequence. However, in the DRD technology, since one data line is required to charge two rows of pixels at the same time, the charging rate is reduced.
Therefore, how to reduce the number of the flip chip films without reducing the number of the data lines or the charging efficiency, and to save the cost, is a urgent problem to be solved.
Disclosure of Invention
The application discloses a display panel, a display device and a driving method of the display panel, and aims to reduce the number of flip chip films and save cost under the conditions of not reducing the number of data lines and not reducing charging efficiency.
The application discloses a display panel which comprises a flip chip film, a plurality of fan-out wires and a plurality of data wires, wherein the display panel is further divided into a display area and a non-display area, the non-display area is divided into a fan-out area, and the fan-out wires are positioned in the fan-out area; the data lines comprise a plurality of connection data lines and a plurality of output data lines, the connection data lines are positioned in the non-display area, the output data lines are positioned in the display area, and the connection data lines comprise a first connection data line and a second connection data line; the flip chip film comprises a plurality of signal pins, one end of each fan-out wire is correspondingly connected with the corresponding signal pins, the other end of each fan-out wire is respectively connected with the first connection data line and the second connection data line, and each first connection data line and each second connection data line are respectively connected with one output data line through a transfer switch; the transfer switch controls the first connection data line or the second connection data line to be connected or disconnected with the output data line under the control of a control signal.
Optionally, the display panel further includes: the flip chip film comprises a first metal wire and a second metal wire, wherein the flip chip film comprises a first control pin, a second control pin and a plurality of signal pins, one end of the first metal wire is connected with the first control pin, the other end of the first metal wire spans the fan-out area, one end of the second metal wire is connected with the second control pin, and the other end of the second metal wire spans the fan-out area; the transfer layer switch comprises a first transfer layer switch and a second transfer layer switch, the first metal wire is connected with the control end of the first transfer layer switch, and the second metal wire is connected with the control end of the second transfer layer switch.
Optionally, the display panel further includes a printed circuit board, and the printed circuit board is provided with a timing control chip, and the timing control chip is connected with the control end of the layer switch through the first control pin and the second control pin, the first metal wire and the second metal wire; when the time sequence control chip outputs a first control signal, the first connection data line is conducted with the output data line, and when the time sequence control chip outputs a second control signal, the second connection data line is conducted with the output data line.
Optionally, the first metal trace includes a first connection trace and a second connection trace, one end of the first connection trace is connected with the first control pin, the other end is bent towards a side far away from the signal pin, and is connected with one end of the second connection trace, and the second connection trace spans the fan-out area; the second metal wire comprises a third connecting wire and a fourth connecting wire, one end of the third connecting wire is connected with the second control pin, the other end of the third connecting wire is bent towards one side far away from the signal pin and is connected with one end of the fourth connecting wire, and the fourth connecting wire spans the fan-out area; the second connecting wire is parallel to the fourth connecting wire.
Optionally, the first control pin and the second control pin are both located outside the signal pin and on the same side.
Optionally, the first control pin is located at an outer side of the signal pin and located at a different side of the flip chip film.
Optionally, a first layer rotating hole and a second layer rotating hole are respectively arranged at one end, close to the display area, of each fan-out wiring, and the fan-out wiring is connected with the first connection data line and the second connection data line through the first layer rotating hole and the second layer rotating hole respectively.
The application also discloses a display device which comprises the optical module, and the display panel is arranged on one side of the light emitting surface of the optical module.
The application also discloses a driving method of the display panel, which is used for driving the display panel, and comprises the following steps: the control signal controls the first connection data line to be conducted with the output data line and controls the second connection data line to be disconnected with the output data line in a first preset time; the signal pins output data signals to the output data lines conducted with the first connection data lines so as to control the corresponding pixel units to be charged; the control signal controls the second connection data line to be conducted with the output data line in a second preset time, and controls the second connection data line to be disconnected with the output data line at the same time; the signal pin outputs a data signal to the output data line which is conducted with the second connection data line so as to control the corresponding pixel unit to be charged.
Optionally, the first preset time is a first half frame of a frame scanning time, and the second preset time is a second half frame of the frame scanning time.
According to the application, at least two connection data lines are simultaneously connected to one fan-out wiring, each connection data line is respectively connected with an output data line positioned in a display area through a layer-switching switch, a design of converting a single fan-out wiring into multiple data lines is formed, and the connection data line and the output data line are controlled to be turned on or off through the layer-switching switch so as to realize signal transmission, so that the design that the corresponding data line of the fan-out wiring in the traditional logic is 1:1 is changed, and the design can be adjusted to be 1:2;1:3 or even 1:4, the number of fan-out wires can be effectively reduced; the fan-out wiring is branched by utilizing the connection of a plurality of data lines and the fan-out wiring through a layer-switching switch, so that the single property of line conveying is ensured; the number of the flip chip films is determined by the number of the fan-out wires, so that the number of the fan-out wires is reduced, the required number of the flip chip films can be reduced, but the number of the data wires is not reduced, and therefore the data wires in the display area can not be influenced to charge the pixel electrodes, and the number of the flip chip films can be reduced under the conditions that the number of the data wires is not reduced and the charging efficiency is not reduced.
Drawings
The accompanying drawings, which are included to provide a further understanding of embodiments of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the present application, from which other drawings can be obtained without inventive effort for a person skilled in the art, in which:
FIG. 1 is a schematic diagram of a first embodiment of a display panel according to the present application;
FIG. 2 is a schematic diagram of a first metal line transfer switch in a first embodiment of a display panel according to the present application;
FIG. 3 is a schematic diagram of a second metal line transfer switch in a first embodiment of a display panel according to the present application;
FIG. 4 is a schematic diagram of a second embodiment of a display panel according to the present application;
FIG. 5 is a schematic diagram of a display device according to an embodiment of the application;
fig. 6 is a step diagram of an embodiment of a driving method of a display panel according to the present application.
10, a display device; 100. a display panel; 200. an optical module; 110. a printed circuit board; 111. a timing control chip; 120. a display area; 130. a non-display area; 140. a fan-out area; 141. a fan-out wiring; 142. a first transfer hole; 143. a second lamination hole; 150. a data line; 151. connecting a data line; 152. a first connection data line; 153. a second connection data line; 154. an output data line; 160. a layer-turning switch; 161. a first switch; 162. a second transfer switch; 170. a flip chip film; 171. a first control pin; 172. a second control pin; 173. signal pins; 180. a first metal wire; 181. a first connection trace; 182. a second connecting trace; 190. a second metal wire; 191. a third connecting trace; 192. and a fourth connecting wire.
Detailed Description
The present application will be described in detail below with reference to the drawings and the optional embodiments, and it should be noted that, without conflict, new embodiments may be formed by any combination of the embodiments or technical features described below.
Fig. 1 is a schematic diagram of a first embodiment of a display panel according to the present application, and fig. 2 is a schematic diagram of a first metal line up-conversion switch in the first embodiment of the display panel according to the present application; FIG. 3 is a schematic diagram of a second metal line transfer switch in a first embodiment of a display panel according to the present application; as shown in fig. 1 to 3, the present application discloses a display panel 100, which includes a flip chip film 170, a plurality of fan-out wires 141 and a plurality of data wires 150, wherein the display panel 100 is further divided into a display area 120 and a non-display area 130, the non-display area 130 is divided into a fan-out area 140, and the fan-out wires 141 are located in the fan-out area 140; the data line 150 includes a plurality of connection data lines 151 and a plurality of output data lines 154, the plurality of connection data lines 151 are located in the non-display region 130, the plurality of output data lines 154 are located in the display region 120, and the connection data lines 151 include a first connection data line 152 and a second connection data line 153; the flip chip film 170 includes a plurality of signal pins 173, one end of a plurality of fan-out wires 141 is connected to the plurality of signal pins 173 in a one-to-one correspondence manner, the other end of each fan-out wire 141 is connected to the first connection data line 152 and the second connection data line 153, and each of the first connection data line 152 and the second connection data line 153 is connected to one of the output data lines 154 through the transfer switch 160; the transfer switch 160 controls the first connection data line 152 or the second connection data line 153 to be turned on or off with the output data line 154 under the control of the control signal.
According to the application, at least two connection data lines 151 are simultaneously connected to one fan-out wiring 141, each connection data line 151 is respectively connected with one output data line 154 positioned in a display area 120 through a layer-switching switch 160, so that a design that a single fan-out wiring 141 changes into a plurality of data lines 150 is formed, and the connection data line 151 and the output data line 154 are controlled to be turned on or off through the layer-switching switch 160, so that signal differentiation output is realized, and the design that the fan-out wiring 141 corresponds to the data lines 150 in a 1:1 manner in the traditional logic is changed, and the design can be adjusted to be 1:2;1:3 or even 1:4, the number of the fan-out wires 141 can be effectively reduced; the fan-out wires 141 are branched by utilizing the connection of the plurality of data wires 150 and the fan-out wires 141 through the layer-switching switch 160, so that the single property of the wire conveying is ensured; since the number of the flip chip films 170 is determined by the number of the fan-out traces 141, reducing the number of the fan-out traces 141 can reduce the number of the flip chip films 170 required, but does not reduce the number of the data lines 150, so that the data lines 150 in the display area 120 are not affected to charge the pixel unit electrodes, and thus the number of the flip chip films 170 can be reduced without reducing the number of the data lines 150 or the charging efficiency.
As shown in fig. 1, the display panel 100 further includes: the flip chip film 170 includes a first control pin 171, a second control pin 172 and a plurality of signal pins 173, one end of the first metal wire 180 is connected to the first control pin 171, the other end spans the fan-out area 140, one end of the second metal wire 190 is connected to the second control pin 172, and the other end spans the fan-out area 140; the layer switch 160 includes a first layer switch 161 and a second layer switch 162, the first metal wire 180 is connected to the control terminal of the first layer switch 161, and the second metal wire 190 is connected to the control terminal of the second layer switch 162.
In the application, a first control pin 171 and a second control pin 172 are additionally added on the flip-chip film 170, the first control pin 171 and the second control pin 172 are respectively connected with a first metal wire 180 and a second metal wire 190, and control signals are respectively output by the first control pin 171 and the second control pin 172 on the flip-chip film 170 to respectively control a first transfer switch 161 connected with the first metal wire 180 and a second transfer switch 162 connected with the second metal wire 190, so as to realize the signal on or off of the output data wire 154.
Taking the resolution 3840×2160 of the display panel 100 as an example; the number of required output data lines 154 in the display area 120 is 11520, and according to the conventional design of the flip-chip film 170, a single flip-chip film 170 can drive the output data lines 154 into 1440 columns, i.e. 1440 signal pins 173 of each flip-chip film 170.
As shown in fig. 1, the first control pin 171 and the second control pin 172 are located outside the signal pin 173 and on the same side.
Taking the first flip-chip film 170 as an example, the two leftmost rows of pin lead gate lines bypass from the left side of the display area, and penetrate through the fan-out area 140 and the display area as a gate design of the inversion area. Of the remaining 1440 signal pins 173, each signal pin 173 is connected to two connection data lines 151, and the two connection data lines 151 penetrate downward, and when passing through the two transfer switches 160 of the first metal trace 180 and the second metal trace 190, the transfer switches 160 are connected to the output data lines 154 to transfer and shunt. The fan-out wires 141 are branched by utilizing the connection of the plurality of data wires 150 and the fan-out wires 141 through the layer-switching switch 160, so that the single property of the wire conveying is ensured; since the number of the flip chip films 170 is determined by the number of the fan-out traces 141, reducing the number of the fan-out traces 141 can reduce the number of the flip chip films 170 required, but does not reduce the number of the data lines 150, so that the data lines 150 in the display area 120 are not affected to charge the pixel unit electrodes, and thus the number of the flip chip films 170 can be reduced without reducing the number of the data lines 150 or the charging efficiency.
It should be noted that the number of the additional control pins on the flip-chip film 170 may be two or more, and according to the above principle, the more the plurality of control pins, the more the fan-out lines 141 can be formed, the more the number of the flip-chip film 170 can be saved.
In addition, since the number of the fan-out lines 141 is large, fig. 1 shows only a case where one fan-out line 141 is connected to the connection data line 151 and the output data line 154 through the layer-switching switch 160 for explanation; in the present application, only two metal wires, namely, the first metal wire 180 and the second metal wire 190 are actually adopted, so that the fan-out wires 141 can be respectively connected with the connection data wire 151 and the output data wire 154 by using the transfer switch 160 through the design, and the transfer switches 160 on the first metal wire 180 and the second metal wire 190 are controlled to be opened or closed together through the first metal wire 180 and the second metal wire 190; the aim of saving the number of the flip chip films 170 is better realized, meanwhile, the structure can be simplified, and the risk of contact short circuit caused by line staggering is avoided;
further, the display panel 100 further includes a printed circuit board 110, the printed circuit board 110 is provided with a timing control chip 111, and the timing control chip 111 is connected with the control end of the layer switch 160 through a first control pin 171 and a second control pin 172, and a first metal wire 180 and a second metal wire 190; when the timing control chip 111 outputs the first control signal, the first connection data line 152 is turned on with the output data line 154, and when the timing control chip 111 outputs the second control signal, the second connection data line 153 is turned on with the output data line 154.
Outputting control signals to a first control pin 171 and a second control pin 172 on the flip-chip film 170 through a timing control chip 111 on the printed circuit board 110, and outputting the first control signal and the second control signal with equal delays through the timing control chip 111; for example: when the timing control chip 111 outputs the first control signal, the transfer switch 160 between the first connection data line 152 and the output data line 154 is turned on, the transfer switch 160 between the second connection data line 153 and the output data line 154 is turned off, at this time, the output data line 154 turned on with the first connection data line 152 writes display data, and when the timing control chip 111 outputs the second control signal, the transfer switch 160 between the first connection data line 152 and the output data line 154 is turned off, the transfer switch 160 between the second connection data line 153 and the output data line 154 is turned on, at this time, the output data line 154 turned on with the second connection data line 153 writes display data, so that not only can the alternate writing of display data of the odd-numbered column output data line 154 and the even-numbered column output data line 154 be formed, the normal charging of the pixel units by the data line 150 is ensured, but also the voltages written on the odd-numbered column output data line 154 and the even-numbered column output data line 154 are equal, and the uniformity of the column brightness of the display panel 100 is ensured.
Further, the first metal trace 180 includes a first connection trace 181 and a second connection trace, one end of the first connection trace 181 is connected to the first control pin 171, the other end is bent toward a side far from the signal pin 173, and is connected to one end of the second connection trace, and the second connection trace spans the fan-out area 140; the second metal trace 190 includes a third connection trace 191 and a fourth connection trace 192, one end of the third connection trace 191 is connected to the second control pin 172, the other end is bent toward a side far from the signal pin 173, and is connected to one end of the fourth connection trace 192, and the fourth connection trace 192 spans the fan-out area 140; the second connection trace is parallel to the fourth connection trace 192.
The first metal wire 180 and the second metal wire 190 in the present application are both composed of two parts, and the first metal wire 180 and the second metal wire 190 are made to bypass from the left side of the display area through the connection wires of the two parts, and penetrate through the fan-out area 140 on the antenna side and the display area to be used as a gate design of the inversion area. Of the remaining 1440 signal pins 173, each signal pin 173 is connected to two connection data lines 151, and the two connection data lines 151 penetrate downward, and when passing through the two transfer switches 160 of the first metal trace 180 and the second metal trace 190, the transfer switches 160 are connected to the output data lines 154 to transfer and shunt. The fan-out wires 141 are branched by utilizing the connection of the plurality of data wires 150 and the fan-out wires 141 through the layer-switching switch 160, so that the single property of the wire conveying is ensured; since the number of the flip chip films 170 is determined by the number of the fan-out traces 141, reducing the number of the fan-out traces 141 can reduce the number of the flip chip films 170 required, but does not reduce the number of the data lines 150, so that the data lines 150 in the display area 120 are not affected to charge the pixel unit electrodes, and thus the number of the flip chip films 170 can be reduced without reducing the number of the data lines 150 or the charging efficiency.
And, the width, thickness and length of the first metal wire 180 and the second metal wire 190 are equal, and the first metal wire and the second metal wire are made of the same material, so that impedance is reduced, and stability of signal transmission is improved.
The fan-out wires 141 are respectively connected with the first connection data line 152 and the second connection data line 153 through the first layer rotating hole 142 and the second layer rotating hole 143.
According to the application, the first transfer layer hole 142 and the second transfer layer hole 143 are arranged on the connecting end of the fan-out wire 141, the fan-out wire 141 is respectively connected with the first connecting data wire 152 and the second connecting data wire by utilizing the first transfer layer hole 142 and the second transfer layer hole 143, so that at least two connecting data wires 151 are simultaneously connected on one fan-out wire 141 to realize signal transmission, and the design that the corresponding data wires 150 of the fan-out wire 141 in the traditional logic are 1:1 is changed, and the adjustment is 1:2; the number of the fan-out lines 141 can be effectively reduced.
Fig. 4 is a schematic diagram of a second embodiment of the display panel according to the present application, as shown in fig. 4, in which the embodiment shown in fig. 4 is based on the modification of fig. 1, and the first control pins 171 are located on the outer side of the signal pins 173 and on different sides of the flip chip film 170.
In this embodiment, the positions of the first control pin 171 and the second control pin 172 are adjusted, the first control pin 171 and the second control pin 172 are disposed on different sides of the flip-chip film 170, and after the first metal trace 180 and the second metal trace 190 are connected to the first control pin 171 and the second control pin 172, the first metal trace 180 and the second metal trace 190 respectively output control signals from different sides of the flip-chip film 170 toward the crossing fan-out area 140, and the first transfer switch 161 connected to the first metal trace 180 and the second transfer switch 162 connected to the second metal trace 190 are respectively controlled to realize signal on or off of the output data line 154 through the first control pin 171 and the second control pin 172 on the flip-chip film 170.
It should be noted that, since the plurality of signal pins 173 are sequentially arranged in rows, the outer side in the embodiment refers to the outer side in the arrangement direction of the plurality of signal pins 173, or is understood as the end of the flip chip film 170.
Fig. 5 is a schematic diagram of an embodiment of a display device according to the present application, as shown in fig. 5, the present application further discloses a display device 10, including an optical module 200, the display device 10 further includes the display panel 100, and the display panel 100 is disposed on one side of the light emitting surface of the optical module 200.
The display panel 100 does not emit light, and the optical module 200 is required to provide a light source for normal light emission for the display panel 100, and the optical module 200 in the present application may be a liquid crystal module or an OLED module, and the type of the optical module 200 is not particularly limited in the present application.
In order to save the cost of the display device 10, the application improves the display panel 100 in the display device 10, at least two connecting data lines 151 are simultaneously connected to one fan-out wiring 141, each connecting data line 151 is respectively connected with one output data line 154 positioned in the display area 120 through a layer switch 160, a design that a single fan-out wiring 141 changes into a plurality of data lines 150 is formed, and the connection or disconnection of the connecting data lines 151 and the output data lines 154 is controlled through the layer switch 160 so as to realize signal transmission, so that the use number of the fan-out wirings 141 can be effectively reduced; since the number of the flip chip films 170 is determined by the number of the fan-out traces 141, reducing the number of the fan-out traces 141 can reduce the number of the flip chip films 170 required, but does not reduce the number of the data lines 150, so that the data lines 150 in the display area 120 are not affected to charge the pixel unit electrodes, and thus the number of the flip chip films 170 can be reduced without reducing the number of the data lines 150 or the charging efficiency.
Fig. 6 is a step diagram of an embodiment of a driving method of a display panel according to the present application, and as shown in fig. 6, the present application also discloses a driving method of a display panel 100, for driving the display panel 100, where the driving method includes:
s1, in a first preset time, the control signal controls the first connection data line 152 to be conducted with the output data line 154, and controls the second connection data line 153 to be disconnected with the output data line 154; the signal pin 173 outputs a data signal to the output data line 154 connected to the first connection data line 152 to control the charging of the corresponding pixel unit;
s2, the control signal controls the second connection data line 153 to be conducted with the output data line 154 and controls the second connection data line 153 to be disconnected with the output data line 154 in a second preset time; the signal pin 173 outputs a data signal to the output data line 154 connected to the second connection data line 153 to control the charging of the corresponding pixel unit.
For example: when the timing control chip 111 outputs a control signal in a first preset time, the transfer switch 160 between the first connection data line 152 and the output data line 154 is turned on, the transfer switch 160 between the second connection data line 153 and the output data line 154 is turned off, at this time, the output data line 154 turned on with the first connection data line 152 is written with display data, the output data line 154 turned on with the first connection data is charged with corresponding pixel units, and when the timing control chip 111 outputs a control signal in a second preset time, the transfer switch 160 between the first connection data line 152 and the output data line 154 is turned off, at this time, the transfer switch 160 between the second connection data line 153 and the output data line 154 is turned on, at this time, the output data line 154 turned on with the second connection data line 153 is written with display data, the output data line 154 turned on with the second connection data is charged with corresponding pixel units, so that not only can the alternate writing of the display data of the odd-numbered column output data line 154 and the even-numbered column output data line 154 be formed, but also the normal charging of the pixel units by the data line 150 is ensured, the brightness of the display data line 100 of the even-numbered column output data line 154 is ensured to be consistent with the even-numbered column output data line 154.
The first preset time is the first half frame of one frame scanning time, and the second preset time is the second half frame of one frame scanning time.
Namely, in two connection data lines 151 sequentially connected to one fan-out line 141 and two output data lines 154 respectively connected to the two connection data lines 151 through a layer-switching switch 160, in the first half time of the first frame, the layer-switching switch 160 controls the first connection data line 151 and the output data line 154 connected to the first connection data line 151 to be turned on, and at this time, a signal passes; however, the second connection data line 151 and the output data line 154 connected to the second connection data line 151 are closed, so that no signal passes, and the first output data line 154 can be ensured to start working; in the second half of the first frame, the transfer switch 160 controls the second connection data line 151 and the output data line 154 connected to the second connection data line 151 to be turned on, and a signal passes through the transfer switch; however, the first connection data line 151 and the output data line 154 connected to the first connection data line 151 are closed, so that no signal passes through, and the first output data line 154 can be ensured to start to work, thereby ensuring the accuracy of the work of the second output data line 154.
It should be noted that, the inventive concept of the present application can form a very large number of embodiments, but the application documents are limited in space and cannot be listed one by one, so that on the premise of no conflict, the above-described embodiments or technical features can be arbitrarily combined to form new embodiments, and after the embodiments or technical features are combined, the original technical effects will be enhanced.
The above description of the application in connection with specific alternative embodiments is further detailed and it is not intended that the application be limited to the specific embodiments disclosed. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the application, and these should be considered to be within the scope of the application.
Claims (10)
1. The display panel comprises a flip chip film, a plurality of fan-out wires and a plurality of data wires, wherein the display panel is further divided into a display area and a non-display area, the non-display area is divided into a fan-out area, and the fan-out wires are positioned in the fan-out area;
the display device is characterized in that the data lines comprise a plurality of connection data lines and a plurality of output data lines, the connection data lines are positioned in the non-display area, the output data lines are positioned in the display area, and the connection data lines comprise a first connection data line and a second connection data line;
the flip chip film comprises a plurality of signal pins, one end of each fan-out wire is correspondingly connected with the corresponding signal pins, the other end of each fan-out wire is respectively connected with the first connection data line and the second connection data line, and each first connection data line and each second connection data line are respectively connected with one output data line through a transfer switch;
the transfer switch controls the first connection data line or the second connection data line to be connected or disconnected with the output data line under the control of a control signal.
2. The display panel of claim 1, wherein the display panel further comprises: the flip chip film comprises a first metal wire and a second metal wire, wherein the flip chip film comprises a first control pin, a second control pin and a plurality of signal pins, one end of the first metal wire is connected with the first control pin, the other end of the first metal wire spans the fan-out area, one end of the second metal wire is connected with the second control pin, and the other end of the second metal wire spans the fan-out area;
the transfer layer switch comprises a first transfer layer switch and a second transfer layer switch, the first metal wire is connected with the control end of the first transfer layer switch, and the second metal wire is connected with the control end of the second transfer layer switch.
3. The display panel of claim 2, further comprising a printed circuit board, wherein the printed circuit board is provided with a timing control chip, and the timing control chip is connected with the control end of the turn-layer switch through the first control pin and the second control pin, and through the first metal wire and the second metal wire;
when the time sequence control chip outputs a first control signal, the first connection data line is conducted with the output data line, and when the time sequence control chip outputs a second control signal, the second connection data line is conducted with the output data line.
4. The display panel of claim 2, wherein the first metal trace includes a first connection trace and a second connection trace, one end of the first connection trace being connected to the first control pin, the other end being bent toward a side away from the signal pin and being connected to one end of the second connection trace, the second connection trace crossing the fan-out region;
the second metal wire comprises a third connecting wire and a fourth connecting wire, one end of the third connecting wire is connected with the second control pin, the other end of the third connecting wire is bent towards one side far away from the signal pin and is connected with one end of the fourth connecting wire, and the fourth connecting wire spans the fan-out area; the second connecting wire is parallel to the fourth connecting wire.
5. The display panel of claim 2, wherein the first control pin and the second control pin are both located outside of the signal pin and on the same side.
6. The display panel of claim 2, wherein the first control pins are located outside the signal pins and on different sides of the flip chip film.
7. The display panel of claim 5, wherein each fan-out trace has a first transfer hole and a second transfer hole at an end thereof adjacent to the display area,
the fan-out wiring is connected with the first connection data line and the second connection data line through the first transfer hole and the second transfer hole respectively.
8. A display device comprising an optical module, wherein the display device further comprises a display panel according to any one of claims 1 to 7, the display panel being disposed on one side of a light-emitting surface of the optical module.
9. A driving method of a display panel for driving the display panel according to any one of claims 1 to 7, comprising:
the control signal controls the first connection data line to be conducted with the output data line and controls the second connection data line to be disconnected with the output data line in a first preset time;
the signal pins output data signals to the output data lines conducted with the first connection data lines so as to control the corresponding pixel units to be charged;
the control signal controls the second connection data line to be conducted with the output data line in a second preset time, and controls the second connection data line to be disconnected with the output data line at the same time;
the signal pin outputs a data signal to the output data line which is conducted with the second connection data line so as to control the corresponding pixel unit to be charged.
10. The driving method of a display panel according to claim 9, wherein the first preset time is a first half frame of a frame scan time, and the second preset time is a second half frame of the frame scan time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310957166.1A CN116991006A (en) | 2023-07-28 | 2023-07-28 | Display panel, display device and driving method of display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310957166.1A CN116991006A (en) | 2023-07-28 | 2023-07-28 | Display panel, display device and driving method of display panel |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116991006A true CN116991006A (en) | 2023-11-03 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310957166.1A Pending CN116991006A (en) | 2023-07-28 | 2023-07-28 | Display panel, display device and driving method of display panel |
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| Country | Link |
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| CN (1) | CN116991006A (en) |
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2023
- 2023-07-28 CN CN202310957166.1A patent/CN116991006A/en active Pending
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