TWI394375B - Unified dual-mode gsm/umts clock - Google Patents

Description

Unified dual mode GSM/UMTS clock

The present invention relates to a data machine, and more particularly to a unified dual system GSM (global system for mobile communication)/universal mobile telecommunication systems (UMTS) clock, and a unified double Mode GSM/UMTS clock transceiver.

In a conventional dual mode GSM/UMTS modem, two different time base recording times are employed, which require multiple clock and clock generation circuits. In addition, a clock-synchronous circuit across the clock domain must be installed on an application-specific integrated circuit (ASIC) in a dual-mode modem to share information between the two clock domains. Such additional circuitry creates delays in information transmission, causes additional power loss, increases die area, and can cause errors due to metastability.

Another way to maintain two simultaneous clocks is to change the operating frequency of the phase-locked loop (PLL)/voltage controlled oscillator (VCO) that obtains the clock. However, in this way, when switching between the two modes, the data machine needs to re-synchronize between the two modes.

The present invention relates to a unified dual mode GSM/UMTS clock, and a transceiver using the unified dual mode GSM/UMTS clock. A reference clock generates a reference clock signal, and a local oscillator (LO) generates an LO signal based on the reference clock signal. A frequency divider selectively generates a GSM clock signal or a UMTS clock signal by converting a frequency of the LO signal by a predetermined factor, and the GSM clock signal and the UMTS clock signal are according to the Shared reference clock signal is generated. The reference clock signal frequency can be a GSM base frequency or a UMTS base frequency such as 13 MHz, 15.36 MHz, 19.2 MHz, 26 MHz, or 38.4 MHz. An interpolator and/or a decimator can be used to match the frequency of the UMTS baseband signal and the UMTS clock signal, or to match the GSM baseband signal and the frequency of the GSM clock signal.

Features of the present invention can be integrated into an integrated circuit (IC) or can be placed on a circuit that includes a plurality of interconnected components.

Figure 1 shows a block diagram of a unified dual mode GSM/UMTS clock 100, which is configured in accordance with the present invention. The clock 100 includes a reference clock 102, a local oscillator (LO) 104, and a divider/multiplier 106. The reference clock 102 produces a reference clock signal 103 that serves as a reference signal for the local oscillator (LO) 104 to produce an LO signal 105. The LO signal 105 is then converted by the divider/multiplier 106 into a GSM clock signal 107 or a UMTS clock signal 108.

In accordance with the present invention, both the GSM clock signal 107 and the UMTS clock signal 108 are generated by a shared reference clock signal 103. The frequency of the shared reference clock signal 103 can be a GSM base frequency or a UMTS base frequency. For example, the reference clock signal 103 can have a frequency of 13 MHz, 15.36 MHz, 19.2 MHz, 26 MHz, 38.4. MHz, or an integer multiple or fraction of these frequencies. In accordance with the present invention, the manner in which the modem can be constructed can be simplified, and no additional circuitry is needed to help span the clock domain or resynchronize.

Figure 2 shows a block diagram of an embodiment of a transceiver 200 using a unified dual mode GSM/UMTS clock 201, which is configured in accordance with the present invention. It is to be noted that the configuration shown in FIG. 2 is merely an embodiment and is not intended to limit the invention, and any other configuration or value that is apparent to those skilled in the art can be used. The transceiver 200 includes a transmitter 260, a receiver 250, and a unified dual mode clock 201 that includes a reference clock 202, a local oscillator (LO) 204, and a plurality of frequency dividers. The frequency divider includes a first frequency divider 206 and a second frequency divider 206 for timing the ADC time in the receiver 250, and the second frequency divider is Used to time the DAC time in the transmitter 260. The frequency divider may further include a third frequency divider 210 of a GSM timing manager 212 and a fourth frequency divider 213 of a UMTS timing manager 218. The frequency divider may include additional frequency dividers 272, 274, and 276 if needed by other processors or modules.

The reference clock 202 generates a reference clock signal 203, which may be a GSM base frequency or a UMTS base frequency. Figure 2 illustrates the reference clock signal 203 as a GSM base frequency (i.e., 13 MHz), and for simplicity, the present invention will be described by way of example only. It should be noted, however, that the configuration and numerical description depicted in Figure 2 can be readily applied to the UMTS base frequency (like 19.2 MHz) as the reference clock signal frequency for those skilled in the art. The situation is modified.

The local oscillator (LO) 204 is preferably a VCO having a PLL and the local oscillator (LO) 204 produces an LO signal 205. In this embodiment, the local oscillator (LO) 204 generates the LO signal 205 at a frequency that is 24 times the reference clock signal 203, so in this embodiment, the output of the VCO is 312 MHz. The LO signal 205 is then divided by the frequency divider into a GSM clock signal, a UMTS clock signal, or any other clock signal.

The first frequency divider 206 and the second frequency divider 208 selectively divide the LO signal 205 into a GSM clock signal or a UMTS clock signal according to a control signal (not shown). For example, the first frequency divider 206 divides the LO signal 205 (312 MHz) into a UMTS clock signal by a factor of 40 such that it produces an output at 7.8 MHz and divides it into a GSM by a factor of 288. The clock signal causes it to produce an output at 1.0833 MHz. The second frequency divider 208 divides the LO signal 205 (312 MHz) into a UMTS clock signal by a factor of 20 such that it produces an output at 15.6 MHz and divides the LO signal into a GSM with a factor of 288. The pulse signal causes it to produce an output at 1.0833 MHz. Next, the UMTS clock signal and the GSM clock signal drive an analog-to-digital converter (ADC) 222 in the receiver 250, and a digital to analog converter (DAC) 232 in the transmitter 260, In order to perform reception and transmission processing separately.

The receiver 250 includes an ADC 222, an interpolator 224, a sampler 226, a sampler 228, and a receiver front end 230. The UMTS clock signal generated by the first frequency divider 206 or the ADC 222 clocked by the GSM clock signal digitizes a down converted received signal 221. For example, for UMTS data, the received signal 221 is digitized at a sampling frequency of 7.8 MHz, and the sample 223 is interpolated and sampled by the interpolator 224 and the sampler 226. The interpolator 224 interpolates the sample 223 by a factor of 64, and the sampler 226 samples the interpolated data 225 by a factor of 65, which produces a downconversion data 227 at 7.68 MHz. The sampler 228 then samples the down-converted data 227 by a factor of two (2) and further downconverts to 3.84 MHz, which is then forwarded to the receiver front end 230 for further processing. For GSM data, the received data 221 is digitized at a sampling frequency of 1.0833 MHz, and the sample 223 is sent to the receiver front end 230 for further processing. It must be noted that the sampling frequencies of 7.8 MHz and 1.0833 MHz are only an example, and it is obvious to those skilled in the art that any other sampling frequency or rate can be used, and various interpolation and sampling factors can be employed.

The transmitter 260 includes a root raised cosine (RRC) filter 240, 242, an interpolator 238, a sampler 236, a multiplexer 234, and a DAC 232. The UMTS data 244 (3.84 MHz) is preferably upconverted to 15.6 MHz, while the GSM data 246 (270.833 KHz) is preferably upconverted to 1.0833 MHz. The UMTS data 244 is processed by the RRC filter 240, which also performs an interpolation operation. For example, the interpolation can be a four (4) factor that will convert the UMTS data at 3.84 MHz to 15.36 MHz. Next, the over-conversion data 239 is converted by the RRC filter 240 and processed by the interpolator 238 and the sampler 236 to match the frequency. Since the second frequency divider 208 generates a UMTS clock signal at 15.6 MHz from a shared reference clock signal 203 having a frequency of 13 MHz, the DAC 232 is clocked at 15.6 MHz, so preferably the data is The rate (ie 15.36 MHz) is converted to this rate (ie 15.6 MHz). The interpolator 238 interpolates the data 239 by a factor of 65, and the sampler 236 samples the interpolated data 237 by a factor of 64, which produces a data output at 15.6 MHz.

The GSM baseband data 246 is also processed by the RRC filter 242, which also performs the interpolation action. For example, the interpolation can be a factor of four (4) that converts GSM data at 270.833 KHz to 10.833 MHz.

The upconverted UMTS data 235 and the upconverted GSM data 241 are multiplexed by a multiplexer 234 in accordance with a control signal 281 (UMTS/GSM). The multiplexer 234 selectively outputs one of the inputs 235, 241 according to the control signal 281, and the output of the multiplexer is then converted by the DAC 232 into an analog data.

The clock 201 can include a third frequency divider 210 to generate a clock signal for timing the GSM timing manager 212. In the embodiment illustrated in FIG. 2, the third frequency divider divides the LO signal 205 (312 MHz) by a factor of 288, which downconverts the LO signal 205 to 1.0833 MHz, the downconverted signal 211 It is then used to time the GSM timing manager 212.

The clock 201 can also include a fourth frequency divider 213 to generate a clock signal for timing the UMTS timing manager 218. For example, the fourth frequency divider 213 can include a rate matching unit 214 and a frequency divider 216 that absorbs one (1) pulse from the 64 pulses of the LO signal 205 and A factor two (2) divides it to produce an output at an average of 153.6 MHz. The frequency divider 216 then divides the output 215 of the rate matching unit 214 by a factor of four (4) to produce a signal 217 at 38.4 MHz.

Fig. 3 is a diagram showing an embodiment of the rate matching unit 214 of the fourth frequency divider 213 shown in Fig. 2. The rate matching unit 214 includes a 6-bit binary counter 302, a NAND gate 304, and a D flip-flop 306. The 6-bit binary counter 302 calculates the LO signals 205 to 64 and outputs a 6-bit binary number 303 to the NAND gate 304. The NAND gate 304 receives the 6-bit binary number 303 and outputs "0" when the binary number 303 reaches 64, otherwise outputs "1". The output 305 of the NAND gate 304 enters the "enable" of the D flip-flop 306. When the NAND gate output 305 is "1", the flip-flop starts, but when the NAND gate output is "0" The D flip-flop is turned off. The LO signal 205 counts the D flip-flop 306. The output of the D flip-flop 306 Is fed back to the input of the D flip-flop 306, and the The output is output as a clock signal 307 to time the UMTS timing manager 218. While the 64th pulse is off, the D flip-flop output 307 is tied to one-half of the input rate of the pulse train. Thus, in the present embodiment, the output rate of the D flip-flop 306 averages 153.6 MHz, and the 153.6 MHz signal is then down-converted by the divider 216 by a factor of four to produce a 38.4 MHz clock signal.

Additional crossovers can be made if other processors or modules are needed. For example, the LO signal 205 (312 MHz) can be downconverted by dividers 272, 274, 276 to 39 MHz, 78 MHz, 156 MHz, or any other frequency.

According to the present invention, the time base of GSM and UMTS can be maintained at the same time without re-acquiring time synchronization while switching modes. A single primary clock ASIC is easier to produce than a multi-clock ASIC.

Although the features and elements of the present invention are described in a particular combination of the embodiments, each feature or element of the embodiments can be used alone, without being combined with other features or elements of the preferred embodiment, or with / No combination of other features and elements of the invention. While the invention has been described in terms of the preferred embodiments, it will be apparent to those skilled in the art

100, 201‧‧‧ Unified dual mode GSM/UMTS clock

103‧‧‧Reference clock signal

105, 205‧‧‧LO signal

107‧‧‧GSM clock signal

108‧‧‧UMTS clock signal

214‧‧‧ rate matching unit

303‧‧6-bit binary number

304‧‧‧NAND gate

305, 215‧‧‧ output

306‧‧‧D forward and reverse

307‧‧‧ clock signal

200‧‧‧ transceiver

232‧‧‧Digital to analog converter

281‧‧‧Control signal

235‧‧‧Upconversion of UMTS data

237, 225‧‧‧Interpolation data

239‧‧‧Information

241‧‧‧Upconversion of GSM data

244‧‧‧UMTS data

246‧‧‧GSM data

260‧‧‧transmitter

250‧‧‧ Receiver

221‧‧‧ Downconverting Receive Signal

222‧‧‧ Analog to digital converter

223‧‧‧ sample

227‧‧‧ Down conversion data

203‧‧‧Reference clock signal

211‧‧‧ Downconversion signal

213‧‧‧fourth divider

217‧‧‧ signal

The invention will be more fully understood by the following description of the preferred embodiments, the examples given, and the accompanying drawings, in which:

Figure 1 shows a unified dual mode GSM/UMTS clock block diagram, which is configured in accordance with the present invention;

Figure 2 is a block diagram of an embodiment of a transceiver using a unified dual mode GSM/UMTS clock, configured in accordance with the present invention;

Figure 3 shows an embodiment of a rate matching unit for use in the clock of Figure 2.

214. . . Rate matching unit

205. . . LO signal

302. . . 6-bit binary counter

303. . . 6-bit binary number

304. . . NAND gate

305. . . Output

306. . . D flip-flop

307. . . Clock signal

Claims (5)

A unified dual mode mobile communications global system (GSM) / global mobile telecommunications system (UMTS) transceiver comprising: a transmitter comprising a digital to analog converter (DAC); a receiver comprising an analog to digital conversion (ADC); a dual mode GSM/UMTS reference clock comprising a reference clock configured to generate a reference clock signal; a local oscillator (LO) configured For generating a single local oscillator signal based on the reference clock signal; a first frequency divider configured to time the analog-to-digital converter; and a second frequency divider configured to time the digital a transom converter; a third frequency divider configured to (1) convert a frequency of the local oscillator signal by a predetermined integer factor to selectively generate a GSM clock signal or (2) Generating an integer factor to convert the frequency of the local oscillator signal to selectively generate a UMTS clock signal, wherein the GSM clock signal and the UMTS clock signal are generated according to the reference clock signal; wherein a rate match Unit includes: 6 digits a counter configured to count pulses of the local oscillator (LO) signal and to generate a 6-bit binary number; a NAND gate configured to generate an output based on the 6-bit binary number; and a D positive a counter configured to enable uniformity to be driven by the output of the NAND gate, the local oscillator (LO) signal timing the D flip-flop, and the D being used as a clock signal of a UMTS timing manager One of the pros and cons The output is fed back to an input of the D flip-flop. The transceiver of claim 1, wherein the reference clock is configured to generate the reference clock signal having one of a frequency of 13 MHz, 15.36 MHz, 19.2 MHz, 26 MHz, and 38.4 MHz. . The transceiver of claim 1, wherein the first frequency divider is configured to convert the LO signal to generate the UMTS clock signal having a frequency of 7.8 MHz or the frequency of 1.0833 MHz. GSM clock signal. The transceiver of claim 1, wherein the second frequency divider is configured to convert the LO signal to generate the UMTS clock signal having a frequency of 15.6 MHz or the frequency of 1.0833 MHz GSM clock signal. The transceiver of claim 1, wherein the local oscillator is configured to generate the local oscillator signal at a frequency of 312 MHz.