TWI394244B - Chip package module - Google Patents

Chip package module Download PDF

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Publication number
TWI394244B
TWI394244B TW095150097A TW95150097A TWI394244B TW I394244 B TWI394244 B TW I394244B TW 095150097 A TW095150097 A TW 095150097A TW 95150097 A TW95150097 A TW 95150097A TW I394244 B TWI394244 B TW I394244B
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Taiwan
Prior art keywords
chip package
package module
substrate
insulating layer
conductive layer
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TW095150097A
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Chinese (zh)
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TW200828543A (en
Inventor
Chien Hung Liu
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Xintec Inc
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Priority to TW095150097A priority Critical patent/TWI394244B/en
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Publication of TWI394244B publication Critical patent/TWI394244B/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods

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Description

晶片封裝模組Chip package module

本發明係有關一種晶片封裝模組,尤針對晶片封裝模組之封導電層結構加以改良,旨在提供一種被完全包覆,進而防止氧化,以及可確保晶片封裝之穩定性不會因外力干擾而斷裂之導電層結構。The invention relates to a chip package module, in particular to an improved structure of a sealing layer of a chip package module, which aims to provide a completely covered, thereby preventing oxidation, and ensuring that the stability of the chip package is not interfered by external forces. And the structure of the broken conductive layer.

近年來,由於電子產品輕量化、小型化的要求,電子元件的組裝及構裝技術,也漸次地往輕、薄、短、小的目標發展,一般單晶片或多晶片電子元件為了能夠具有傳輸I/O信號以及電流的能力,並提供散熱及保護感光晶片的功能,必須經過封裝製程加以建構成為整合好的晶片封裝模組。In recent years, due to the requirements of lightweight and miniaturization of electronic products, the assembly and assembly technology of electronic components has gradually evolved toward light, thin, short, and small targets. Generally, single-chip or multi-chip electronic components are capable of transmission. The ability of the I/O signal and current, as well as the function of dissipating heat and protecting the photosensitive wafer, must be constructed into an integrated chip package module through a packaging process.

如第一圖所示的影像感測器為例,其可以算是即為典型的模組化晶片封裝元件之一,類似的影像感測器係包括有感光晶片11、電路架構以及殼體等部份;其中,所有感光用的感光晶片11係佈列在一個設在殼體內部的基材12上,且該基材12上並設有該感光晶片11之外部接點111。As an example of the image sensor shown in the first figure, it can be regarded as one of the typical modular chip package components. A similar image sensor includes a photosensitive wafer 11, a circuit structure, and a housing. And all the photosensitive wafers 11 for light sensing are arranged on a substrate 12 disposed inside the casing, and the external contacts 111 of the photosensitive wafer 11 are disposed on the substrate 12.

另外在基材12的下方依序建構有基板13、絕緣層14、導電層15,以及最外圍的焊遮層16和電路接腳17;在整個電路架構當中,各電路接腳17即穿過焊遮層16與導電層15接觸,再經由導電層15繞過絕緣層14以及基板13的方式構成基材12與電路接腳17之間的電性聯結,而感光晶片11上方並設有一透明蓋板18,其透明蓋板18與感 光晶片11間係利用一堰牆19隔開。Further, under the substrate 12, a substrate 13, an insulating layer 14, a conductive layer 15, and an outermost solder mask 16 and circuit pins 17 are sequentially constructed; in the entire circuit structure, each circuit pin 17 passes through The solder mask 16 is in contact with the conductive layer 15 , and the electrical connection between the substrate 12 and the circuit pin 17 is formed by the conductive layer 15 bypassing the insulating layer 14 and the substrate 13 , and a transparent layer is disposed above the photosensitive wafer 11 . Cover plate 18, transparent cover 18 and sense The optical wafers 11 are separated by a wall 19 .

再者,習知的晶片封裝模組的加工製造方法,係採用如第二圖所示,在同一個基板13上同時佈列多數個晶片封裝模組的加工模式,最後再將完成封裝的晶片封裝模組單元逐一的裁切分開,使獲得完整的晶片封裝模組單體;在既有的技術領域當中,必須於建構絕緣層之前先行在晶片封裝模組單元之間開設一道如第三圖所示的凹溝A,再依序於晶片封裝模組單元上設置絕緣層、導電層以及焊遮層,最後再沿著凹溝A將透明蓋板18切斷,每一個晶片封裝模組單元得以被逐一的裁切分開。Moreover, the conventional method for manufacturing a chip package module uses a processing mode in which a plurality of chip package modules are simultaneously disposed on the same substrate 13 as shown in the second figure, and finally the packaged wafer is completed. The package module units are cut one by one to obtain a complete chip package module unit; in the existing technical field, it is necessary to open a layer between the chip package module units before constructing the insulation layer, as shown in the third figure. The groove A is shown, and then the insulating layer, the conductive layer and the solder mask are disposed on the chip package module unit, and finally the transparent cover 18 is cut along the groove A, and each chip package module unit Can be divided one by one.

然而,如此的導電層結構設計,以及加工製造方法將造成導電層在裁切處外露(如第一圖所示),以致於容易發生導電層氧化腐蝕的現象,且此種加工製造方法所形成之導電層,其與外部接點111接觸面係形成T字型接觸(T CONTACT),如第一圖所示,此種結構方式較不穩定容易脫離,且容易因為外力干擾而使該T字型接觸處產生斷裂。However, such a conductive layer structure design, and a manufacturing method will cause the conductive layer to be exposed at the cutting portion (as shown in the first figure), so that the phenomenon of oxidative corrosion of the conductive layer is liable to occur, and the manufacturing method is formed. The conductive layer, which is in contact with the external contact 111, forms a T-shaped contact. As shown in the first figure, the structure is relatively unstable and easily detached, and the T-character is easily caused by external force interference. The type of contact produces a break.

有鑑於此,本發明之主要目的即在提供一種能夠解決晶片封裝模組導電層容易氧化問題,以及可確保晶片封裝之穩定性不會因外力干擾而斷裂的導電層結構及相關的製造方法。In view of the above, the main object of the present invention is to provide a conductive layer structure and related manufacturing method capable of solving the problem that the conductive layer of the chip package module is easily oxidized, and ensuring that the stability of the wafer package is not broken by external force interference.

本發明之一種晶片封裝模組的實施例,包括:至少一晶片,布列在一基材上;一蓋板,覆蓋住該晶片;一堰牆,用於隔開該蓋板和該晶片;一穿透孔,穿過該基材;一第 一絕緣層,位於該穿透孔內;一第二絕緣層,覆蓋該基材下方;及一導電層,位於該穿透孔內並由該第一絕緣層所圍繞並延伸至該第二絕緣層上。An embodiment of a chip package module of the present invention includes: at least one wafer disposed on a substrate; a cover plate covering the wafer; and a wall for separating the cover plate and the wafer; a through hole that passes through the substrate; An insulating layer is disposed in the through hole; a second insulating layer covers the substrate; and a conductive layer is disposed in the through hole and surrounded by the first insulating layer and extends to the second insulating layer On the floor.

本發明之特點,可參閱本案圖式及實施例之詳細說明而獲得清楚地瞭解。The features of the present invention can be clearly understood by referring to the drawings and the detailed description of the embodiments.

本發明主要解決習有晶片封裝模組之導電層容易氧化腐蝕,以及結構不穩定等課題,如第四圖本發明一較佳實施例之晶片封裝模組結構剖視圖所示,本發明所應用的晶片封裝模組同樣係包括有感光晶片21、電路架構以及殼體等部份;其中,所有感光用的感光晶片21係佈列在一個設在殼體內部的基材22上,該基材22可以為矽,且該基材22上並設有該感光晶片21之外部接點211。The present invention mainly solves the problem that the conductive layer of the chip package module is easily oxidized and corroded, and the structure is unstable. For example, the fourth embodiment shows a cross-sectional view of the structure of the chip package module according to a preferred embodiment of the present invention, and the present invention is applied. The chip package module also includes a portion of the photosensitive wafer 21, the circuit structure, and the casing; wherein all the photosensitive wafers 21 for light sensing are arranged on a substrate 22 disposed inside the casing, the substrate 22 It may be 矽, and the substrate 22 is provided with an external contact 211 of the photosensitive wafer 21.

其中,基材22的下方依序建構有絕緣層23、導電層24,以及最外圍的焊遮層25和電路接腳26;在整個電路架構當中,各電路接腳26即穿過焊遮層25與導電層24接觸,透過導電層24構成感光晶片21與電路接腳26之間的電性連結,而感光晶片21上方並設有一透明蓋板27,其透明蓋板27與感光晶片21間係利用一堰牆28隔開。Wherein, the underlying substrate 22 is sequentially constructed with an insulating layer 23, a conductive layer 24, and the outermost solder mask 25 and circuit pins 26; in the entire circuit architecture, each circuit pin 26 passes through the solder mask 25 is in contact with the conductive layer 24, and the conductive layer 24 is electrically connected between the photosensitive wafer 21 and the circuit pin 26. The transparent wafer 27 is disposed above the photosensitive wafer 21, and the transparent cover 27 and the photosensitive wafer 21 are disposed. It is separated by a wall 28.

其重點在於,整個晶片封裝模組的絕緣層23底部係開設有至少一個貫穿至基材22頂面的穿透孔29,且該穿透孔29係靠近外部接點211,並且在此穿透孔29的內壁建構絕緣材料291,讓後續建構在絕緣層23外圍的導電層24得以經由穿透孔29延伸到基材22的上方,再由後續建構 的焊遮層25以及電路接腳26完全將晶片封裝模組底部的導電層24完全遮蔽,並且經由導電層24穿過絕緣層23以及基材22的方式,構成基材22與電路接腳26之間的電性聯結。The focus is that the bottom of the insulating layer 23 of the entire chip package module is provided with at least one through hole 29 penetrating to the top surface of the substrate 22, and the through hole 29 is adjacent to the external contact 211 and penetrates therethrough. The inner wall of the hole 29 is constructed with an insulating material 291, so that the conductive layer 24, which is subsequently constructed on the periphery of the insulating layer 23, extends over the substrate 22 through the through hole 29, and is subsequently constructed. The solder mask 25 and the circuit pins 26 completely shield the conductive layer 24 at the bottom of the chip package module, and form the substrate 22 and the circuit pins 26 through the conductive layer 24 through the insulating layer 23 and the substrate 22. Electrical connection between.

據以,構成一種可被完全包覆的導電層24結構,不但能夠解決導電層24外露氧化之課題,更可以讓經由晶片封裝模組基部向上延伸的導電層24被包覆在絕緣層23以及基材22的構造當中;且該導電層24與外部接點211之接觸面係為平面,而非T CONTACT式接觸,其結構更為穩定不易脫離,亦不會因外力干擾而產生斷裂。Therefore, the structure of the conductive layer 24 which can be completely covered can not only solve the problem of external oxidation of the conductive layer 24, but also the conductive layer 24 extending upward through the base of the chip package module can be coated on the insulating layer 23 and The structure of the substrate 22 is in the middle; and the contact surface of the conductive layer 24 and the external contact 211 is a flat surface instead of a T CONTACT type contact, and the structure is more stable and difficult to be detached, and no breakage occurs due to external force interference.

在具體實施時,本發明晶片封裝模組係同樣可以採用在同一個晶圓上同時佈列多數個晶片封裝模組的加工模式;至於,整體晶片封裝模組之加工製造方法,係包括有下列步驟:a、將複數感光晶片建構在基材22上,並於感光晶片上方設置以堰牆隔開之透明蓋板27,如第五圖所示;b、在基材22上利用蝕刻形成用以將每一個封裝晶片封裝模組單元區隔的第一道凹溝B,以及於基材22適當位置處形成至少一個貫穿至基材22頂面的穿透孔29,且該穿透孔29係靠近外部接點211,該第一道凹溝B的深度以深入透明蓋板27為佳,且該第一凹溝B以垂直基材22為佳,使晶片封裝模組單元係形成略呈矩形之外觀結構,如第四圖所示;c、在晶圓外圍建構絕緣層23,該絕緣層23係以將上述第一道凹溝B填平為佳,且同時於穿透孔29之內壁上建 構絕緣材料291;d、在絕緣層23外圍建構導電層24,讓導電層24經由穿透孔29延伸到基材22頂面,並與外部接點211連接;e、在導電層24的外圍建構焊遮層25,並且讓焊遮層25的原物料浸入第一道凹溝B;f、建構電路接腳26;g、最後沿著第一道凹溝B將基板切斷即可將每一個晶片封裝模組單元逐一的裁切分開。In a specific implementation, the chip package module of the present invention can also adopt a processing mode in which a plurality of chip package modules are simultaneously arranged on the same wafer; and the processing and manufacturing method of the whole chip package module includes the following Step: a. Constructing a plurality of photosensitive wafers on the substrate 22, and providing a transparent cover 27 separated by a wall above the photosensitive wafer, as shown in FIG. 5; b, forming an etching on the substrate 22. Forming at least one through hole 29 penetrating to the top surface of the substrate 22 at a suitable position of the substrate 22 by separating the first groove B of each packaged package module unit, and the through hole 29 The depth of the first groove B is preferably deeper than the transparent cover plate 27, and the first groove B is preferably perpendicular to the substrate 22, so that the chip package module unit is formed slightly. The appearance structure of the rectangle is as shown in the fourth figure; c. The insulating layer 23 is formed on the periphery of the wafer, and the insulating layer 23 is preferably filled with the first groove B, and is simultaneously penetrated through the hole 29. Built on the inner wall The insulating material 291 is formed on the periphery of the insulating layer 23, and the conductive layer 24 is extended to the top surface of the substrate 22 via the through hole 29 and connected to the external contact 211; e. at the periphery of the conductive layer 24. Constructing the solder mask 25, and immersing the original material of the solder mask 25 into the first trench B; f, constructing the circuit pin 26; g, and finally cutting the substrate along the first trench B to each A chip package module unit is cut one by one.

藉由上述晶片封裝模組之導電層結構設計,以及加工製造方法之實施,不但能夠解決習有晶片封裝模組之導電層容易氧化腐蝕之課題,以及可確保晶片封裝之穩定性,避免T CONTACT式接觸,使結構較為穩定不會因外力干擾而斷裂。The conductive layer structure design of the chip package module and the implementation of the manufacturing method can not only solve the problem that the conductive layer of the chip package module is easily oxidized and corrosion, but also ensure the stability of the chip package and avoid T CONTACT. Contact makes the structure more stable and will not break due to external interference.

本發明之技術內容及技術特點巳揭示如上,然而熟悉本項技術之人士仍可能基於本發明之揭示而作各種不背離本案創作精神之替換及修飾。因此,本發明之保護範圍應不限於實施例所揭示者,而應包括各種不背離本發明之替換及修飾,並為以下之申請專利範圍所涵蓋。The technical content and technical features of the present invention are disclosed above, but those skilled in the art can still make various substitutions and modifications without departing from the spirit of the present invention based on the disclosure of the present invention. Therefore, the scope of the present invention should be construed as being limited by the scope of the appended claims

A‧‧‧凹溝A‧‧‧ groove

11‧‧‧感光晶片11‧‧‧Photosensitive wafer

111‧‧‧外部接點111‧‧‧External contacts

12‧‧‧基材12‧‧‧Substrate

13‧‧‧基板13‧‧‧Substrate

14‧‧‧絕緣層14‧‧‧Insulation

15‧‧‧導電層15‧‧‧ Conductive layer

16‧‧‧焊遮層16‧‧‧welding mask

17‧‧‧電路接腳17‧‧‧Circuit pins

18‧‧‧透明蓋板18‧‧‧Transparent cover

19‧‧‧堰牆19‧‧‧堰 wall

21‧‧‧感光晶片21‧‧‧Photosensitive wafer

211‧‧‧外部接點211‧‧‧ External contacts

22‧‧‧基材22‧‧‧Substrate

23‧‧‧絕緣層23‧‧‧Insulation

24‧‧‧導電層24‧‧‧ Conductive layer

25‧‧‧焊遮層25‧‧‧ welding mask

26‧‧‧電路接腳26‧‧‧Circuit pins

27‧‧‧透明蓋板27‧‧‧Transparent cover

28‧‧‧堰牆28‧‧‧堰Wall

29‧‧‧穿透孔29‧‧‧through hole

291‧‧‧絕緣材料291‧‧‧Insulation materials

第一圖係為習有影像感測器之晶片封裝模組結構剖視圖。The first figure is a cross-sectional view of a chip package module with an image sensor.

第二圖係為習有影像感測器之晶片封裝模組尚未切割之半成品結構剖視圖。The second figure is a cross-sectional view of a semi-finished product that has not been cut by the chip package module of the image sensor.

第三圖係為習有影像感測器之晶片封裝模組尚未建構絕緣層之前的半成品結構剖視圖The third figure is a cross-sectional view of the semi-finished structure before the wafer package module of the image sensor has not been constructed with an insulating layer.

第四圖係為本發明一較佳實施例之晶片封裝模組結構剖視圖。FIG. 4 is a cross-sectional view showing the structure of a chip package module according to a preferred embodiment of the present invention.

第五圖係為本發明一較佳實施例之晶片封裝模組尚未切割之半成品結構剖視圖。The fifth figure is a cross-sectional view of a semi-finished product of a wafer package module that has not been cut according to a preferred embodiment of the present invention.

21‧‧‧感光晶片21‧‧‧Photosensitive wafer

211‧‧‧外部接點211‧‧‧ External contacts

22‧‧‧基材22‧‧‧Substrate

23‧‧‧絕緣層23‧‧‧Insulation

24‧‧‧導電層24‧‧‧ Conductive layer

25‧‧‧焊遮層25‧‧‧ welding mask

26‧‧‧電路接腳26‧‧‧Circuit pins

27‧‧‧透明蓋板27‧‧‧Transparent cover

28‧‧‧堰牆28‧‧‧堰Wall

29‧‧‧穿透孔29‧‧‧through hole

291‧‧‧絕緣材料291‧‧‧Insulation materials

Claims (12)

一種晶片封裝模組,包括:至少一晶片,布列在一基材上;一蓋板,覆蓋住該晶片;一堰牆,用於隔開該蓋板和該晶片;一穿透孔,位於該堰牆下方,穿過該基材;一第一絕緣層,位於該穿透孔內;一第二絕緣層,覆蓋該基材下方;以及一導電層,位於該穿透孔內並完全由該第一絕緣層所圍繞並延伸至該第二絕緣層上。 A chip package module comprising: at least one wafer disposed on a substrate; a cover plate covering the wafer; a wall for separating the cover plate and the wafer; a penetration hole located at Under the crucible wall, through the substrate; a first insulating layer is located in the through hole; a second insulating layer covers the underside of the substrate; and a conductive layer is located in the through hole and is completely The first insulating layer surrounds and extends onto the second insulating layer. 如申請專利範圍第1項所述之晶片封裝模組,其更包括一焊遮層,其覆蓋該第二絕緣層及該導電層;藉以使得該導電層免於暴露而被氧化。 The chip package module of claim 1, further comprising a solder mask covering the second insulating layer and the conductive layer; thereby oxidizing the conductive layer from exposure. 如申請專利範圍第1項所述之晶片封裝模組,其更包括一外部接點,在該穿透孔之上,以電性耦接該導電層。 The chip package module of claim 1, further comprising an external contact, the conductive layer being electrically coupled to the through hole. 如申請專利範圍第3項所述之晶片封裝模組,其更包括一電路接腳,該導電層電性耦接該電路接腳和該外部接點。 The chip package module of claim 3, further comprising a circuit pin electrically coupled to the circuit pin and the external contact. 如申請專利範圍第4項所述之晶片封裝模組,其中該基材之底部和側邊呈直角。 The chip package module of claim 4, wherein the bottom and sides of the substrate are at right angles. 如申請專利範圍第4項所述之晶片封裝模組,其中該第二絕緣層鄰接該基材側邊。 The chip package module of claim 4, wherein the second insulating layer is adjacent to a side of the substrate. 如申請專利範圍第4項所述之晶片封裝模組,其中 該第二絕緣層位於該基材底部並鄰接該基材側邊。 The chip package module of claim 4, wherein The second insulating layer is located at the bottom of the substrate and adjacent to the side of the substrate. 如申請專利範圍第2項所述之晶片封裝模組,其中該堰牆連接該焊遮層。 The chip package module of claim 2, wherein the sidewall is connected to the solder mask. 如申請專利範圍第2項所述之晶片封裝模組,其中該堰牆連接該第二絕緣層及該焊遮層。 The chip package module of claim 2, wherein the sidewall is connected to the second insulating layer and the solder mask. 如申請專利範圍第1項所述之晶片封裝模組,其中該蓋板為透光材料構成。 The chip package module of claim 1, wherein the cover plate is made of a light transmissive material. 如申請專利範圍第1項所述之晶片封裝模組,其中該基材為矽材料構成。 The chip package module of claim 1, wherein the substrate is made of a tantalum material. 如申請專利範圍第1至11項任一項所述之晶片封裝模組,其中該穿透孔整體的深度與鄰近該穿透孔的該基材的厚度相等。 The chip package module according to any one of claims 1 to 11, wherein the penetration hole has a depth equal to a thickness of the substrate adjacent to the penetration hole.
TW095150097A 2006-12-29 2006-12-29 Chip package module TWI394244B (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI244186B (en) * 2005-03-02 2005-11-21 Advanced Semiconductor Eng Semiconductor package and method for manufacturing the same
TWI250596B (en) * 2004-07-23 2006-03-01 Ind Tech Res Inst Wafer-level chip scale packaging method
TWI254467B (en) * 2005-03-01 2006-05-01 Advanced Semiconductor Eng Semiconductor package having an optical device and the method of making the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI250596B (en) * 2004-07-23 2006-03-01 Ind Tech Res Inst Wafer-level chip scale packaging method
TWI254467B (en) * 2005-03-01 2006-05-01 Advanced Semiconductor Eng Semiconductor package having an optical device and the method of making the same
TWI244186B (en) * 2005-03-02 2005-11-21 Advanced Semiconductor Eng Semiconductor package and method for manufacturing the same

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