TWI393234B - Package substrate and chip package structure - Google Patents

Description

Package substrate and chip package structure

The present invention relates to a package substrate and a chip package structure including the package substrate, and in particular, the package substrate according to the present invention includes a plurality of marks corresponding to a part of the pins, so that the user can conveniently calculate the number of pins, and thus Quickly find the location of the pin you are looking for.

With the advancement of semiconductor technology and the increasing demand of users, more and more electronic products need to use high-performance chips as the computing core. The increase in the performance of the wafer usually also represents an increase in the number and type of signals input to or output from the wafer. Therefore, the number of leads or wires used for signal transmission also needs to be greatly increased.

However, due to the trend of thinning or miniaturization of the size or size of most electronic products or their components, the size of the wafer must also shrink, so the external pins or wires must be thinner and more closely arranged. . At present, in order to ensure the normal conduction of the wafer and the leads or wires, and to protect the wafer from damage caused by external forces such as collision or pulling, the above purpose is often achieved by means of packaging.

The existing chip package type includes a Tape Automated Bonding technology using a flexible substrate as a wafer carrier, which includes: Tape Carrier Package (TCP), film flip chip Chip On Film (COF), etc. This type of package is to fix the wafer on the carrier tape and press-fit the metal conductive layer carrying the tape with the bumps or pads of the wafer, which is one of the common chip packaging technologies. It is a package applied to a driving chip of a liquid crystal display. The metal conductive layer disposed on the carrying tape is patterned by, for example, etching to form a plurality of pins and a plurality of test pads, and one end of each pin is electrically connected to the bump or the pad of the wafer. And extending outwardly to respectively connect one of the test pads.

After the wafer is bonded to the carrier tape, it is usually necessary to electrically test the packaged wafer. The most common test method currently used is probe testing, which is usually done by a probe card containing several probes. During the test, the probe can sequentially contact the surface of the test pad to detect whether the signal transmitted by the pin connected to the test pad is normal.

If the test results indicate electrical anomalies on certain pins (possibly due to pin breakage, short circuit contact with adjacent pins, bumps in the die bond area, or poor contact with the test pads), then The operator will cut it out as a defective product and hand it over to the relevant personnel for failure analysis. The failure analysis usually needs to visually inspect the defective product through the microscope, find the abnormal pin, and analyze the cause of the abnormality. .

However, these pins are hundreds of pins, and analysts need to spend a lot of effort and time, focus on one by one calculation, find the pin corresponding to the abnormal test data. This is not only costly, but also inefficient. It is easier to find the wrong pin because of the number of errors, resulting in half the results.

Therefore, one aspect of the present invention is to provide a package substrate, and in particular, the package substrate according to the present invention includes a plurality of marks corresponding to a part of the pins, so that the user can conveniently calculate the number of pins, thereby quickly finding the desired one. The position of the pins to solve the problems in the prior art.

According to a specific embodiment, the package substrate comprises a flexible dielectric layer, a plurality of first pins, a plurality of second pins, and a plurality of marks. The flexible dielectric layer defines a die bond region for arranging a wafer. The plurality of first pins and the plurality of second pins are disposed on the flexible dielectric layer and extend outward from the wafer bonding region, respectively. The plurality of marks are located in the wafer bonding region, and a plurality of second pins are disposed on the flexible dielectric layer. Wherein each of the second pins of the plurality of second pins becomes a second pin group, and a plurality of the first pins are located between the second pin groups, and the M system is a positive integer .

Another aspect of the present invention is to provide a chip package structure to solve the problems in the prior art.

According to a specific embodiment, the chip package structure of the present invention comprises a package substrate and a wafer. As described above, the package substrate includes a flexible dielectric layer, a plurality of first pins, a plurality of second pins, and a plurality of marks. The flexible dielectric layer defines a wafer bonding region for arranging the wafer. The plurality of first pins and the plurality of second pins are disposed on the flexible dielectric layer and extend outward from the wafer bonding region, respectively. And the plurality of marks are located in the wafer bonding region, and the plurality of second pins are disposed on the flexible dielectric layer. Wherein each of the second pins of the plurality of second pins becomes a second pin group, and a plurality of the first pins are located between the second pin groups, and the M system is a positive integer .

In summary, when the data of the probe test is abnormal, and the problematic pin must be manually identified by the naked eye, the design of the mark corresponding to the second pin in the present invention can facilitate the calculation of the lead by the operator. The number of feet, along with test data, can quickly and efficiently find abnormal pins. In addition, the design of the tag also has the function of assisting positioning.

The advantages and spirit of the present invention will be further understood from the following detailed description of the invention.

The invention provides a package substrate and a chip package structure including the package substrate. Several specific embodiments in accordance with the present invention are disclosed below.

1 and FIG. 2, FIG. 1 is a top view of a package substrate 10 according to an embodiment of the present invention; and FIG. 2 is a top view of a chip package structure 1 according to an embodiment of the present invention. (Where the wafer 12 is shown in partial perspective). As shown in the figure, the chip package structure 1 of the present invention comprises the package substrate 10 and a wafer 12 disposed on the package substrate 10.

Further, as shown in FIG. 1 and FIG. 2, the package substrate 10 of the present invention comprises a flexible dielectric layer 100, a plurality of first pins 102, a plurality of second pins 104, a plurality of marks 106, and a plurality of Test pad 108. In addition, the flexible dielectric layer 100 defines a die bond region 1000. The wafer 12 can be disposed in the die bond region 1000 by flip chip or other suitable means. A plurality of contacts (e.g., bumps or pads) of the wafer 12 correspond to the pins 102 and 104, respectively, and the contacts are coupled to the corresponding pins 102, 104, for example, by heat and pressure.

In the embodiment, the plurality of first pins 102 and the plurality of second pins 104 are disposed on the flexible dielectric layer 100 and extend outward from the wafer bonding region 1000 (away from the wafer) Joint area). In addition, the test pads 108 are electrically connected to the other ends of the pins 102 and 104, respectively. In practical applications, the probe can be contacted with the test pads 108 for testing to determine whether the electrical properties of the chip package structure 1 are normal.

In this embodiment, the package substrate 10 includes a plurality of marks 106 (only two of the marks 106 are shown in the figure), located in the wafer bonding area 1000, and corresponding to the plurality of second pins 104. The markers 106 are also disposed on the flexible dielectric layer 100.

In addition, each of the plurality of second pins 104 included in the plurality of second pins 104 included in the package substrate 10 of the present invention becomes a second pin group, and each of the second pin groups has a plurality of such The first pin 102, M is a positive integer. In the specific embodiment shown in FIG. 1, M is equal to 1, in other words, each second pin 104 is a second pin group. In addition, in the specific embodiment shown in FIG. 1, nine first pins 102 are spaced apart between the two second pin groups. In other words, in this embodiment, a mark 106 is provided for every ten pins 102, 104, thereby facilitating the operator to calculate the number of pins.

In addition, in practical applications, the material of the flexible dielectric layer 100 may be polyimide (PI), polyethylene terephthalate (PET) or other suitable materials. In practice, in order to enhance the heat dissipation effect of the package substrate 10 on the wafer 12, the flexible dielectric layer 100 may be fabricated using a material having a high thermal conductivity.

In addition, the material of the plurality of first pins 102, the plurality of second pins 104, and the plurality of marks 106 may be a metal material (such as, but not limited to, copper). The first pins 102, the second pins 104, and the marks 106 can be formed by etching in the same etching process. Further, in practical applications, the indicia 106 may also be made of a solder resist material or an epoxy resin. Also, the indicia 106 can be formed by printing or other suitable means.

In practical applications, the appearance, size, and shape of the aforementioned mark 106 can be appropriately adjusted for the convenience of the wafer packaging process or for consideration of time and money. The following will be described in detail in several embodiments.

Referring to FIG. 3A to FIG. 3E, the drawings respectively show schematic diagrams of setting states of the mark 106 according to the present invention. Please note that in order to more clearly illustrate the setting of the markers 106, FIGS. 3A to 3E only depict partial pins (including the first pin 102 and the second pin 104) and the wafer bonding region 1000, The complete package substrate or chip package structure is not shown.

As shown in FIG. 3A, in the embodiment, M is equal to 2, that is, every 2 second pins 104 become a second pin group, and each of the second pin groups includes 3 A pin 102. In other words, in the embodiment, the number of the first pins 102 between the second pin groups is the same.

As shown in FIG. 3B, in the embodiment, M is equal to 1, that is, each of the second pins 104 becomes a second pin group, and the first pin group includes The number of pins 102 is sequentially increased from left to right, which are 1, 2, 3, ....

As shown in FIG. 3C, in the embodiment, M is also equal to 1, that is, each second pin 104 becomes a second pin group, and the second pin group includes The number of one pin 102 is sequentially decreased from left to right, which are 3, 2, and 1 respectively. In particular, in the present embodiment, the shape of the mark 106 is circular. Of course, in practice, the shape of the indicia 106 may be varied as appropriate and is not limited to the examples given in this specification.

As shown in FIG. 3D, in the embodiment, M is equal to 3, that is, every 3 second pins 104 become a second pin group, and each of the second pin groups includes 3 A pin 102. In particular, in the present embodiment, the mark 106 is of the English alphabet (A, B, C, ...), whereby the operator can use the order of the letters as the unit for calculating the carry of the pins 102, 104.

As shown in Fig. 3E, in the present embodiment, the mark 106 is of the Arabic numerals (1, 2, 3, ...), whereby the operator can quickly know the number and position of the pins.

It should be noted that the above embodiments are intended to describe the present invention in more detail, but the number, arrangement, and form of the markers of the present invention may be adjusted as appropriate. In addition, the above M is a positive integer, which may be equal to 5, 10, ... or other suitable quantities depending on the actual situation.

In one embodiment, the package substrate 10 of the present invention may further include a solder resist layer partially covering the pins 102, 104 and exposing the die bond region 1000. In practical applications, the solder mask can protect the pins 102, 104 from external forces and prevent the pins 102, 104 from contacting the conductors to create a short circuit.

In practical applications, the appearance, size, and shape of the mark of the present invention can be appropriately adjusted for the convenience of the wafer packaging process or for consideration of time and money. The following will be described in detail in several embodiments.

Referring to FIG. 4, FIG. 4 is a top view of a package substrate 10 according to another embodiment of the present invention. As shown in FIG. 4, the package substrate 10 of the present invention comprises a flexible dielectric layer 100, a plurality of first pins 102, a plurality of second pins 104, and a plurality of marks 109. In addition, a wafer bonding region 1000 is defined on the flexible dielectric layer 100, and a wafer (not shown) may be disposed in the wafer bonding region 1000 by flip chip or other suitable manner.

In the present embodiment, the plurality of marks 109 are located in the wafer bonding region 1000, and the plurality of second pins 104 are disposed on the flexible dielectric layer 100. Different from the one shown in FIG. 1, the marks 109 in the specific embodiment are respectively connected to the corresponding second pins 104. In other words, each of the second pins 104 and their corresponding indicia 109 can be considered as a tag pin in one piece. In addition, as described above, each of the second pins 104 of the second pins 104 becomes a second pin group, and a plurality of the first pins 102 are located in the second pin group. between. In the specific embodiment shown in FIG. 4, M is equal to 1, in other words, each second pin 104 is a second pin group. In addition, in the specific embodiment shown in FIG. 4, nine first pins 102 are spaced apart between the two second pin groups. In other words, in the specific embodiment, a mark 109 is provided for every 10 pins 102 and 104, that is, every 10 pins 102 and 104 are a mark pin, thereby facilitating the operator to calculate the pin. number.

In practice, the marks 109 and the pins 102, 104 can be formed in the same etching process by etching a metal material. Further, in practical applications, the marks 109 may also be made of a solder resist material or an epoxy resin. Also, the indicia 109 can be formed by printing or other suitable means.

Please refer to FIG. 5A and FIG. 5B, which are respectively schematic diagrams showing the setting state of the mark 109 according to the present invention. Please note that in order to more clearly illustrate the setting of the markers 109, FIGS. 5A and 5B only depict partial pins (including the first pin 102 and the second pin 104) and the wafer bonding region 1000, The complete package substrate or chip package structure is not shown.

As shown in FIG. 5A, in the embodiment, M is equal to 2, that is, every 2 second pins 104 become a second pin group, and each of the second pin groups includes 4 A pin 102. In other words, in the embodiment, the number of the first pins 102 between the second pin groups is the same. In particular, in the present embodiment, the mark 109 is formed at the end of the second pin 104, which can be regarded as the extension of the second pin 104 toward the center of the wafer bonding region 1000.

As shown in FIG. 5B, in the embodiment, M is equal to 1, that is, each second pin 104 becomes a second pin group, and each of the second pin groups includes seven A pin 102. In particular, in the present embodiment, the mark 109 is formed at the end of the second pin 104, which can also be regarded as the extension of the second pin 104 toward the center of the wafer bonding region 1000. Further, the mark 109 in this embodiment is a triangle.

Please note that the markings of the present invention are designed to facilitate the operator to calculate the pins and match the test data to quickly and efficiently find the problematic pins. Therefore, for such a purpose, the form of the mark of the present invention can be reasonably adjusted as appropriate, and is not limited to the examples given above.

In summary, when the data of the probe test is abnormal, and the problematic pin must be manually identified by the naked eye, the design of the mark corresponding to the second pin in the present invention can facilitate the calculation of the lead by the operator. The number of feet, along with test data, can quickly and efficiently find abnormal pins.

The features and spirit of the present invention will be more apparent from the detailed description of the preferred embodiments. On the contrary, the intention is to cover various modifications and equivalents within the scope of the invention as claimed.

1. . . Chip package structure

12. . . Wafer

10. . . Package substrate

100. . . Flexible dielectric layer

1000. . . Wafer bonding area

102. . . First pin

104. . . Second pin

106, 109. . . mark

108. . . Test pad

1 is a top view of a package substrate in accordance with an embodiment of the present invention.

2 is a top view of a wafer package structure in accordance with an embodiment of the present invention.

3A to 3E are schematic views respectively showing setting states of the mark according to the present invention.

4 is a top view of a package substrate in accordance with an embodiment of the present invention.

FIG. 5A and FIG. 5B are respectively schematic diagrams showing the setting states of the mark according to the present invention.

10. . . Package substrate

100. . . Flexible dielectric layer

1000. . . Wafer bonding area

102. . . First pin

104. . . Second pin

106. . . mark

108. . . Test pad

Claims (16)

A package substrate comprising: a flexible dielectric layer defining a wafer bonding region for arranging a wafer; a plurality of first pins disposed on the flexible dielectric layer and respectively Extending outwardly from the wafer bonding region; a plurality of second pins disposed on the flexible dielectric layer and extending outwardly from the wafer bonding region; and a plurality of marks located in the wafer bonding region and corresponding to plural a second pin is disposed on the flexible dielectric layer; wherein each of the plurality of second pins of the plurality of second pins becomes a second pin group, and the plurality of the first pins Located between each of the second pin groups, the M system is a positive integer, and the plurality of tags are respectively connected to the corresponding plurality of second pins. The package substrate according to claim 1, wherein the number of the first pins between the second pin groups is the same. The package substrate of claim 1, wherein the number of the first pins between each of the second pin groups is sequentially increased or decreased. The package substrate according to claim 1, wherein the plurality of first pins, the plurality of second pins, and the plurality of marks are made of a metal material. The package substrate as described in claim 4, wherein the plurality of first pins, the plurality of second pins, and the plurality of marks are formed by etching. The package substrate according to claim 1, wherein the plurality of marks are made of a solder resist material or an epoxy resin. The package substrate of claim 6, wherein the plurality of marks are formed by printing. A chip package structure comprising: a package substrate, comprising: a flexible dielectric layer defining a die bond region; a plurality of first pins disposed on the flexible dielectric layer and respectively bonded by the die Extending outwardly from the region; a plurality of second pins disposed on the flexible dielectric layer and extending outwardly from the wafer bonding region; and a plurality of marks located in the wafer bonding region and corresponding to the plurality of second a pin is disposed on the flexible dielectric layer, wherein each of the plurality of second pins of the plurality of second pins becomes a second pin group, and a plurality of the first pins are located at each Between the second set of pins, M is a positive integer, the plurality of marks are respectively connected to the corresponding plurality of second pins; and a wafer is disposed in the wafer bonding area, and the wafer includes a plurality of connections The points are respectively coupled to the plurality of first pins and the plurality of second pins. The chip package structure of claim 8, wherein the number of the first pins between each of the second pin groups is the same. The chip package structure of claim 8, wherein the number of the first pins between each of the second pin groups is sequentially incremented or decremented. The chip package structure of claim 8, wherein the plurality of first pins, the plurality of second pins, and the plurality of marks are made of a metal material. The chip package structure according to claim 11 of the patent application, the plurality of The pin, the plurality of second pins, and the plurality of marks are formed by etching. The chip package structure of claim 8, wherein the plurality of marks are made of a solder resist material or an epoxy resin. The wafer package structure of claim 13, wherein the plurality of marks are formed by printing. A package substrate comprising: a flexible dielectric layer defining a wafer bonding region for arranging a wafer; a plurality of first pins disposed on the flexible dielectric layer and respectively Extending outwardly from the wafer bonding region; a plurality of second pins disposed on the flexible dielectric layer and extending outwardly from the wafer bonding region; and a plurality of marks located in the wafer bonding region and corresponding to plural a second pin is disposed on the flexible dielectric layer; wherein each of the plurality of second pins of the plurality of second pins becomes a second pin group, and the plurality of the first pins Located between each of the second pin groups, the M system is a positive integer, and the plurality of tags are respectively located adjacent to the plurality of second pins corresponding to the plurality of pins. A chip package structure comprising: a package substrate, comprising: a flexible dielectric layer defining a die bond region; a plurality of first pins disposed on the flexible dielectric layer and respectively bonded by the die Extending outwardly from the region; a plurality of second pins disposed on the flexible dielectric layer and extending outwardly from the wafer bonding region; and a plurality of marks located in the wafer bonding region and corresponding to the plurality of second lead a leg is disposed on the flexible dielectric layer, wherein each of the plurality of second pins of the plurality of second pins becomes a second pin group, and a plurality of the first pins are located in each of the Between the two pin groups, M is a positive integer, the plurality of marks are respectively located adjacent to the plurality of second pins; and a wafer is disposed in the wafer bonding area, and the chip includes a plurality of connections The points are respectively coupled to the plurality of first pins and the plurality of second pins.