TWI393189B - Design method and architecture for power gate switch placement - Google Patents

Description

Design method and architecture for power gate switch configuration Field of invention

The present invention relates to a method of designing a multi-threshold voltage complementary metal oxide semiconductor (MTCMOS) circuit and a physical architecture resulting from the results obtained using the method. In particular, the present invention relates to a method of arranging a power switch in an MTCMOS design and a physical architecture resulting from the results obtained using the method.

Background of the invention

One of the major concerns in integrated design is the reduction of leakage current. The leakage current flows into the ground node from the power supply node in the logic circuit due to the undesirable switching characteristics of the transistor in the logic design (ie, the transistor cannot be completely turned off).

In an MTCMOS circuit, one technique for reducing the leakage current is to place a "power gate" between the lowest potential junction of a logic gate ("virtual ground" reference) and the ground reference (also known as a "power switch" or simply It is a "switch unit"). This technique is shown in Figure 1 which shows the power gate or logic unit 101 that controls the logic unit 102 to the grounded leakage current path. As shown in Figure 1, the switching unit 102 is formed using a low threshold voltage transistor to provide a short switching time. The power gate is typically a transistor having a threshold voltage that is higher than a threshold voltage of a transistor used to apply the logic cells. The leakage current path from the power gate to ground. When the power gate 101 is electrically conductive (i.e., a high voltage is provided at the control node 106), the leakage current is passed by the power supply node 104 through the logic unit 102 to the virtual ground node 103 and through the power gate 101 to the real ground node 105. However, at the time of standby (i.e., when a voltage that is much less than the threshold voltage of the power gate 101 is applied to the control node 106), the power gate 101 cuts off the path from the virtual ground node 103 to the real ground node 105.

Several design methods have been used to provide the power gate unit, such as the method shown in Figure 2 ("integrated switch") to integrate the power gate 202 with the logic unit 201. In this configuration, logic unit 201 is arranged in columns according to conventional standard cell designs. As shown in Figure 2, conductors 204a and 204b are part of a power grid that provides a supply voltage to the switching unit. Similarly, conductors 203a and 203b are portions of a ground reference grid that provides a true ground reference to the switch unit. A virtual ground node is placed within each switching unit (e.g., switching unit 101).

Figure 3 shows a second method of arranging a power gate ("cavity switch") in which a column of logic cells (such as logic cells 301a, 301b, 301c, and 301d) are shared in adjacent dedicated columns (such as "power switch recesses" The power switch provided in 302). Conductors 303a and 303b provide a true ground voltage reference and conductors 304a and 304b provide a supply voltage reference.

Figure 4 shows a third method of arranging a power gate ("ring switch") in which a group of switch units (such as switch unit 401) share a circular strip (such as power gate region 402) surrounded by a circle around the switch unit. The power switch is arranged. The power switches in the power gate region 402 are typically connected in parallel. The conductors outside the power gate region 402 are routed to the power gates in the power gate region 402. A virtual ground reference node is provided between the power gate region 402 and the logic unit 401.

Figure 5 shows a fourth method of arranging a power supply gate ("grid switch") in which power switches (such as power switches in power switch areas 502a and 502b) are arranged at regular intervals to serve at regular intervals. Its adjacent multi-column logic cells (e.g., logic cells 501a and 501b are serviced by power switches in power switch 502a). Power switches in the predetermined power switch zone can be connected in parallel, and conductors (e.g., conductors 505a, 505b, and 505c) extending orthogonally to the respective column of switch cells can provide a virtual ground reference grid.

Summary of invention

One design method places a power gate or switch unit in an unoccupied position of the logic cell column. These power gates do not have to be fully connected in parallel. In an embodiment ("fill switch"), there is no limit to the arrangement of the power gates. In another embodiment ("sealed switch"), the power gates are arranged in logic units that are successively arranged adjacent to one of the same sleep signal domains. Due to the customary standard cell design and layout technology, only 70-80% of the layout density or the use (the unoccupied space between 20-30% of the available space in each logical unit) is achieved. Arranging the power gate units in the occupied space does not increase the overall real estate demand, even if the power gate units are introduced into the design. Arrangement optimization techniques can be applied to achieve the proper size and distribution of the power gate unit while avoiding performance penalties due to the power gate unit. In one embodiment, the fine grained power gate is achieved by selectively providing a non-power gate logic unit in the power gate logic unit.

The invention can be applied to a power supply gate unit that connects a virtual ground voltage reference to a true ground and a power supply gate unit that connects a virtual power supply voltage reference to a true supply voltage reference.

With these fill switches, the virtual ground voltage reference to the logic cells can be routed using conventional logic signal routing techniques. These virtual ground references can be routed using routing channels, using channelless routing techniques (such as on logical units in one or more signal routing layers), or using a common switch ground bus. The method of the present invention can be used with any signal routing technique.

In accordance with an embodiment of the present invention, an integrated circuit can include a supply voltage reference, a ground voltage reference, logic cells arranged in a linear configuration to form a plurality of columns of cells, and logic provided in each column of cells Unit unit. In one embodiment, the conductors in the routing channel are used to route the virtual ground signal between the logic unit and the power gate in the same manner as the logic signal is routed between the logic cells in accordance with conventional standard cell design methods.

In one embodiment, each of the power gate units having a different number of transistors connected in parallel can be provided in a design library. A properly selected power gate unit limits the required circuit real estate to the voltage drop through the power gate unit.

In an embodiment, the power gate logic unit (ie, the switch unit that is directly connected to the true ground voltage reference) is arranged. Non-power gate logic cells can achieve higher circuit performance where needed. In this manner, high circuit performance is achieved with a trade-off of a very small amount of additional leakage current.

In an embodiment, the unoccupied space in which the power gate unit is disposed is generated in a random manner such that the power gate unit is arranged in an irregular manner. Optimization techniques can be applied to reduce irregularities in the distribution of the power supply gate units. Such optimization techniques may include adjusting the number of power gate units to be used, the size of each power gate unit, and the selected location of the power gate unit.

In accordance with an embodiment of the present invention, a method for arranging power supply gate units includes first arranging logic units in columns. Among the arranged logic units is a logic unit to be a power gate, which has a connector for coupling a virtual ground voltage reference. The power gate unit is then arranged in columns in the unoccupied space and the virtual ground voltage node is routed between the logic unit and the power gate unit in accordance with the routing technique employed. The width of the conductor used to carry the virtual ground voltage reference is provided in accordance with an estimate of the wiring resistance.

In an embodiment, the size of each of the power gate units that are disposed in the unoccupied space is calculated based on the estimated current in the logic unit to which the power gate unit is to be connected. These currents are estimated using static or dynamic techniques. In another embodiment, the size of each power gate unit that is arranged can be determined using the number of transistors in the logic unit to be connected.

In an embodiment, an arrangement optimization step is performed to re-determine the size of the unoccupied space before arranging the power gate unit, for example by removing the logic unit in each column along the lateral direction, or by The logic cells passing through the columns are removed by the longitudinal direction.

In an embodiment, prior to arranging the power gate unit, an arrangement optimization step is performed to rearrange the logic unit to achieve a particular distribution of unoccupied space. This particular distribution can be achieved by determining the distance to a particular target for each column between the two power gate units.

The invention will be better understood from the following detailed description and drawings.

Simple illustration

Figure 1 schematically shows the power gate or switching unit 101 of the leakage current path of the controlled logic unit 102 to ground.

Figure 2 shows the logic unit 201 of the accumulation logic unit 202, which can be arranged using conventional standard cell design methods.

Figure 3 shows a second method for arranging logic cells in which a column of logic cells (e.g., logic cells 301a, 301b, 301c, and 301d) are shared in adjacent dedicated columns ("switch recesses", such as power switch column 302). The power switch is provided in the middle.

Figure 4 shows a third method for arranging logic cells, wherein a group of logic cells (e.g., logic cells 401) share a power switch disposed in a circular strip (e.g., logic cell region 402) surrounding the logic cells in a circle. .

Figure 5 shows a fourth method ("grid switch") for arranging logic cells in which power switches (such as power switches in power switch zones 502a and 502b) are spaced at regular intervals relative to the columns of switch cells. Let the position be arranged.

Figures 6a and 6b show a design method ("fill switch") in accordance with an embodiment of the present invention.

Figure 6c shows the structure of, for example, logic unit 601a and fill switch unit 602a in accordance with an embodiment of the present invention.

Figure 7 shows the use of a sealed switch in accordance with an embodiment of the present invention.

Detailed description of the preferred embodiment

The present invention provides a design method in which a logic unit or a switching unit is arranged at an unoccupied position of a column of logic cells. The inventors have observed that using conventional standard cell design and placement techniques, the placement density or utilization can typically be achieved between 70-80% (i.e., unoccupied space constitutes between 20-30% of the logic cells of each column). Available space). The present invention arranges the power gate unit in an unoccupied space. The available unoccupied space typically provides sufficient space to accommodate all of the power gate units required in a column of logic cells. Therefore, the inclusion of a power gate in a logic circuit does not increase the real estate demand.

In this detailed description, the invention is illustrated with an embodiment in which the power supply gate unit is connected to the logic unit to a true ground voltage reference. However, the present invention is equally applicable to a power supply gate unit that connects a logic unit to a real power supply voltage reference (in this case, a connector that connects the power supply gate to the logic unit is referred to as a "virtual power supply voltage reference"). The invention can also be applied to both the logic unit connecting the logic unit to a true ground voltage reference and the design of the logic unit connecting the logic unit to the true supply voltage reference.

Figures 6a and 6b show a design method ("fill switch") in accordance with an embodiment of the present invention. In the filling switch design method, the filling switch (ie, the power gate unit) is designed to have the same height and shape as the logic unit in the design library, such that the filling switch unit is in the same manner as the logic unit is arranged in this column. Arranged in the usual logical unit column. As shown in Figure 6a, fabric 600 represents a three-column logic unit isolated by the space ("channel") of the area in which the inter-logic routing signals are reserved for conventional standard cell design techniques.

Fabric 600 is achieved using conventional placement techniques without the placement of any fill switches. In an embodiment, the arrangement of the logic unit and the fill switch occurs using a separate tool. In this embodiment, the arrangement of the logic units is implemented with an arrangement tool that is unaware of the subsequent steps of providing the fill switches. In another embodiment, the arrangement of the logic unit and the fill switch can be implemented using the same tool, but with the arrangement of the logic units being implemented in a first stage in which the fill switch is eliminated. Excluding the fill switch can be achieved by providing the appropriate weights in the placement cost function to the fill switch or by eliminating the fill switch by the design hall in which the particular arrangement step is used. In the initial arrangement, the logic unit can be arranged according to its "sleep signal domain" (ie, the logic unit that is controlled by the same control signal to be connected to the fill switch unit). The sleep domain of a logic unit can be determined by traversing the list of nets from the control signal of the switching unit to the back through the buffer and serially connecting the pairs of inverters to the source of the control signal.

As shown in Figure 6a, conductors 603a and 603b provide a supply voltage reference in a conventional manner. Similarly, conductors 604a and 604b provide a true ground voltage reference in a conventional manner for each column of logic cells shown. Typically, as shown in Figure 6a, the arrangement can only fill 70-80% of the available space in each column of logic, leaving gaps such as gaps 605 and 606. In the rare case where the arrangement law can achieve a higher utilization rate and the unoccupied space left by the placement of the filling switch is insufficient, the arrangement can be directed to a space that is not available at a lower level of operation. The target, while filling the switch unit allows a minimum amount of unoccupied space.

Figure 6c shows, for example, the structure of logic unit 601a and fill switch unit 602a in accordance with one embodiment of the present invention. As shown in Figure 6a, both logic unit 601a and fill switch unit 602a are both true ground and true supply voltage references to extend through their respective top and bottom portions (i.e., locations 624 and 626). Conductor 623 is provided in logic unit 601a for connecting a logic input signal. Similarly, conductor 625 in fill switch unit 602a is provided with a sleep control signal for connecting the power gate. Conductor 622 and conductor 620 are respectively provided in logic unit 601a and fill switch unit 602a to connect a virtual ground voltage reference. This connection can be effected, for example, by conductor 624 using a suitable routing technique.

According to an embodiment of the invention, the design hall comprises a plurality of filling switch units of different sizes and different orientations. In the next step, the unoccupied space ("gap") in the logical unit column is determined. In each gap, one or more fill switch units are arranged. The size of the arranged fill switch unit can be determined, for example, by a current estimate assigned to the logic unit filling the switch. The current assigned to the logic unit filling the switch can be estimated using static or dynamic estimation techniques. Suitable current estimation techniques include current averaging or "Current Scheduling System and Method For Optimizing Multi-Threshold CMOS Design" of U.S. Patent Application Serial No. 10/739,659, filed on Dec. 17, 2003. Any of the dynamic current estimation techniques disclosed in "Vectorless Instantaneous Current Estimation" of U.S. Patent No. 6,807,660, issued Oct. 19, 2004. The size of the arranged fill switch unit can also be determined by the number of transistors that can be assigned to nearby logic cells by the fill switch unit. The use of any of these and other suitable methods is necessary to determine the necessary cumulative device size for each group of logic cells. Depending on the required size, a suitable filling switch unit is selected and arranged in the gap. The orientation of the placed fill switch unit (Note 1) is selected to minimize the virtual ground net impedance. Figure 6b shows the resulting composition 610. For example, gaps 605 and 606 of Figure 6a are replaced with fill switch units 602a and 602b, respectively.

[Note 1] Various versions of the filling switch unit with a certain current capability can be provided (such as a filling switch unit and its mirror image). In some embodiments, the selection of one version for another version may result in a lower resistance in the virtual ground signal. This difference can be due, for example, to the location of the conductor used to connect the virtual ground voltage reference.

A comprehensive overall routing model for estimating the wiring resistance of the virtual ground grid based on the position of the filling switch unit served by a virtual grounding grid and the location of the logic unit is a preferred tool for guiding the arrangement. In one embodiment, at the time of optimization, the fill switch is assigned a fill switch in the order of decreasing current demand (ie, the logic unit with the highest current demand is first designated to fill the switch), so that the logic unit has the highest current demand. It is placed closest to it. Filling switches that serve the same logical unit or groups of logical units are connected in parallel to provide a single virtual grounding grid, while meeting the virtual grounding threshold voltage of the logic unit with higher current requirements and available for use in the filling switch unit arrangement Maximizing space utilization (ie, filling switches that serve the same logical unit or groups of logical units can be distributed over several small gaps in the same neighborhood). Similarly, the fill switch unit arrangement can also be limited by the wiring limit specification to limit the voltage drop between the true ground voltage reference of the logic unit and the true ground reference. This wiring limit specification also minimizes the effect of the desired electromigration of the resulting virtual ground grid.

The invention can also be used with "local power gate" technology. In this technique, the filling switch units do not share in parallel if they share the same sleep signal domain or the same true ground connection.

An arrangement optimization technique including, for example, re-adjusting the gap size by removing the logic cells in a lateral direction can be used to allow the required fill switch to fit within the gap. Where appropriate, the logic unit can also be moved or exchanged between columns to provide or optimize the gap used to fill the switch. The gaps may also be resized or repositioned such that the fill switch units that replace the gaps may be limited to a particular size or distributed in a target distribution. An optimization step that allows rearrangement of logical unit arrangements within a column or movement of logical units between columns can be used to allow for proper distribution of the filled switch units. This redistribution of the filling unit can be optimized, for example, by avoiding the designation of the filling switch unit to serve more than a certain number of switching unit transistors for this purpose and thus affecting the timing. In general, it is intended to arrange the filling switch unit as close as possible to the logic unit it serves. A suitable cost function for specifying one of the logic cells to the fill cells may take into account the distance limit specified by the use of the virtual ground voltage reference and the true ground reference, the wiring resistance, the estimated current, the desired voltage drop, and the signal integrity of the concern. It also intends to limit the movement of the logic unit at the time of filling the switching unit arrangement. In this embodiment, since the arrangement of the filling switch unit is dependent on the initial arrangement of the logic unit, the filling switch unit is thus arranged in a relatively random and irregular manner. Alternatively, the arrangement of the logic units can be adjusted after determining the size of the filling switch unit such that the filling switch unit is arranged in a more regular manner. After the filling switch unit is placed, its movement should be limited.

The arrangement may further compensate for any variation between the estimated interconnect resistance formed by the movement of the fill switch unit and the logic unit and the true interconnect resistance by reconfiguring the size of the filled switch unit when possible Be optimized.

A suitable signal routing technique can then be used to route the virtual ground voltage reference, the supply voltage reference signal and the control signal between the logic cells for the fill switch in the channel. Thus, in accordance with an embodiment of the present invention, there is no need for a dedicated routing channel for a virtual ground voltage reference. The width of the conductor used to route the virtual ground voltage reference can be adjusted based on the estimated current and wiring resistance to minimize the effects on switching speed when the active logic circuit is operating. To minimize the voltage drop in the virtual ground grid, a wide wiring can be used for the virtual ground grid. As mentioned above, the invention is not specific to the use of any routing technology. Thus, techniques can be applied to the use of channelless routing techniques, such as routing on a cell. In another embodiment, a shared virtual ground bus can be provided.

Although the arrangement of the filling switch unit is not limited, the present invention also provides a method for where a power supply gate unit can be placed. This method ("sealed switch") requires that the power lock unit ("sealed switch") be placed at one or both ends of a power gate logic unit that is continuously arranged in one of the same sleep domains. Figure 7 shows the use of a sealed switch unit in accordance with an embodiment of the present invention. As shown in FIG. 7, fabric 700 includes both power gate logic cells (such as logic cells 701 and 702) and non-power gate logic cells (such as logic cell 707). In contrast to the filling switch method, the sealed switch unit is arranged at one or both ends of a power gate logic unit that is continuously arranged in one of the same sleep domains. In this example, sealed switch units 706a and 706b are provided adjacent to logic units 701 and 702. If the entire column of logic cells (e.g., logic cell column 703) is in the same sleep signal domain, the sealed switch can be placed at one or both ends of the column (e.g., sealed switch cells 705a and 705b are arranged at the end of logic cell column 703) ).

Fig. 7 also shows the internal structure of the logic unit 703-n of column 703 and the sealed switch unit 705b. As shown in Figure 7, conductors (e.g., conductors 723 and 725) are provided for connecting logic signals and a sleep control signal to logic unit 703-n and sealed switch unit 705b, respectively. Unlike the filling switch unit, the virtual ground voltage reference 721 is provided in the same manner as the true ground and true supply voltage reference. In this manner, the connection between a logic unit and its associated sealed switch unit takes effect at the time of placement, bypassing the subsequent routing steps. The optimization techniques discussed above for the fill switch unit can be used to rearrange the logic cells and gaps to make room for the sealed switch unit.

In addition to the arrangement constraints on the sealed switch relative to its associated logic unit, the sealed switch achieves substantially the same resiliency and benefits as the fill switch discussed above.

The technique for arranging the fill switch and the sealed switch and its optimization according to an embodiment of the present invention can be implemented before signal routing, after signal routing, or both.

The following table compares the features of the various design techniques discussed in this specification for MTCMOS:

Based on the characteristics evaluated in the above table, the inventors have come to the conclusion that the filling switch method has the following advantages over the prior art:

The above detailed description is provided to illustrate the specific embodiments of the invention Many modifications and variations are possible in the field of the invention. The invention is set forth in the following patent claims.

101. . . Power brake

102. . . Switch unit

103. . . Virtual ground node

104. . . Power node

105. . . Real ground node

106. . . Control node

201. . . Switch unit

202. . . Power brake

203a. . . Ground reference grid

203b. . . Ground reference grid

204a. . . conductor

204b. . . conductor

301a-301d. . . Logical unit

302. . . Power switch recess

303a. . . conductor

303b. . . conductor

304a. . . conductor

304b. . . conductor

401. . . Logical unit

402. . . Power gate

501a. . . Logical unit

501b. . . Logical unit

502a. . . Power switch area

502b. . . Power switch area

503a-503d. . . conductor

505a-505d. . . conductor

600. . . Fabrication

601a-601c. . . Logical unit

602a-602b. . . Filling switch unit

603a-603b. . . conductor

604a-604b. . . conductor

605. . . gap

606. . . gap

610. . . Fabrication

620. . . conductor

621. . . Virtual ground

622. . . conductor

623. . . conductor

624. . . Part

625. . . conductor

626. . . Part

700. . . Fabrication

701. . . Logical unit

702. . . Logical unit

703. . . Logical unit column

703a, 703b. . . conductor

704a, 704b. . . conductor

705a, 705b. . . Sealed switch unit

706a, 706b. . . Sealed switch unit

707. . . Logical unit

721. . . Virtual ground voltage reference

723. . . conductor

725. . . conductor

Figure 1 schematically shows the power gate or switching unit 101 of the leakage current path of the controlled logic unit 102 to ground.

Figure 2 shows the logic unit 201 of the accumulation logic unit 202, which can be arranged using conventional standard cell design methods.

Figure 3 shows a second method for arranging logic cells in which a column of logic cells (e.g., logic cells 301a, 301b, 301c, and 301d) are shared in adjacent dedicated columns ("switch recesses", such as power switch column 302). The power switch is provided in the middle.

Figure 4 shows a third method for arranging logic cells, wherein a group of logic cells (e.g., logic cells 401) share a power switch disposed in a circular strip (e.g., logic cell region 402) surrounding the logic cells in a circle. .

Figure 5 shows a fourth method ("grid switch") for arranging logic cells in which power switches (such as power switches in power switch zones 502a and 502b) are spaced at regular intervals relative to the columns of switch cells. Let the position be arranged.

Figures 6a and 6b show a design method ("fill switch") in accordance with an embodiment of the present invention.

Figure 6c shows the structure of, for example, logic unit 601a and fill switch unit 602a in accordance with an embodiment of the present invention.

Figure 7 shows the use of a sealed switch in accordance with an embodiment of the present invention.

600. . . Fabrication

601a-601c. . . Logical unit

603a-603b. . . conductor

604a-604b. . . conductor

605. . . gap

606. . . gap

Claims (51)

An integrated circuit comprising: a conductor for providing a voltage reference; a column or columns of logic cells comprising a first group of logic cells, each logic cell having a connector for coupling a virtual voltage reference; One or more power supply gate units each having a connector for coupling the virtual voltage reference and a connector for coupling the conductor for providing a voltage reference between the plurality of power supply gate units Arranged wherein the joints of the virtual voltage references for coupling the logic elements of the first group are connected to a joint for coupling the virtual voltage references of the power gate units. The integrated circuit of claim 1, wherein the logic unit of the first group is continuously arranged in a column, and wherein one of the power gate units is adjacent to the logic unit of the first group One of the logical units is arranged. The integrated circuit of claim 2, wherein the conductor at a predetermined position is provided in both the adjacent logic unit and the power gate unit, such that the connector for coupling the virtual voltage reference in the logic unit Because of the nature of this arrangement, it is connected to a connector for coupling the virtual voltage reference of the power gate unit. The integrated circuit of claim 2, wherein the integrated circuit comprises logic cells arranged in a series, each column comprising a power gate unit at an end of the column. The integrated circuit of claim 2, wherein the integrated circuit comprises a logic unit configured in a first column and a second column, wherein a power gate unit is provided at an end of the first column, and logic The unit is provided at the end of the second column. The integrated circuit of claim 5, wherein the logic unit of the first group is located in the second column. The integrated circuit of claim 5, further comprising a third column comprising only conductors connected to provide the virtual voltage reference. The integrated circuit of claim 1, wherein the voltage reference is a ground voltage reference. The integrated circuit of claim 1, wherein the voltage reference is a power supply voltage reference. The integrated circuit of claim 1, wherein the connector for the virtual voltage reference for coupling the logic unit of the first group is used in a conductor in the routing channel to be connected to a virtual circuit for coupling the power gate units Voltage reference connector. The integrated circuit of claim 1, wherein the dummy voltage reference connector for coupling the logic unit of the first group is connected to a virtual voltage reference for coupling the power gate units using a channelless routing technique. Connector. The integrated circuit of claim 1, wherein the connector for the virtual voltage reference for coupling the logic unit of the first group is connected to the dummy for coupling the power gate unit with a conductor in the shared routing channel The virtual voltage reference bus of the voltage reference connector. The integrated circuit of claim 1, wherein each of the power supply gate units comprises a plurality of transistors connected in a parallel configuration. The integrated circuit of claim 1, wherein the plurality of power supply gate units are connected in a parallel configuration. The integrated circuit of claim 1, wherein each of the logic cells of the second group is connected to a conductor that provides a voltage reference. The integrated circuit of claim 1, wherein the power supply gate units are arranged in a column in an irregular manner. The integrated circuit of claim 1, wherein the power gates are arranged in a gap in a column resulting from the arrangement of the logic cells. A method for arranging a power gate unit, comprising: providing a conductor for carrying a voltage reference; arranging one or more columns of logic cells, wherein the logic cells comprise a first group of logic cells, each a logic unit having a connector for coupling a virtual voltage reference; and a plurality of power supply gate units each having a connector for coupling the virtual voltage reference to a connector for coupling the conductor for providing a voltage reference The plurality of power gate units are arranged between the logic units. The method of claim 18, wherein the logical unit of the first group is continuously arranged in a column, and wherein one of the power gate units is adjacent to the logic unit in the logic unit of the first group One is arranged. The method of claim 18, wherein the conductor at a predetermined location is provided in both the adjacent logic unit and the power gate unit such that the connector for coupling the virtual voltage reference in the logic unit is The nature of the arrangement is connected to a joint for coupling the virtual voltage reference of the power gate unit. The method of claim 18, wherein the voltage reference is a ground voltage reference. The method of claim 18, wherein the voltage reference is a power supply voltage reference. The method of claim 18, wherein the plurality of power gate units are arranged in an unoccupied space between logical units resulting from the arrangement of the logic units. The method of claim 23, wherein the size of each power gate unit disposed in the unoccupied space is determined by an estimate of the current to be connected to the logic cells of the power gate unit. Calculation. The method of claim 24, wherein the estimation of the current is performed using a static estimation technique. The method of claim 24, wherein the estimation of the current is performed using a dynamic and static estimation technique. The method of claim 23, wherein the size of each of the power gate units arranged in the unoccupied space is the number of transistors in the logic units to which the power gate unit is connected Calculation. The method of claim 18, further comprising routing the virtual A pseudo voltage reference is coupled to the connector of the virtual voltage reference for coupling the logic cells of the first group to a connector for coupling the virtual voltage references of the power gate units. The method of claim 28, wherein the routing is performed using a conductor in the routing channel. The method of claim 28, wherein the routing is performed using a conductor in the non-routing channel. The method of claim 28, wherein the routing is implemented using a shared virtual voltage reference busbar conductor. The method of claim 18, further comprising re-determining the size of the unoccupied space by moving the logical units within each column in a lateral direction. The method of claim 18, further comprising re-determining the size of the unoccupied space by moving the logical units across the columns. The method of claim 18, wherein prior to arranging the power gate units, an arrangement optimization step is performed to rearrange the logic units to achieve unoccupied space in the one or more columns A specific distribution. The method of claim 34, wherein the specific distribution is achieved by targeting a specific distance along each of the columns between the two power gate units. The method of claim 18, further comprising directly connecting a second group logic unit to the conductor for providing the voltage reference. Such as the method described in claim 18, which is used for such logic The conductor width of the connection between the unit and the power supply gate units is provided in accordance with an estimate of the wiring resistance. The method of claim 18, wherein the logical units having a common sleep domain are arranged in close proximity to each other. The method of claim 38, further comprising traversing a list of netlists to determine a control signal for the power gate associated with each of the logic units. The method of claim 39, wherein the traversing comprises tracking the control signal backwards through a plurality of pairs of buffers and inverters. The method of claim 18, wherein the logic units and the power gate units are arranged in accordance with a limit on a distance specified by the user. The method of claim 18, wherein the logic units and the power gate units are arranged in accordance with a limit on the estimated voltage drop. The method of claim 18, wherein the logic units and the power gate units are arranged in accordance with restrictions on signal integration of concern. The method of claim 18, wherein each of the power gate units is arranged in accordance with an arrangement of logic units in accordance with the arrangement of the power gate unit and the logic unit associated with the power gate. The method of claim 18, wherein each of the power gate units is associated with the power gate according to an arrangement of the power gate unit The arrangement of the logic cells estimates that one of the overall routing models is arranged. The method of claim 18, wherein the power gate units are assigned to the logic unit in descending order of current demand. The method of claim 18, wherein the power gate unit is arranged to be limited by current. The method of claim 18, wherein the logic unit uses a first arrangement step, and the power gate units are arranged using a second arrangement step, wherein the first arrangement step is not concerned with the power gates The arrangement of the units is performed. The method of claim 18, wherein the logic units are arranged with the power supply gate units using a plurality of arrangement steps, wherein one of the arrangement steps is performed with the power supply gate units excluded. The method of claim 49, further comprising assigning a high cost function to the power gate units to exclude the power gate units in the step of arranging. The method of claim 49, wherein the power gate units are excluded from the design hall used in the arrangement step.