TWI393095B - Scan line driver, shift register and compensation circuit thereof - Google Patents

Description

Scan line driver, translation register and its compensation circuit

The present invention relates to a compensation circuit for a transistor, and more particularly to a compensation circuit for applying a pull-down transistor in a translation register.

1 is a system block diagram of a flat display device. Referring to FIG. 1, in the flat display device 100, an active area 102 is included in which a pixel array can be configured. The pixel array is composed of a plurality of pixels, and at least one thin film transistor (hereinafter referred to as TFT) is disposed as a switch in each pixel. In addition, the flat panel display 100 may further include a data line driver 104 and a scan line driver 106. The data line driver 104 is coupled to the active area 102 through a plurality of data lines DL[0:m], and the scan line driver 106 is coupled to the active area 102 through a plurality of scan lines SL[0:n]. Where n and m are both positive integers.

Scan line driver 106 includes a plurality of translation registers, such as 112 and 114. Each of the translation registers can be coupled to at least a portion of the scan lines to sequentially enable the pixels coupled to each of the scan lines. Multiple pull-down transistors can be configured in each translation register. When these pull-down transistors are turned on, the potential corresponding to the output of the shift register can be pulled down to the ground potential. Thereby, the non-enabled scan line can be kept at a low potential.

In the early days, the scan line driver 106 was in the form of an external circuit, such as a wafer-film process (COF) structure configured in a flat panel display. However, as the panel process progresses, the scan line driver 106 can be directly formed on the display panel using techniques such as wafer-to-glass bonding (COG). on. Therefore, when the scan line driver 106 is formed directly on the display panel, each translation register can be implemented using a TFT. However, TFTs have inherently poor characteristics such as poor reliability. Therefore, it is necessary to cooperate with other acquired methods, such as component structure design, circuit compensation design, or system-side adjustment to increase the reliability of the TFT.

U.S. Patent No. 7,023,410 B2 is directed to the use of a TFT to achieve a translational register in a scan driver. In this prior art, each translation register uses the output signal of the next stage translation register to achieve a reset, and the output of the previous stage translation register is treated as a drive signal. In addition, the capacitor C achieves signal enhancement due to the bootstrapping effect, and uses the transistors NT2, NT6, and NT7 to provide the low potential required for the scan line driver to disable, thereby reducing the coupling of the upper and lower vibrations of the panel voltage and the internal parasitic capacitance of the circuit. The effect generates a malfunction of the circuit. However, since the operating times of the transistors NT2, NT6, and NT7 are almost the entire Frame Time, an extremely large threshold voltage shift is caused.

The invention provides a translation register and a scan line driver, which can reduce the influence of the critical voltage offset of the internally configured pull-down transistor.

It includes a compensation circuit that compensates for the shift in the threshold voltage caused by the TFT after prolonged use. .

The present invention provides a translation register having a first output terminal and including a buffer circuit, a translation drive circuit, a reset circuit, a pull-down circuit and a compensation circuit. The buffer circuit can receive an activation signal and is coupled to the translation drive circuit, the reset circuit, the pull-down circuit, and the compensation circuit. The translating drive circuit can receive a clock signal and send the clock signal to the first output during the second half of the period after the enable signal is enabled. In addition, the reset circuit can receive a reset signal and can disable the translation drive circuit when the reset signal is enabled. The pull-down circuit has a plurality of pull-down transistors, and these pull-down transistors can be coupled to the compensation circuit. Thereby, the compensation circuit can memorize the threshold voltages of the pull-down transistors, and the voltage difference between the gate and the source of each pull-down transistor is equal to the threshold voltage of the pull-down transistor plus a compensation voltage. Wherein, when the output of the first output terminal is a high potential, the compensation voltage is a low potential; and when the output of the first output terminal is a low potential, the compensation voltage is switched to a high potential.

From another point of view, the present invention also provides a scan line driver that can drive a plurality of scan lines in a display. The scan line driver of the present invention includes a plurality of translation registers having a reset terminal, a first output terminal and a second output terminal, and each translation register further includes a plurality of pull-down transistors. The first output ends of the translation registers are respectively coupled to at least one scan line, and the reset ends of each translation register are respectively coupled to the second output end of the next-stage translation register. In addition, a plurality of compensation circuits are respectively disposed in each of the translation registers, and may be coupled to corresponding pull-down transistors. Thereby, each compensation circuit can memorize the threshold voltage of the corresponding pull-down crystal such that the gate-to-source voltage across each pull-down transistor is equal to the threshold voltage of the pull-down transistor plus a compensation voltage. Wherein, when the output of the first output terminal is a high potential, the compensation voltage is a low potential; and when the output of the first output terminal is a low potential, the compensation voltage is switched to a high potential.

From another point of view, the present invention further provides a compensation circuit that can be applied to a translation register, and the translation register can have a plurality of pull-down transistors. The compensation circuit of the present invention may include a first memory circuit, a second memory circuit, a compensation drive circuit and a compensation capacitor. The first memory circuit can be coupled to the pull-down transistor in the translation register and receive a memory reset signal and a memory start signal. The second memory circuit can receive the memory reset signal and the memory start signal. In addition, the memory capacitor can couple the gate terminal of the pull-down transistor to the second memory circuit to memorize the threshold voltage of the pull-down transistors. The compensation driving circuit enables the first memory circuit and the second memory circuit to set the voltage across the gate to the source of each pull-down transistor as the threshold voltage of the pull-down transistor according to the memory reset signal and the memory start signal. The last compensation voltage.

Since the compensation circuit provided by the present invention can memorize the threshold voltage of the pull-down transistor, and the voltage difference between the pull-gate transistor gate and the source is equal to the threshold voltage of the pull-down transistor plus a compensation voltage. Therefore, the current flowing through the pull-down transistor is not affected by the threshold voltage shift.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

2 is a circuit block diagram of a scan line driver in accordance with a preferred embodiment of the present invention. Referring to FIG. 2, the scan line driver 200 provided in this embodiment includes a plurality of translation registers 202[0:n+1]. Where n is a positive integer. In addition, the translation register [n+1] can be redundant (Dummy) Register. Taking the translation register 202[0] as an example, it includes an input terminal IN, a reset terminal R, a first output terminal OUT, a second output terminal SOUT, and a clock terminal CLK. The input terminal IN can receive an activation signal STA1, and the reset terminal R can be coupled to the second output terminal SOUT of the next-stage translation register 202[1], and the translation register 202[1] The output of the second output terminal SOUT is treated as a reset signal RST1[0].

In addition, the first output terminal OUT of the translation register 202[0] can be coupled to the corresponding scan line SL[0], and the second output terminal SOUT is coupled to the input of the next-stage translation register 202[1]. End IN, and the start signal STA1 is passed to the next stage translation register 202[1]. More specifically, in this embodiment, the clock terminal CLK of the adjacent translation register can be coupled to the clock signals CLK1 and CLK2, respectively. The clock signals CLK1 and CLK2 can be inverted each other.

3 is a circuit diagram of a translation register in accordance with a preferred embodiment of the present invention. Referring to FIG. 3, the translation register 300 provided in this embodiment can be applied to the scan line driving circuit 200 in FIG. 2, and includes a buffer circuit 302, a translation driving circuit 304, a reset circuit 306, a pull-down circuit 308, and Compensation circuit 310. The buffer circuit 302 can receive the start signal STA1 through, for example, the input terminal IN in FIG. 2 . In addition, the buffer circuit 302 can also be coupled to the translation driving circuit 304, the reset circuit 306, the pull-down circuit 308, and the compensation circuit 310.

Referring to FIG. 3, the translation driving circuit 304 can receive the clock signal CLK1 or CLK2 through the clock terminal CLK of FIG. 2, and is coupled to the first output terminal OUT and the second output terminal SOUT. In this embodiment, After the start signal STA1 is enabled, the translation driving circuit 304 may output the clock signal CLK1 or CLK2 from the first output terminal OUT and the second output terminal SOUT. In addition, the reset circuit 306 can be coupled to the second output terminal SOUT (SOUT[k+1]) of the next-stage translation register (202[k+1]) through the reset terminal R in FIG. 2 . . In other words, the signal output from the second output terminal SOUT(SOUT[k+1]) of the next-stage translation register (202[k+1]) can be sent to the reset signal RST1[k]. The reset circuit 306 of the previous stage translation register (202[k]). Where k is an integer between the intervals [0, n+1]. When the reset signal RST1 (RST1[k]) is enabled, the reset circuit 306 can disable the action of the translation drive circuit 304.

In the present embodiment, the buffer circuit 302 includes a buffer transistor 312 whose anode terminal and gate terminal are coupled to each other and receives the start signal STA1. In addition, the reset circuit 306 includes a reset transistor 314 having a source terminal coupled to a low voltage VL, a gate terminal receiving the reset signal R, and a drain terminal coupled to the source terminal of the buffer transistor. Among them, the potential of the low voltage VL is, for example, a ground potential. In addition, the translating drive circuit 304 includes a first driving transistor 316, a second driving transistor 318, and a capacitor 320. The NMOS terminal of the first driving transistor receives the clock signal CLK1 or CLK2, and the gate terminal is coupled to the source terminal of the buffer transistor 312. In addition, the source terminal of the first driving transistor 316 can be coupled to its own gate terminal through the capacitor 320 and can be coupled to the first output terminal OUT. The 汲 terminal and the gate terminal of the second driving transistor 318 can be respectively coupled to the 汲 terminal and the gate terminal of the first driving transistor 316, and the source terminal of the second driving transistor 318 can be coupled to the second output terminal SOUT.

Moreover, in the present embodiment, the pull-down circuit 308 can include a first pull-down transistor 322, a second pull-down transistor 324, and a third pull-down transistor 326. The source terminal of the first pull-down transistor 322 can be coupled to the low voltage VL, and the drain terminal can be coupled to the drain terminal of the buffer transistor 312. In addition, the source and gate terminals of the second pull-down transistor 324 and the third pull-down transistor 326 may be coupled to the source terminal and the gate terminal of the first pull-down transistor 322, respectively, and the second pull-down transistor 324 and the third The 汲 terminal of the pull-down transistor 326 can be coupled to the first output terminal OUT and the second output terminal SOUT, respectively.

4 is a circuit diagram of a compensation circuit in accordance with a preferred embodiment of the present invention. Referring to FIG. 4, the compensation circuit 310 provided in this embodiment includes a first memory circuit 410, a second memory circuit 420, a memory capacitor 430, and a compensation driving circuit 440. In some embodiments, the compensation circuit 310 can also include a third memory circuit 450. The first memory circuit 410 receives a memory reset signal RST2 and a memory start signal STA2, and can be coupled to the 汲 terminal of the second pull-down transistor 324. In addition, the second memory circuit 420 can also receive the memory reset signal RST2 and the memory start signal STA2, and can be coupled to the first pull-down transistor 322, the second pull-down transistor 324, and the third pull-down through the memory capacitor 430. The gate terminal of transistor 326.

In addition, the memory driving circuit 440 can be coupled to the second memory circuit 420 and can be coupled to the gate terminal of the first driving transistor 316. In addition, the third memory circuit 450 can also receive the memory reset signal RST2 and the memory start signal STA2, and can be coupled to the memory drive circuit 440.

In this embodiment, the first memory circuit 410 includes a first memory operation. A transistor 412, a second memory operating transistor 414 and a third memory operating transistor 416 are provided. The drain terminal of the first memory operating transistor 412 receives an operating voltage V1, and its gate terminal receives the memory reset signal RST2. In addition, the gate terminal of the second memory operating transistor 414 receives the memory start signal STA2, and the drain terminal is coupled to the source terminal of the first memory operating transistor 412, and is coupled to the first pull-down transistor 322, the second The gate terminals of the transistor 324 and the third pull-down transistor 326 are pulled down. In addition, the source terminal and the gate terminal of the third memory operating transistor 416 can be coupled to the source terminal and the drain terminal of the second memory operating transistor 414, respectively, and the 汲 terminal of the third memory operating transistor 416 can be coupled to the Two pull down the 汲 extreme of the transistor 324.

In addition, in the second memory circuit 420, a fourth memory operating transistor 422 and a fifth memory operating transistor 424 are included. The source terminal of the fourth memory operation transistor 422 has a low potential VL, the gate terminal thereof receives the memory reset signal RST2, and the gate terminal is coupled to the drain terminal of the third memory operation transistor 414 through the memory capacitor 430. The gate terminal of the fifth memory operation transistor 424 receives the memory start signal STA2, and the 汲 terminal and the source terminal are coupled to the 汲 terminal and the source terminal of the fourth memory operation transistor 422, respectively.

The memory drive circuit 440 then includes a first compensation operation transistor 442, a second compensation operation transistor 444, a third compensation operation transistor 446, and a fourth compensation operation transistor 448. The source terminal of the first compensation operating transistor 442 is coupled to the low voltage VL, and the gate terminal thereof is coupled to the drain terminal of the first pull-down transistor 322. In addition, the second compensation operation transistor 444 is coupled to the compensation voltage Vc, and the source terminal is coupled to the first compensation operation transistor 442, the fourth memory operation transistor 422, and the fifth memory operation transistor 424. Extremely extreme. In addition, the gate terminal and the drain terminal of the third compensation operating motor body 446 collectively receive an operating voltage V2, and the source terminal is coupled to the gate terminal of the second compensation operating transistor 444, and coupled to the fourth compensation operating transistor.汲 汲 extreme. The gate terminal and the source terminal of the fourth compensation operating transistor 448 are coupled to the gate terminal and the source terminal of the first compensation operating transistor 442, respectively.

With continued reference to FIG. 4, the third memory circuit 450 in the compensation circuit 310 includes a sixth memory operating transistor 452 and a seventh memory operating transistor 454. The source terminal of the sixth memory operating transistor 452 is coupled to the low voltage VL, the gate terminal thereof receives the memory reset signal RST2, and the drain terminal is coupled to the drain terminal of the fourth compensation operating transistor 448. In addition, the gate terminal of the seventh memory operating transistor 454 can receive the memory start signal STA2, and the drain terminal and the source terminal can be coupled to the drain terminal and the source terminal of the sixth memory operating transistor 452, respectively.

In some embodiments, all of the transistors disclosed above can be implemented using TFTs. However, the invention is not limited thereto.

FIG. 5 is a timing diagram of a signal according to a preferred embodiment of the present invention. The translation register 202[0] of FIG. 2 is taken as an example for description. Those skilled in the art should be able to To other translation registers. Referring to FIG. 4 and FIG. 5 together, during the time interval P1, the memory reset signal RST2 is enabled, and the first memory operation transistor 412 is turned on, so that the potential of the node N1 rises to the potential of the operating voltage V1. The third memory operating transistor 416, the first pull-down transistor 322, the second pull-down transistor 324, and the third pull-down transistor 326 are both turned on. In addition, the fourth It is recalled that the operating transistor 422 is also turned on because the memory reset signal RST2 is enabled, so that the potential of the node X1 is lowered to the potential of the low voltage VL. For the convenience of description, the low voltage VL in the following paragraphs is set to the ground potential, but the invention is not limited thereto. Obviously, the potential across the memory capacitor 430 is the ground potential. In addition, the sixth memory operation transistor 452 is also turned on because the memory reset signal RST2 is enabled, and the potential of the G1 node is the ground potential.

During the time interval P2, the memory reset signal RST2 is disabled, causing the first memory operation transistor 412, the fourth memory operation transistor 422, and the sixth memory operation transistor 452 to be turned off. In addition, the memory start signal STA2 will be enabled. At this time, the second memory operation transistor 414 is turned on. Since the third memory operation transistor 416 and the second pull-down transistor 324 are both maintained in a conducting state, the voltage on the node N1 will begin to be discharged, and the voltage on the node N1 is equal to the threshold of the second pull-down transistor 324. Voltage.

In addition, the fifth memory operation transistor 424 is also turned on because the memory start signal STA2 is enabled, so that the potential of the node X1 is maintained at the ground potential. Thereby, the memory capacitor 430 can memorize the threshold voltage of the second pull-down transistor 324. In the present embodiment, the time elapsed between the time intervals P1 and P2 may be referred to as a memory period. In addition, the seventh memory operation transistor 454 is also turned on because the memory start signal STA2 is enabled, so the potential of the node G1 is maintained at the ground potential.

During the time interval P3, the memory start signal STA2 is in turn disabled, at this time, the second memory operation transistor 414, the fifth memory operation transistor Both 424 and seventh memory operating transistor 454 are turned off. In addition, the enable signal STA1 is enabled, so that the potential of the translation register 202[0] node Q1 will start to rise, so that the translation register 202[j], j=0, 2, 4...first drive The transistor 316 and the second drive transistor 318 are turned on. It is assumed that the first terminal of the first driving transistor 316 and the second driving transistor 318 are coupled to the clock signal CLK1, and since the clock signal CLK1 is disabled during the time interval P3, the first output terminal OUT[0 ] and the second output SOUT[0] does not have an output generated. In addition, since the potential of the node Q1 of the translation register 202[0] starts to rise, the first compensation operation transistor 442 and the second compensation operation transistor 448 are turned on, so that the potentials of the nodes X1 and G1 are maintained at the ground. Potential.

During time interval P4, clock signal CLK1 is enabled such that first drive transistor 316 and second drive transistor 318 of translation register 202[0] generate an operating current. Therefore, the translation register 300 can synchronously generate the scan signal from the first output terminal OUT[0] and the second output terminal SOUT[0] to the IN of the corresponding scan line and the translation register 202[1]. In addition, since the potential across the capacitor 320 is continuous, the potential of the node Q1 is again boosted.

Then, during the time interval P5, the clock signal CLK1 is disabled, and the clock signal CLK2 is enabled, resulting in the first output terminal OUT[j+1] and the second output terminal SOUT of the next-stage translation register. [j+1] will generate the scan signal synchronously. In other words, the reset signal RST1[0] of the first stage shift register is enabled. At this time, the reset transistor 314 of the translation register 202[0] is turned on, so that the potential of the node Q1 is pulled down to the ground potential. The first drive transistor 316 and the second drive transistor 318 are caused to be turned off. At this time, the first output terminal OUT[0] and the second output terminal SOUT[0] are locked at the ground potential because the second pull-down transistor 324 and the third pull-down transistor 326 are continuously turned on. After P5, the shift registers [i],, =2...n, in the same operating principle, sequentially output OUT[i] and SOUT[i] as high voltages.

Since the potential of the node Q1 is pulled down to the ground potential, the first compensation operating transistor 442 and the fourth compensation operating transistor 448 are turned off, and the potential of the node G1 rises due to the third compensation operation transistor 446 being turned on. The potential of the operating voltage V2. At this time, the second compensation operation transistor 444 is turned on, and the potential of the node X1 is pulled up to the potential of the compensation voltage Vc. Since the voltage across the memory capacitor 430 needs to be continuous, the voltage between the gate and the source of the first pull-down transistor 322, the second pull-down transistor 324, and the third pull-down transistor 326 is set to a threshold voltage plus The upper compensation voltage Vc.

It should be understood by those of ordinary skill in the art that the operating current I _DS flowing through the first pull-down transistor 322, the second pull-down transistor 324, and the third pull-down transistor 326 can be expressed by: Among them, μ , C _OX and W/L are constants, and V _gs and V _T are the voltages of the gate-to-source of the pull-down transistor and the threshold voltage, respectively. In the present embodiment, the voltage V _{gs of the} source of the gate of the transistor can be expressed by the following equation: V _gs = V _T + V _c Therefore, the equation (1) can be rewritten as Where Vc is a constant. Therefore, the operating current I _DS flowing through the first pull-down transistor 322, the second pull-down transistor 324, and the third pull-down transistor 326 is not affected by the threshold voltage shift.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

100‧‧‧Flat display device

102‧‧‧Active area

104‧‧‧Data line driver circuit

106, 200‧‧‧ scan line drive circuit

112, 114, 202 [0: n] ‧ ‧ translation register

302‧‧‧ buffer circuit

304‧‧‧ translation drive circuit

306‧‧‧Reset circuit

308‧‧‧ Pulldown circuit

310‧‧‧Compensation circuit

312‧‧‧ buffered crystal

314‧‧‧Reset the transistor

316‧‧‧First drive transistor

318‧‧‧Second drive transistor

320‧‧‧ Capacitance

322‧‧‧First pull-down transistor

324‧‧‧Second pull-down transistor

326‧‧‧ Third pull-down transistor

410‧‧‧First memory circuit

412‧‧‧First memory operating transistor

414‧‧‧Second memory operation transistor

416‧‧‧ Third memory operating transistor

420‧‧‧Second memory circuit

422‧‧‧fourth memory operation transistor

424‧‧‧ fifth memory operation transistor

430‧‧‧ memory capacitor

440‧‧‧Compensation drive circuit

442‧‧‧First compensation operating transistor

444‧‧‧Second compensation operation transistor

446‧‧‧ Third compensation operation transistor

448‧‧‧fourth compensation operation transistor

450‧‧‧third memory circuit

452‧‧‧ sixth memory operating transistor

454‧‧‧ seventh memory operating transistor

CLK‧‧‧ clock end

CLK1, CLK2‧‧‧ clock signal

DL[0:m]‧‧‧ data line

G1, N1, Q1, X1‧‧‧ nodes

IN‧‧‧ input

OUT‧‧‧ first output

P1, P2, P3, P4, P5‧‧‧ time interval

R‧‧‧Reset end

RST1[0:n]‧‧‧Reset signal

RST2‧‧‧ memory reset signal

SL[0:n]‧‧‧ scan line

SOUT‧‧‧ second output

STA1‧‧‧ start signal

STA2‧‧‧ memory start signal

V1, V2‧‧‧ operating voltage

Vc‧‧‧compensation voltage

VL‧‧‧low voltage

1 is a system block diagram of a flat display device.

2 is a circuit block diagram of a scan line driver in accordance with a preferred embodiment of the present invention.

3 is a circuit diagram of a translation register in accordance with a preferred embodiment of the present invention.

4 is a circuit diagram of a compensation circuit in accordance with a preferred embodiment of the present invention.

FIG. 5 is a timing diagram of a signal in accordance with a preferred embodiment of the present invention.

312‧‧‧ buffered crystal

314‧‧‧Reset the transistor

316‧‧‧First drive transistor

318‧‧‧Second drive transistor

320‧‧‧ Capacitance

322‧‧‧First pull-down transistor

324‧‧‧Second pull-down transistor

326‧‧‧ Third pull-down transistor

410‧‧‧First memory circuit

412‧‧‧First memory operating transistor

414‧‧‧Second memory operation transistor

416‧‧‧ Third memory operating transistor

420‧‧‧Second memory circuit

422‧‧‧fourth memory operation transistor

424‧‧‧ fifth memory operation transistor

430‧‧‧ memory capacitor

440‧‧‧Compensation drive circuit

442‧‧‧First compensation operating transistor

444‧‧‧Second compensation operation transistor

446‧‧‧ Third compensation operation transistor

448‧‧‧fourth compensation operation transistor

450‧‧‧third memory circuit

452‧‧‧ sixth memory operating transistor

454‧‧‧ seventh memory operating transistor

CLK‧‧‧ clock end

CLK1, CLK2‧‧‧ clock signal

DL[0:m]‧‧‧ data line

G1, N1, Q1, X1‧‧‧ nodes

IN‧‧‧ input

OUT‧‧‧ first output

P1, P2, P3, P4, P5‧‧‧ time interval

R‧‧‧Reset end

RST1‧‧‧Reset signal

RST2‧‧‧ memory reset signal

SL[0:n]‧‧‧ scan line

SOUT‧‧‧ second output

STA1‧‧‧ start signal

STA2‧‧‧ memory start signal

V1, V2‧‧‧ operating voltage

Claims (28)

A shift register has a first output, and the shift register includes: a buffer circuit; a translation drive circuit coupled to the buffer circuit; a reset circuit coupled to the buffer circuit and the translation drive a circuit, and receiving a reset signal; a pull-down circuit having a plurality of pull-down transistors coupled to the buffer circuit, the reset circuit, and the translation drive circuit; and a compensation circuit coupled to the buffer circuit a circuit, the pull-down circuit and the first output terminal, the compensation circuit memorizing the threshold voltages of the pull-down transistors, and causing the voltage across the gate to the source of each of the pull-down transistors to have a compensation voltage component The compensation voltage is low when the output of the first output is high, and is high when the output of the first output is low. The translation register as described in claim 1 further includes a second output. The translation register of claim 2, wherein the pull-down circuit comprises: a first pull-down transistor, the source terminal is coupled to a low voltage, and the gate terminal and the 汲 terminal are respectively coupled to the compensation circuit a second pull-down transistor, the 汲 terminal is coupled to the first output terminal and coupled to the compensation circuit, and the gate terminal and the source terminal are respectively coupled to the gate terminal and the source terminal of the first pull-down transistor ;as well as A third pull-down transistor has a source terminal coupled to the second output terminal, and a gate terminal and a source terminal coupled to the gate terminal and the source terminal of the first pull-down transistor, respectively. The translation register according to claim 1, further comprising a buffer circuit, wherein the buffer circuit has a buffer transistor, the 汲 terminal and the gate terminal are coupled to each other, and receive a start signal, and the source terminal Then coupled to the compensation circuit and coupled to the 汲 terminal of the first pull-down transistor. The translation register of claim 1, wherein the reset circuit comprises a reset transistor, the gate terminal receives the reset signal, the source terminal is grounded, and the 汲 terminal is shared with the buffer circuit. The circuit is coupled to the compensation circuit and coupled to the 汲 terminal of the first pull-down transistor. The translational register of claim 1, wherein the translation driving circuit comprises a first driving transistor, the 汲 terminal is coupled to the clock signal, and the source terminal is coupled to the first output terminal, and The first terminal of the first driving transistor is coupled to the compensation circuit and coupled to the first The 汲 extreme of the pull-on crystal. The translational register of claim 1, wherein the translation driving circuit comprises a first driving transistor, the 汲 terminal is coupled to the clock signal, and the source terminal is coupled to the first output terminal, and The first terminal of the first driving transistor is coupled to the compensation circuit and coupled to the first a 汲 terminal of the pull transistor; and a second drive transistor, the 汲 terminal and the gate terminal are respectively coupled to the first A driving transistor has a drain terminal and a gate terminal, and a source terminal of the second driving transistor is coupled to the second output terminal and coupled to a drain terminal of a third pull-down transistor of the pull-down circuit. The translation register of claim 3, wherein the low voltage potential is a ground potential. The shift register of claim 1, wherein the compensation circuit comprises: a first memory operating transistor, wherein the first terminal is coupled to a first operating voltage, and the gate terminal is coupled to a memory reset signal. The source terminal is coupled to the gate terminal of the first pull-down transistor; a second memory operating transistor has a gate terminal coupled to a memory start signal, and a drain terminal coupled to the first memory operating transistor a source terminal; a third memory operating transistor having a gate terminal and a source terminal coupled to the 汲 terminal and the source terminal of the second memory operating transistor, respectively, and the 汲 terminal of the third memory operating transistor is coupled to The first output terminal is coupled to the 汲 terminal of the second pull-down transistor; a fourth memory operating transistor, the source terminal is grounded, the gate terminal receives the memory reset signal; and a fifth memory operation transistor, The source is extremely grounded, the gate terminal is coupled to the memory start signal; and a memory capacitor is coupled to the fourth memory operating transistor and the 汲 terminal of the fifth memory operating transistor, the second terminal Then coupled to the first Pull the gate of the transistor. The translation register as described in claim 1, wherein the The compensation circuit includes: a first memory operating transistor, the first terminal is coupled to a first operating voltage, the gate terminal is coupled to a memory reset signal, and the source terminal is coupled to the gate terminal of the first pull-down transistor; a second memory operating transistor having a gate terminal coupled to a memory start signal and a drain terminal coupled to a source terminal of the first memory operating transistor; a third memory operating transistor having a gate terminal and a source The 极端 terminal and the source terminal of the second memory operating transistor are coupled to the first output terminal and coupled to the second pull-down transistor. a fourth memory operating transistor whose source is extremely grounded, the gate terminal receiving the memory reset signal; a fifth memory operating transistor whose source is extremely grounded, and whose gate terminal is coupled to the memory start signal; a first capacitor is coupled to the fourth memory operating transistor and the 汲 terminal of the fifth memory operating transistor, and the second terminal is coupled to the gate terminal of the first pull-down transistor; Operating the transistor, its source Grounding, the gate terminal is coupled to the first terminal of the first pull-down transistor; a second compensation operating transistor is coupled to the second terminal of the memory capacitor, and the source terminal is coupled to the first compensation An operating transistor, the fourth memory operating transistor, and a 汲 terminal of the fifth memory operating transistor; a third compensation operating transistor, wherein the 汲 terminal and the gate terminal are coupled together with a second operating voltage, and the source terminal Coupling the second compensation operation transistor And a fourth compensation operation transistor, wherein the source terminal is grounded, and the gate terminal and the gate terminal are respectively coupled to the gate terminals of the first compensation operation transistor and the second compensation operation transistor. The shift register of claim 1, wherein the compensation circuit comprises: a first memory operating transistor, wherein the first terminal is coupled to a first operating voltage, and the gate terminal is coupled to a memory reset signal. The source terminal is coupled to the gate terminal of the first pull-down transistor; a second memory operating transistor has a gate terminal coupled to a memory start signal, and a drain terminal coupled to the first memory operating transistor a source terminal; a third memory operating transistor having a gate terminal and a source terminal coupled to the 汲 terminal and the source terminal of the second memory operating transistor, respectively, and the 汲 terminal of the third memory operating transistor is coupled to The first output terminal is coupled to the 汲 terminal of the second pull-down transistor; a fourth memory operating transistor, the source terminal is grounded, the gate terminal receives the memory reset signal; and a fifth memory operation transistor, The source is extremely grounded, and the gate terminal is coupled to the memory start signal; a memory capacitor, the first terminal is coupled to the fourth memory operating transistor and the fifth terminal of the fifth memory operating transistor, and the second terminal is Coupling the first pull-down a gate terminal of the crystal; a first compensation operating transistor whose source is extremely grounded, and whose gate terminal is coupled to the 汲 terminal of the first pull-down transistor; a second compensation operation transistor, the 汲 terminal is coupled to the second end of the memory capacitor, and the source terminal is coupled to the first compensation operation transistor, the fourth memory operation transistor, and the fifth memory operation a third compensation operating transistor, the 汲 terminal and the gate terminal are coupled to a second operating voltage, and the source terminal is coupled to the gate terminal of the second compensation operating transistor; a fourth compensation operation a transistor whose source is extremely grounded, and its gate terminal and the gate terminal are respectively coupled to the gate terminals of the first compensation operation transistor and the second compensation operation transistor; a sixth memory operation transistor whose source terminal is grounded and its gate Extremely coupled to the memory reset signal, and the other end coupled to the fourth terminal of the fourth compensation operating transistor; and a seventh memory operating transistor whose gate terminal is coupled to the memory start signal and the source thereof The extreme and 汲 extremes are respectively coupled to the source terminal and the 汲 terminal of the sixth memory operating transistor. A scan line driver for driving a plurality of scan lines in a display, the scan driver comprising: a plurality of translation registers having a reset end, a first output end and a second output end, and each The shift register further includes a plurality of pull-down transistors, wherein the first output ends are respectively coupled to one of the scan lines, and the reset ends of the translation registers are respectively coupled to the lower a second output end of the first stage shift register, wherein the states of the first output end and the second output end are synchronized; and a plurality of compensation circuits respectively disposed in each of the translation register registers, And coupling the pull-down transistors to memorize the threshold voltages of the pull-down transistors, so that the gate-to-source voltage across each of the pull-down transistors has a component of a compensation voltage, wherein the compensation voltage is The output of the first output terminal is low when the output is high, and is switched to the high potential when the output of the first output is low. The scan line driver of claim 12, wherein the pull-down transistors comprise: a first pull-down transistor, the source terminal is coupled to a low voltage, and the gate terminal and the 汲 terminal are respectively coupled to each other. a compensation circuit; a second pull-down transistor, the 汲 terminal is coupled to the first output end and coupled to the corresponding compensation circuit, and the gate terminal and the source terminal are respectively coupled to the gate terminal of the first pull-down transistor And a source terminal; and a third pull-down transistor, the 汲 terminal is coupled to the second output terminal, and the gate terminal and the source terminal are respectively coupled to the gate terminal and the source terminal of the first pull-down transistor. The scan line driver of claim 12, wherein each of the translation registers comprises: a buffer transistor, wherein the drain terminal and the gate terminal are coupled to each other and receive a start signal, and the source terminal And coupled to the corresponding compensation circuit and coupled to the 下拉 terminal of the first pull-down transistor; and a reset transistor, the gate of which is coupled to the reset terminal, the source terminal is grounded, and the 汲 terminal is The snubber circuit is coupled to the corresponding compensation circuit and coupled to the 汲 terminal of the first pull-down transistor. A scan line driver as described in claim 12, Each of the translation registers has a clock end for receiving one of a first clock signal and a second clock signal, and the first clock signal and the second clock signal are mutually Inverted. The scan line driver of claim 12, wherein each of the translation registers comprises a buffer transistor, the 汲 terminal and the gate terminal are coupled to each other, and receive a start signal, and the source terminal is coupled. Connected to a corresponding compensation circuit and coupled to the 汲 terminal of the first pull-down transistor; and a reset transistor, the gate of which is coupled to the reset terminal, the source terminal is grounded, and the 汲 terminal is coupled to the buffer The circuit is coupled to the corresponding compensation circuit and coupled to the 汲 terminal of the first pull-down transistor; and a first driving transistor, the 汲 terminal is coupled to the clock terminal, and the source terminal is coupled to the first The output terminal, and the gate terminal of the first driving transistor is coupled to the corresponding compensation circuit together with the source terminal of the buffer transistor. The scan line driver of claim 12, wherein each of the translation registers comprises: a buffer transistor, wherein the drain terminal and the gate terminal are coupled to each other and receive a start signal, and the source terminal And coupled to the corresponding compensation circuit and coupled to the first terminal of the first pull-down transistor; a reset transistor, the gate of which is coupled to the reset terminal, the source terminal is grounded, and the drain terminal is coupled to the buffer The circuit is coupled to the corresponding compensation circuit and coupled to the first terminal of the first pull-down transistor; a first driving transistor is coupled to the clock terminal, and the source terminal is coupled to the first output End, and the gate terminal of the first driving transistor is The source terminals of the buffer transistor are commonly coupled to the corresponding compensation circuit; and a second driving transistor having a drain terminal and a gate terminal coupled to the drain terminal and the gate terminal of the first driving transistor, respectively, and the second driving circuit The source terminal of the crystal is coupled to the second output. The scan line driver of claim 13, wherein the low voltage potential is a ground potential. The scan line driver of claim 12, wherein each of the compensation circuits comprises: a first memory operating transistor, the first terminal is coupled to a first operating voltage, and the gate terminal is coupled to a memory reset signal. The source terminal is coupled to the gate terminal of the corresponding first pull-down transistor; the second memory-operated transistor has a gate terminal coupled to a memory start signal, and a drain terminal coupled to the first memory operation circuit a source terminal of the crystal; a third memory operating transistor having a gate terminal and a source terminal coupled to the 汲 terminal and the source terminal of the second memory operating transistor, respectively, and the 汲 terminal of the third operating transistor is coupled to Corresponding first output end; a fourth memory operation transistor, the source terminal is grounded, the gate terminal receives the memory reset signal; a fifth memory operation transistor, the source terminal is grounded, and the gate terminal is coupled to the memory And a memory capacitor, the first end is coupled to the gate terminal of the corresponding first pull-down transistor, and the second end is coupled to the fourth memory operating transistor and the fifth memory operating transistor Extremely extreme. A scan line driver as described in claim 12, Each of the compensation circuits includes: a first memory operation transistor, wherein the first terminal is coupled to a first operating voltage, the gate terminal is coupled to a memory reset signal, and the source terminal is coupled to the corresponding first pull-down transistor. a second memory operating transistor having a gate terminal coupled to a memory start signal and a drain terminal coupled to a source terminal of the first memory operating transistor; a third memory operating transistor; The gate terminal and the source terminal are respectively coupled to the 汲 terminal and the source terminal of the second memory operating transistor, and the 汲 terminal of the third operating transistor is coupled to the corresponding first output terminal; a fourth memory operating transistor The source is extremely grounded, and the gate terminal receives the memory reset signal; a fifth memory operation transistor has a source terminal grounded, and a gate terminal coupled to the memory start signal; a memory capacitor, the first terminal is coupled To a gate terminal of the corresponding first pull-down transistor, a second terminal is coupled to the fourth memory operating transistor and a drain terminal of the fifth memory operating transistor; a first compensation operating transistor, the source terminal is grounded Its gate extreme coupling Corresponding to the 汲 extreme of the first pull-down transistor; a second compensation operating transistor, the 汲 terminal is coupled to a second operating voltage, and the source terminal is coupled to the first compensation operating transistor, the fourth memory Operating the transistor, the 汲 terminal of the fifth memory operating transistor; a third compensation operating transistor, wherein the 汲 terminal and the gate terminal are coupled to the second operating voltage, and the source terminal is coupled to the second compensation operating transistor Gate extreme; and A fourth compensation operating transistor, the source terminal of which is connected to the gate terminal of the first compensation operating transistor and the second compensation operating transistor, respectively. The scan line driver of claim 12, wherein each of the compensation circuits comprises: a first memory operating transistor, the first terminal is coupled to a first operating voltage, and the gate terminal is coupled to a memory reset signal. The source terminal is coupled to the gate terminal of the corresponding first pull-down transistor; the second memory-operated transistor has a gate terminal coupled to a memory start signal, and a drain terminal coupled to the first memory operation circuit a source terminal of the crystal; a third memory operating transistor having a gate terminal and a source terminal coupled to the 汲 terminal and the source terminal of the second memory operating transistor, respectively, and the 汲 terminal of the third operating transistor is coupled to Corresponding first output end; a fourth memory operation transistor, the source terminal is grounded, the gate terminal receives the memory reset signal; a fifth memory operation transistor, the source terminal is grounded, and the gate terminal is coupled to the memory a start capacitor; a memory capacitor, the first end is coupled to the gate terminal of the corresponding first pull-down transistor, and the second end is coupled to the fourth memory operating transistor and the fifth memory operating transistor Extreme Compensating the operating transistor, the source of which is extremely grounded, the gate terminal of which is coupled to the 汲 terminal of the corresponding first pull-down transistor; the second compensation operating transistor, the 汲 terminal is coupled to a second operating voltage, and the source terminal thereof And coupling the first compensation operation transistor, the fourth note Recalling the operating transistor, the 汲 terminal of the fifth memory operating transistor; a third compensation operating transistor, the 汲 terminal and the gate terminal are coupled to the second operating voltage, and the source terminal is coupled to the second compensation operating circuit a gate terminal of the crystal; a fourth compensation operation transistor, the source terminal is grounded, and the gate terminal and the gate terminal are respectively coupled to the gate terminals of the first compensation operation transistor and the second compensation operation transistor; a sixth memory operation a transistor whose source is extremely grounded, a gate terminal coupled to the memory reset signal, and a drain terminal coupled to a drain terminal of the fourth compensation operating transistor; and a seventh memory operating transistor having a gate extreme coupling The memory start signal is connected, and the source terminal and the drain terminal are respectively coupled to the source terminal and the drain terminal of the sixth memory operating transistor. A compensation circuit is applicable to a translation register, and the translation register has a plurality of pull-down transistors, and the translation register has a first output end, and the compensation circuit comprises: a first memory circuit, coupled Connecting the pull-down transistors and receiving a memory reset signal and a memory start signal; a second memory circuit coupled to the pull-down transistors and receiving the memory reset signal and the memory start signal; a first capacitor is coupled to the gate terminals of the pull-down transistors, and a second terminal is coupled to the second memory circuit for memorizing the threshold voltages of the pull-down transistors; and a compensation driving circuit coupled Connecting the first memory circuit and the second memory a circuit, wherein the first memory circuit and the second memory circuit have a compensation voltage between a gate to a source of each of the pull-down transistors according to the memory reset signal and the memory start signal Ingredients. The compensation circuit of claim 22, wherein the compensation voltage is low when the output of the first output is high, and is high when the output of the first output is low. The compensation circuit of claim 22, wherein the pull-down transistors comprise at least a first pull-down transistor and a second pull-down transistor. The compensation circuit of claim 22, wherein the first memory circuit comprises: a first memory operating transistor, wherein the first terminal is coupled to a first operating voltage, and the gate terminal is coupled to a memory reset signal. The source terminal is coupled to the gate terminal of the first pull-down transistor; a second memory operating transistor has a gate terminal coupled to a memory start signal, and a drain terminal coupled to the first memory operating transistor And a third memory operating transistor having a gate terminal and a source terminal coupled to the 汲 terminal and the source terminal of the second memory operating transistor, respectively, and the 汲 terminal of the third operating transistor is coupled to The first output end is coupled to the 汲 terminal of the second pull-down transistor. The compensation circuit of claim 22, wherein the second memory circuit comprises: a fourth memory operating transistor, the source terminal is grounded, and the gate terminal is connected Receiving a memory reset signal; and a fifth memory operating transistor having a source terminal grounded, a gate terminal coupled to a memory start signal, and a drain terminal connected to a drain terminal of the fourth memory operating transistor, and The second end of the memory capacitor is coupled. The compensation circuit of claim 22, wherein the compensation driving circuit comprises: a first compensation operating transistor, the source terminal is coupled to a low voltage, and the gate terminal is coupled to the first pull-down transistor a second compensation operating transistor, the 汲 terminal is coupled to a second operating voltage, and the source terminal is coupled to the first compensation operating transistor, the fourth memory operating transistor, and the fifth memory operation a 补偿 terminal of the transistor; a third compensation operating transistor, the 汲 terminal and the gate terminal are coupled to the second operating voltage, and the source terminal is coupled to the gate terminal of the second compensation operating transistor; and a fourth Compensating the operating transistor, the source terminal is grounded, and the gate terminal and the drain terminal are respectively coupled to the gate terminals of the first compensation operating transistor and the second compensation operating transistor. The compensation circuit of claim 22, further comprising a third memory operation circuit, comprising: a sixth memory operation transistor, wherein a source terminal is coupled to the low voltage, and a gate terminal is coupled to the memory weight a signal signal, and the other end is coupled to the 汲 terminal of the fourth compensation operating transistor; and a seventh memory operating transistor, the gate terminal of which is coupled to the memory start signal, and the source terminal and the 汲 terminal are respectively The source terminal and the 汲 terminal of the sixth memory operating transistor are coupled.