TWI392913B - Touch panel - Google Patents

Description

Touch panel

The present invention relates to a touch panel, and more particularly to the setting of a signal readout line of a touch panel.

The conventional touch panel can be divided into a capacitive sensing or a resistive sensing. The capacitive touch panel determines the position of the finger touch by detecting the capacitance generated between the touch panel and the sensing electrode, and the resistive touch The panel presses the panel with a finger, so that the electrodes of the touch sensing structure in the touch panel are short-circuited with each other, and the sensing thin film transistor is electrically connected to the pressing sensing structure, and the signal reading line and the sensing film are used. The transistor is connected to read the pressing sensing signal to determine the position of the finger pressing.

Please refer to FIG. 1 , which is a plan view showing a conventional resistive touch panel having a plurality of sub-pixel regions 18 , which are composed of two adjacent straight data lines 10 and two phases. The adjacent straight scanning line 11 is defined, and each sub-pixel area 18 has a display film transistor 12, and the display film transistor 12 is electrically connected to the straight data line 10. In addition, the conventional resistive touch panel further has a pressing sensing structure 15 electrically connected to the sensing thin film transistor 16 , and the sensing thin film transistor 16 of the same row in the touch panel is read by the signal The outgoing line 14 is connected to transmit the sensing signal to the integrated circuit.

In the conventional resistive touch panel, the signal readout line 14 is a linear (straight) conductive line (or a non-bent conductive line), so that the display film transistor 12 is blocked by the signal readout line 14, Can be set on the same side of the data line 10, can not be set to the left and right staggered (zigzag) configuration, so that the traditional resistive touch panel can not use dot inversion drive mode, can not achieve power saving effect.

Therefore, there is a need in the industry for a touch panel that can overcome the above problems and achieve power saving effects.

The present invention provides a touch panel having a plurality of pixel regions, including: a first substrate, the first conductive layer is disposed on the first substrate, the first conductive layer serves as a gate and a scan line; and the second conductive layer is disposed Above the first conductive layer, the second conductive layer serves as a source and a drain and a data line, wherein the data line and the scan line are alternately formed to form the pixel regions; and the third conductive layer is disposed on the second conductive layer. The third conductive layer is used as a common electrode; the pixel electrode is disposed on the third conductive layer, wherein the pixel electrode has a main block and at least one secondary block electrically insulated from the main block, and the main block is located In each pixel region, the secondary block covers a portion of the second conductive layer and a portion of the third conductive layer; and a curved signal readout line in the same row and adjacent two pixel regions Having different bending directions, wherein viewed from the upper viewing direction, the curved signal reading line is formed by interconnecting the first, second and third conductive layers with the secondary blocks of the pixel electrodes, and wherein the first The conductive layer is connected to the second conductive layer via a first via hole Connection, the secondary block of the pixel electrode via the second via holes are connected to the second conductive layer and the third layer is electrically conductive.

In addition, the present invention further provides a touch panel, comprising: a first substrate, the first patterned conductive layer is disposed on the first substrate, wherein the first patterned conductive layer comprises: a plurality of scan lines are arranged in a first direction, A plurality of first conductive electrodes connected in series, and a plurality of independent second conductive electrodes.

The second patterned conductive layer is disposed on the first substrate and above the first patterned conductive layer, wherein the second patterned conductive layer comprises: a plurality of data lines are arranged in a second direction, and are interlaced with the scan lines a plurality of pixel group groups, wherein each pixel group includes at least a first pixel region, a second pixel region, a third pixel region, and a fourth pixel region; at least one first source/dippole The pair is disposed in each of the pixel regions, and each source is electrically connected to each of the data lines; at least one third conductive electrode is disposed on each of the first conductive electrodes, above each of the second conductive electrodes, and first In the pixel region, the third conductive electrode located above each of the first conductive electrodes is electrically connected to each of the first conductive electrodes; and the at least one first conductive line is disposed in the first pixel region and the third pixel region. And electrically connecting the third conductive electrode located in the first pixel region and the third conductive electrode located above each of the first conductive electrodes; and the at least one second source/drain pair is disposed in the first pixel region, The second source is electrically connected to the first conductive line in the other pixel group.

The third patterned conductive layer is disposed on the first substrate and above the second patterned conductive layer, wherein the third patterned conductive layer comprises: at least one second conductive line is arranged parallel to one of the scan lines, at least one The three conductive lines cover a portion of each of the data lines, and the at least one fourth conductive line is disposed in the first pixel region, and covers a portion of the second source and a third conductive portion located in the first pixel region a part of the electrode.

The pixel electrode is disposed on the first substrate and above the third patterned conductive layer, wherein the pixel electrode comprises: a pixel electrode block disposed in each pixel region, and each of the first pixels in each pixel region a second electrically conductive electrode is covered and electrically connected to the third conductive electrode and the second source in the first pixel region; and the fifth conductive line is disposed in the second pixel region On the conductive electrode, the first conductive electrode, the first conductive line, the third conductive electrode, the fourth conductive line and the fourth conductive electrode form a ZigZag signal readout line.

In order to make the above objects, features, and advantages of the present invention more comprehensible, the following detailed description is made in conjunction with the accompanying drawings.

The invention provides a touch panel with a curved signal readout line. Therefore, the display thin film transistor connected to the same data line can be configured by using left and right interlacing, so that the touch panel can adopt dot inversion. The way to drive, and thus achieve the purpose of power saving.

Please refer to FIG. 2, which is a plan view showing a touch panel according to an embodiment of the invention. The touch panel has a plurality of sub-pixel regions 28 defined by two adjacent data lines 20 and two adjacent scan lines 40, each of which has at least one display film transistor 22 therein. . The range enclosed by the dotted line in FIG. 2 is a pixel area group 30, which includes a first pixel area 31, a second pixel area 32, a third pixel area 33, and a fourth pixel area 34. There are a plurality of pixel group groups 30 in the panel. Having at least one sensing thin film transistor 26 in the first pixel region 31, and a plurality of sensing thin film transistors 26 in the pixel group 30 of the same row utilizing a zigzag signal readout line 24 Connected, the curved signal readout line 24 has different bending directions in the same row and adjacent two pixel regions, such as pixel regions 31 and 33, and these different bending directions are in the same row and adjacent to each other. In the pixel region 31, for example, the pixel region 31 and the pixel region above it form an S-shaped shape, so that the display film transistor 22 in which the left and right sides are alternately arranged can be avoided, and the touch panel driven by dot inversion can be realized. Each of the display film transistors 22 is used to control the voltage on and off of the pixel electrodes (not labeled) of each pixel region 28.

In addition, there is at least one pressing sensing structure 25 in the second pixel area 32, which is connected to the sensing thin film transistor 26 in the other pixel group on the right side, in particular, another pixel area. The sensing thin film transistor 26 in the first pixel area 31 of the group receives the signal from the pressing sensing structure 25 and is electrically connected to the other signal readout line 24.

Viewed from the top view, the curved signal readout line 24 is composed of a first conductive layer (or first patterned conductive layer) 241, a second conductive layer (or second patterned conductive layer) 242, A third conductive layer (or third patterned conductive layer) 243 and a minor block 72 of a pixel electrode (not shown) are connected to each other. The first conductive layer 241 functions as a gate of the display film transistor 22 and a gate of the sensing film transistor 26 and the scan line 40, and the gate of the display film transistor 22 is connected to the corresponding scan line 40, and the sense The gate of the thin film transistor 26 is connected to the corresponding scan line 40. The second conductive layer 24 is disposed on the first conductive layer 241 as a source/drain of the thin film transistor 22 and a source/drain of the sensing thin film transistor 26 and the data line 20, and displays the thin film transistor The source/drain of 22 is connected to the corresponding data line 20, and the source/drain of the sensing thin film transistor 26 is connected to the corresponding data line 20. The third conductive layer 243 is disposed on the second conductive layer 24 as a common electrode, and the pixel electrode is disposed on the third conductive layer 243, and has a main block (not shown). It is disposed in each pixel region, and the primary block 72 is electrically insulated from the main block, and the secondary block 72 covers a portion of the second conductive layer 242 and a portion of the third conductive layer 243. The first conductive layer 241 is electrically connected to the second conductive layer 242 via the first via 49, and the secondary block 72 of the pixel electrode is respectively connected to the second conductive layer 242 and the third via the second via 62. The conductive layer 243 is electrically connected.

Next, please refer to FIGS. 3A to 3G, which are schematic diagrams showing process planes of the pixel group 30 of the touch panel according to an embodiment of the present invention, wherein the pixel group 30 includes the first pixel. The area 31, the second pixel area 32, the third pixel area 33, and the fourth pixel area 34. Referring to FIG. 3A, a first substrate (not shown) is first provided, which is, for example, a transparent substrate (eg, glass, quartz, other materials, or a combination thereof), a non-transparent substrate (eg, wafer, ceramic, Metal plate, opaque glass, opaque quartz, opaque polymer plate, other materials, or a combination of the above.) or a flexible substrate (eg, polyacrylic acid ester, polycarbonate, poly A first patterned conductive layer 310 is formed on the first substrate by styrene, polyfluorene, polyester, other materials, or a combination thereof. The first patterned conductive layer 310 includes a plurality of scan lines 40 arranged along the first direction X, a plurality of first conductive electrodes 241 connected in series, and a plurality of independent second conductive electrodes 46. In addition, the first patterned conductive layer 310 also functions as a gate 421 for displaying the thin film transistor 22, and a gate 422 for sensing the thin film transistor 26. As can be seen from FIG. 3A, the elements included in the first patterned conductive layer 310 are clearly shown in the respective pixel regions of the drawing without any doubt or understanding.

Referring to FIG. 3B, the semiconductor layer 48 is formed on the gate 421 of the display film transistor 22, and on the gate 422 of the sensing film transistor 26. Next, referring to FIG. 3C, a first via hole 49 is formed on the first conductive electrode 241 connected in series. Please note that the first via 49 is not formed in the material of the first conductive electrode. Please refer to the following FIG. 4C for a clear understanding.

Referring to FIG. 3D, a second patterned conductive layer 320 is formed on the first substrate and above the first patterned conductive layer 310. The second patterned conductive layer 320 includes a plurality of data lines 20 along the second direction. The arrays are interleaved with the scan lines 40 to form respective pixel regions 31, 32, 33 and 34. The second patterned conductive layer 320 further includes a first source/drain pair 52 disposed in each sub-pixel region, and each of the first source/drain pairs 52 is electrically connected to each of the data lines 20. In addition, the second patterned conductive layer 320 further includes a third conductive electrode 50 disposed on each of the first conductive electrodes 241, above each of the second conductive electrodes 46, and in the first pixel region 31, wherein each of the first conductive regions The third conductive electrode 50 above the conductive electrode 241 is electrically connected to each of the first conductive electrodes 241 via the first via 49. In addition, the second patterned conductive layer 320 further includes a first conductive line 242 disposed in the first pixel region 31 and the third pixel region 33 as a part of the curved signal connection line 24, wherein the first pixel is located in the first pixel. The first conductive line 242 in the region 31 is electrically connected to the third conductive electrode 50, and the first conductive line 242 located in the third pixel region 33 is electrically connected to the third conductive electrode located above the first conductive electrode 241. 50. Moreover, the first conductive lines 242 are interleaved with certain scan lines 40. The second patterned conductive layer 320 further includes a second source/drain pair 54 disposed in the first pixel region 31, and the second source is electrically connected to the first conductive line 242 in the other pixel region group. .

Referring to FIG. 3E, a third patterned conductive layer 330 is formed on the first substrate and above the second patterned conductive layer 320. The third patterned conductive layer 330 includes at least one second conductive line 60, parallel to One of the scan lines 40 is arranged; at least one third conductive line 61 covers a portion of each data line 20; at least one fourth conductive line 243 is disposed in the first pixel area 31 and covers the second source A portion of the pole 54 and a portion of the third conductive electrode 50 that is disposed in the first pixel region 31 serves as a portion of the curved signal connection line 24.

Referring to FIG. 3F, a second via hole 62 is formed on each of the first drain electrodes 52, on the second source/drain 54 and on the fourth conductive line 243 above the second source 54 at the third conductive line. The fourth conductive line 243 over a portion of the electrode 50 and the third conductive electrode 50 in the first pixel region 31. Please note that the second via hole 62 is not formed in the material of the first drain 52, the material of the second source/drain 54 , the material of the fourth conductive line 243 and the material of the third conductive electrode 50, please check The subsequent 4A and 4D diagrams will be understood.

Referring to FIG. 3G, a pixel electrode 340 is formed on the first substrate and above the third patterned conductive layer 330. The pixel electrode 340 includes a pixel electrode main block (or a pixel electrode block). 70 is disposed in each of the pixel regions, and is electrically connected to each of the first drain electrodes 52 in each of the pixel regions via the second via holes 62. The pixel electrode 340 further includes a fourth conductive electrode 72, which is a secondary block of the pixel electrode 340, and is electrically insulated from the main block 70 of the pixel electrode. The fourth conductive electrode 72 of the pixel electrode 340 covers a portion of the second source 54 and is electrically connected to the second source 54 via the second via 62. Further, the fourth conductive electrode 72 covers the other portion. The fourth conductive line above the second source. In addition, the fourth conductive electrode 72 also covers a portion of the third conductive electrode 50 in the first pixel region 31 and is electrically connected to the third conductive electrode 50 via the second via hole 62. In addition, the pixel electrode 340 further includes a fifth conductive line 74 disposed on the second conductive electrode 46 in the second pixel region 32. It should be noted that the fifth conductive line 74 is electrically connected to the second drain in the first pixel area 31 of the other pixel group, and the fifth conductive line 74 is in the same pixel group. It is not electrically connected to the second source/drain in the first pixel region 31. At this time, the fifth conductive line 74 is interlaced with some of the data lines 20.

The first conductive electrode 241, the first conductive line 242, the third conductive electrode 50, the fourth conductive line 243, and the fourth conductive electrode 72 constitute a curved signal readout line 24, and the curved signal readout lines 24 are in the same The row and adjacent two pixel regions have an S-shaped shape.

Although the dielectric layer between the conductive layers is not depicted in FIGS. 3A to 3G, there is a first dielectric layer 43 between the first conductive layer 310 and the second conductive layer, and a second conductive layer 320 and A third dielectric layer 45 is disposed between the three conductive layers 330, and a third dielectric layer 47 is disposed between the third conductive layer 330 and the pixel electrode 340. Therefore, the via holes described in the above embodiments are formed or protruded through the material of the dielectric layer.

Referring to Fig. 4A, which is a partial cross-sectional view showing the touch panel along section line A-A' in Fig. 3G, only the structure on the first substrate is depicted. First, a first patterned conductive layer 421 is formed on the first substrate 100 as a gate of the display thin film transistor 22, and then a first dielectric layer (or a gate insulating layer) is overlaid on the first patterned conductive layer 421. 43, then a semiconductor layer 48 is formed on the first dielectric layer 43, and the semiconductor layer 48 may include an undoped semiconductor layer 482 and a doped semiconductor layer 482. Next, a second patterned conductive layer 52 is formed on the semiconductor layer 48 as a first source/drain pair of the thin film transistor 22. Next, a second dielectric layer 45 (or a protective layer) is overlaid on the first source/drain pair 52, and a third dielectric layer 47 is formed on the second dielectric layer 45 in the second dielectric layer. The second via hole 62 is formed in the 45 and the third dielectric layer 47, and the pixel electrode 70 is formed on the third dielectric layer 47 and the second via hole 62, so that the first drain 52 and the pixel electrode 70 are formed. The main block is electrically connected. Furthermore, the present invention has a bottom gate type transistor as an embodiment, but is not limited thereto. In other embodiments, a top gate type transistor may also be used, which differs from the order in which the semiconductor layer 48 is formed on the first substrate 100, the order in which the gates are formed, and the number of dielectric layers. For example, after the bottom gate type transistor first forms the gate of the first patterned conductive layer 421, the dielectric layer 43 is overlaid on the first patterned conductive layer 421 and the first substrate 100. Then, a semiconductor layer 48 is formed over the dielectric layer 43 above the gate. The top gate type transistor first forms a semiconductor layer 48 on the first substrate 100, and then covers the dielectric layer 43 on the semiconductor layer 48 and the first substrate 100. Then, the gate of the first patterned conductive layer 421 is further formed on the dielectric layer 43 above the semiconductor layer 48. In the case of the top gate type transistor, in order to prevent the second patterned conductive layer on the first patterned conductive layer 421 and the first patterned conductive layer 421 from being short-circuited, except for the second dielectric layer 45 and the third dielectric layer In addition to the electrical layer 47, an additional dielectric layer (also referred to as an inner dielectric layer, not shown) is overlying the first patterned conductive layer 421 and the substrate 100. At this time, the first patterned conductive layer The second patterned conductive layer on 421 is located on different horizontal planes; or, without covering the additional dielectric layer, the gate of the first patterned conductive layer 421 is on the same horizontal plane as the second patterned conductive layer, but The two are separated and insulated from each other. Further, the required film layers are stacked, such as a second patterned conductive layer 52, a second dielectric layer 45, and a third patterned conductive layer (not shown in this A'-A cross-sectional view), and the third The electric layer 47 and the pixel electrode 70.

Please refer to FIG. 4B, which is a partial cross-sectional view showing the touch panel along section line B-B' in FIG. 3G. Having a first dielectric layer (or referred to as a gate insulating layer) 43 on the first substrate 100, a second patterned conductive layer 20 as a data line on the first dielectric layer 43, and a second patterned conductive The layer 20 is covered with a second dielectric layer (or referred to as a protective layer) 45. Forming a third conductive line 61 of the third patterned conductive layer on the second dielectric layer 45, then covering the third conductive layer 47 on the third conductive line 61, and forming a main block of the pixel electrode 70. On the three dielectric layers 47.

Referring to Fig. 4C, a partial cross-sectional view of the touch panel along section line C-C' in Fig. 3G is shown. a first conductive electrode 241 having a first patterned conductive layer on the first substrate 100, a first dielectric layer (or referred to as a gate insulating layer) 43 over the first conductive electrode 241, and a first dielectric a first via hole 49 is formed in the layer 43 , and then a third conductive electrode 50 forming a second patterned conductive layer covers the first dielectric layer 43 and the first via hole 49 and forms a second dielectric layer (or The first conductive electrode 241 of the first patterned conductive layer is electrically connected to the third conductive electrode 50 of the second patterned conductive layer via the first via hole 49.

Please refer to FIG. 4D, which is a partial cross-sectional view showing the touch panel along the section line D-D' in FIG. 3G. A first patterned conductive layer 422 is disposed on the first substrate 100 as a gate of the sensing thin film transistor 26, and a first dielectric layer (or a gate insulating layer) is covered on the first patterned conductive layer 422. 43, then forming a second patterned conductive layer 54 on the first dielectric layer 43 as a second source/drain pair of the sensing thin film transistor 26 and forming a second dielectric layer (or referred to as a protective layer) 45 covers the second source/drain pair 54. Then, a fourth conductive line 243 of the third patterned conductive layer is formed on a portion of the second dielectric layer 45, and a second via hole 62 is formed in the second dielectric layer 45 and the fourth conductive line 243, respectively. The fifth conductive line 74 forming the pixel electrode covers the second dielectric layer 45 and the fourth conductive line 243, and the second conductive via 62, wherein the fifth conductive line 74 of the pixel electrode passes through the second conductive via 62. The second source/drain pair 54 and the fourth conductive line 243 of the third patterned conductive layer are electrically connected to the second patterned conductive layer.

Please refer to FIG. 4E, which is a cross-sectional view showing the touch sensing structure 25 of the touch panel along the section line E-E' in FIG. 3G. a second conductive electrode 46 having a first patterned conductive layer on the first substrate 100, a first dielectric layer (or referred to as a gate insulating layer) 43 on the second conductive electrode 46, and then forming a second patterning The third conductive electrode 50 of the conductive layer is on the first dielectric layer 43 and covers the second dielectric layer (or referred to as a protective layer) 45 on the third conductive electrode 50. The first and second patterned conductive layers 46 and 50 and the first and second dielectric layers 43 and 45 constitute the sensing platform 101 of the pressing sensing structure 25.

In addition, the touch panel further includes a second substrate 200 disposed opposite to the first substrate 100, the second substrate 200 is, for example, a glass substrate, and the sensing spacer 201 is disposed on the second substrate 200, for example, a photosensitive spacer ( Photo spacer). The sensing spacer 201 is covered with a first transparent conductive layer 203, and the sensing platform 101 is covered with a second transparent conductive layer 74, which is a fifth conductive line of the pixel electrode, the first and second transparent The conductive layer may be a single layer or a multilayer structure, and the material thereof comprises: indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), aluminum tin oxide (ATO), indium antimony zinc oxide. The IGZO, other suitable materials, or a combination thereof, has a pitch P when the touch panel is not pressed, and contacts each other to form an electrical path (or short circuit) when the touch panel is pressed. At this point, the touch panel is completed, in which there is no other substance in the two substrates. In addition, if the touch display panel is to be formed, the touch panel may be externally attached to the display panel, wherein the display panel has a first substrate having an active component matrix layer, and includes a plurality of transistors, and the second substrate Corresponding to the first substrate, and a spacing between the two substrates and a display medium layer are disposed in the interval. If the touch panel is combined with the manufacturing process of the display panel to form an integrated touch display panel, a display medium layer 300 is further included between the first substrate 100 and the second substrate 200, so that the touch panel can be displayed. image. The material of the display medium layer comprises a non-self-luminous material (for example, a liquid crystal material, an electrophoretic material, other suitable materials or a combination thereof), a self-luminous material (for example, an organic luminescent material, an inorganic luminescent material, other suitable materials). Materials or combinations thereof, other suitable materials or combinations thereof. The display panel may include non-self-illuminating panels according to the material of the display medium layer (for example: liquid crystal display panel, three-dimensional display panel, electrophoretic display panel, blue phase display panel, horizontal switching display panel, vertical alignment display panel, double-sided display panel, other Suitable panels or combinations thereof, self-illuminating panels, other suitable panels, or combinations thereof.

Although the present invention has been disclosed in its preferred embodiments, it is not intended to limit the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application attached.

10, 20. . . Data line

11, 40. . . Scanning line

12, 22. . . Display thin film transistor

14. . . Signal readout line

15,25. . . Press sensing structure

16, 26. . . Sense thin film transistor

18, 28. . . Sub-pixel area

twenty four. . . Curved signal readout line

30. . . Pixel group

31. . . First pixel area

32. . . Second pixel area

33. . . Third pixel area

34. . . Fourth pixel area

310. . . First patterned conductive layer

241. . . First conductive electrode (first patterned conductive layer)

46. . . Second conductive electrode (first patterned conductive layer)

421. . . Display the gate of the thin film transistor (first patterned conductive layer)

422. . . Sensing the gate of the thin film transistor (first patterned conductive layer)

48. . . Semiconductor layer

49. . . First via

320. . . Second patterned conductive layer

242. . . First conductive line (second patterned conductive layer)

50. . . Third conductive electrode (second patterned conductive layer)

52. . . First source/drain pair (second patterned conductive layer)

54. . . Second source/drain pair (second patterned conductive layer)

330. . . Third patterned conductive layer

60. . . Second conductive line (third patterned conductive layer)

61. . . Third conductive line (third patterned conductive layer)

243. . . Fourth conductive line (third patterned conductive layer)

62. . . Second via

340. . . Pixel electrode

70. . . Main block of pixel electrode

72. . . Fourth conductive electrode of the pixel electrode

74. . . Fifth conductive line of the pixel electrode (second transparent electrode layer)

100. . . First substrate

481. . . Undoped semiconductor layer

482. . . Doped semiconductor layer

43. . . First dielectric layer

45. . . Second dielectric layer

47. . . Third dielectric layer

200. . . Second substrate

201. . . Sense spacer

203. . . First transparent conductive layer

101. . . Sensing platform

300. . . Display straight layer

P. . . spacing

X. . . First direction

Y. . . Second direction

Figure 1 is a schematic plan view showing a conventional resistive touch panel.

2 is a plan view showing a touch panel according to an embodiment of the present invention.

3A to 3G are schematic diagrams showing respective process planes for forming a pixel group of a touch panel according to an embodiment of the present invention.

4A to 4E are schematic cross-sectional views showing the touch panels along the hatching lines A-A', B-B', C-C', D-D', and E-E' in the 3G drawing, respectively.

20. . . Data line

40. . . Scanning line

twenty two. . . Display thin film transistor

25. . . Press sensing structure

26. . . Sense thin film transistor

28. . . Sub-pixel area

twenty four. . . Curved signal readout line

30. . . Pixel group

31. . . First pixel area

32. . . Second pixel area

33. . . Third pixel area

34. . . Fourth pixel area

241. . . First conductive electrode (first patterned conductive layer)

49. . . First via

242. . . First conductive line (second patterned conductive layer)

243. . . Fourth conductive line (third patterned conductive layer)

62. . . Second via

72. . . Fourth conductive electrode of the pixel electrode (secondary block)

Claims (14)

A touch panel having a plurality of pixel regions, comprising: a first substrate; a first conductive layer disposed on the first substrate, the first conductive layer serving as a gate and a scan line; a second conductive layer disposed on the first conductive layer, the second conductive layer as a source and a drain, and a data line, wherein the data line and the scan line are interlaced to form the pixel region; a third conductive layer disposed on the second conductive layer, the third conductive layer serving as a common electrode; a pixel electrode disposed on the third conductive layer, wherein the pixel electrode has a main block and at least a secondary block electrically insulated from the main block, the main block being located in each of the pixel regions, the secondary block covering one of the second conductive layer and one of the third conductive layers a portion; and a curved signal readout line having a different bend direction in the same row and adjacent two of the pixel regions, wherein the view is viewed from a top view direction Different bending directions are formed in the same row and in two adjacent pixel regions An S-shaped shape, and the curved signal readout line is formed by interconnecting the first, second, and third conductive layers and the secondary block of the pixel electrode, and wherein the first conductive layer is via the first conductive layer A first via is electrically connected to the second conductive layer, and the secondary block of the pixel electrode is electrically connected to the second conductive layer and the third conductive layer via a second via. The touch panel of claim 1, further comprising a plurality of display film transistors, wherein the display film transistors in the same row and adjacent to the two pixel regions are interlaced one by one Formal arrangement. For example, the touch panel described in claim 2, wherein the message The direction of the bend of the readout line is the position to avoid the display film transistors. The touch panel of claim 2, further comprising: a first dielectric layer disposed between the first conductive layer and the second conductive layer; a second dielectric layer disposed on the a second conductive layer and the third conductive layer; and a third dielectric layer disposed between the third conductive layer and the pixel electrode. The touch panel of claim 4, further comprising a semiconductor layer disposed between the first dielectric layer and the source and the drain to form the display film transistor. The touch panel of claim 4, further comprising: a second substrate disposed opposite the first substrate; and a pressing sensing structure disposed on the first substrate and the second substrate And the pressing sensing structure is electrically connected to the signal sensing line, and the pressing sensing structure comprises: a sensing spacer disposed on the first substrate; and a sensing platform disposed on the sensing Under the spacer; a first transparent conductive layer covering the sensing spacer and facing the sensing platform; and a second transparent conductive layer disposed on the sensing platform, wherein the first The transparent conductive layer and the second transparent conductive layer have a spacing when not pressed, and the second transparent conductive layer is the secondary block of the pixel electrode. The touch panel of claim 6, wherein the sensing platform comprises the first conductive layer and the second conductive layer. The touch panel of claim 7, wherein the sensing platform further comprises the first dielectric layer disposed on the first conductive layer, and the second dielectric layer disposed on the second conductive layer on. The touch panel of claim 6, further comprising a sensing thin film transistor that receives a signal from the pressing sensing structure and is electrically connected to the signal sensing line. The touch panel of claim 6, further comprising a display medium layer disposed between the first substrate and the second substrate. A touch panel includes: a first substrate; a first patterned conductive layer disposed on the first substrate, wherein the first patterned conductive layer comprises: a plurality of scan lines extending in a first direction; a plurality of first conductive electrodes connected in series; and a plurality of independent second conductive electrodes; a second patterned conductive layer disposed on the first substrate and above the first patterned conductive layer, wherein the The second patterned conductive layer includes: a plurality of data lines arranged in a second direction, and interlaced with the scan lines to form a plurality of pixel groups, wherein each of the pixel groups includes at least a first picture a prime region, a second pixel region, a third pixel region, and a fourth pixel region; at least one first source/dual pair, disposed in each pixel region, and each first source is electrically connected Each of the first conductive electrodes is disposed on each of the first conductive electrodes, above each of the second conductive electrodes, and in the first pixel region, wherein each of the first conductive electrodes is located The third conductive electrode is electrically connected to each of the first leads Electric electrode The at least one first conductive line is disposed in the first pixel region and the third pixel region, and electrically connected to the third conductive electrode located in the first pixel region and located in each of the first conductive regions The third conductive electrode above the electrode; and at least one second source/drain pair disposed in the first pixel region, the second source being electrically connected to the first pixel group a third conductive layer disposed on the first substrate and above the second patterned conductive layer, wherein the third patterned conductive layer comprises: at least one second conductive line parallel to the One of the scan lines is arranged; at least one third conductive line covering a portion of each of the data lines; and at least one fourth conductive line disposed in the first pixel region and covering the second source a portion of the third conductive electrode in the first pixel region; and a pixel electrode disposed on the first substrate and above the third patterned conductive layer, wherein the The pixel electrode includes: a pixel electrode block disposed in each of the pixel regions, and Each of the first drain electrodes is electrically connected to each of the pixel regions; a fourth conductive electrode is covered and electrically connected to the third conductive electrode in the first pixel region, and the second portion a fourth conductive line on the source and another portion of the second source; and a fifth conductive line disposed on the second conductive electrode in the second pixel region, wherein the first The conductive electrode, the first conductive line, the third conductive electrode, the fourth conductive line and the fourth conductive electrode form a ZigZag signal readout line, and the curved signal readout lines are in the same row and The adjacent two pixel regions have an S-shaped shape. The touch panel of claim 11, further comprising: a second substrate disposed opposite the first substrate; and a pressing sensing structure disposed on the first substrate and the second substrate And the pressing sensing structure is electrically connected to the signal sensing line, and the pressing sensing structure comprises: a sensing spacer disposed on the first substrate; and a sensing platform disposed on the sensing Under the spacer; a first transparent conductive layer covering the sensing spacer and facing the sensing platform; and a second transparent conductive layer disposed on the sensing platform, wherein the first The transparent conductive layer and the second transparent conductive layer have a spacing when not pressed, and the second transparent conductive layer is the fifth conductive line. The touch panel of claim 11, wherein the fifth conductive line is electrically connected to the second drain of the other pixel group. The touch panel of claim 11, further comprising a display medium layer disposed between the first substrate and the second substrate.