TWI392297B - Method and apparatus for baseline wander compensation in ethernet application - Google Patents

Description

Device and method for compensating baseline free

The present invention relates to a data transmission system, and more particularly to an apparatus and method for compensating for baseline freeness of a baseband transceiver system.

In the past two decades, the increase in computer computing power and the widespread popularity of the Internet have led to an increasing demand for processing, storage, and transmission of large amounts of data. In order to meet the increasing demand for data transmission between users, the transmission speed of Ethernet has evolved from 10 Mbps (megabits per second) to 10 Gbps (gigabits per second) since 1990. The IEEE 802.3 Task Force was established based on different application environments and goals to define various Ethernet specifications for facilitating the development of Ethernet in most regions.

The 100Mbps Fast Ethernet transmission technology of local area networks (LANs) is the most widely used application technology today, enabling high-speed data exchange between computers and electronic devices. In the next-generation computer system, the 1000Mbps Ethernet transmission device will replace the 100Mbps Ethernet transmission device and become a standard device. However, in the construction of the future information high-speed transmission network, the total bandwidth of the current backbone network will encounter bottlenecks. . Based on the above, in order to support higher bandwidth requirements in data transmission, the IEEE802.3an working group has developed a new 10Gbps transceiver system that uses a type 6 or 7 copper transmission line to support transmission links up to 100 meters. For detailed specifications, please refer to The IEEE initial specification P802.3an/D3.0. The 10Gbps Ethernet transmission device has been tested in 2006 and will be implemented in the data center to provide sufficient bandwidth for the backbone network in the initial phase.

Please refer to the first figure, which is a brief block diagram of the 10G Ethernet transceiver system. The 10G system supports more than 4 connector structures and 4 pairs of copper stranded transmissions. The transmission rate of each pair of transmission lines is 800M symbols per second (mega symbols/second), and each symbol represents 3.125 bits. In addition, each pair of transmission lines in the 10G system supports full-duplex operation. Therefore, as shown, a hybrid (Hybrid) 10 is coupled to the transceiver system and each pair of copper transmission lines 11. The 10G transceiver system includes two parts, and the first part is a transmitter for encoding and modulation from the host. The data is sent to the remote end; the other part is a receiver for demodulating and decoding the received signal, and sending the replied data to the host.

In the above, the transmission path further includes a Media Access Control (MAC) unit 12 for managing processing requirements and management connections from the host, and transmitting through a Medium Independent Interface (XGMII) 13 The data block is to the physical layer of the transceiver system. Then, one of the physical layer Physical Coding Sublayers (PCs) 14 scrambles the data bits transmitted by the media access control unit 12, and utilizes a low-density parity-check (LDPC) encoder. Encode the scrambled data bits. Finally, each 7-bit data in the encoded data stream is mapped to a 16-bit pulse-frequency amplitude modulation (16-PAM) symbol, and the 16-bit quasi-pulse amplitude modulation technique is used. The data bit is converted to a predetermined amplitude to improve the transmission efficiency of the bandwidth limited channel.

As shown, the 16-bit quasi-pulse amplitude modulation symbol is further processed by a Tomlinson-Harashima Precoder (THP) 16, which pre-equalizes the signal before transmitting the signal to compensate The signal is attenuated and distorted in the frequency selection channel. In addition, the pre-equalized digital symbols are converted into a continuous time series analog waveform by a digital-to-analog converter (DAC) 18, and the high frequency is converged via an analog filter 20 to respond. Limit high frequency emissions. Finally, the line driver 22 drives the analog waveform to be transmitted through the mixer 10 and the copper transmission line 11 to the corresponding receiver.

Next, the receiving path is described. On the receiving path, the mixer 10 receives the signal transmitted by the copper transmission line 11 to the 10G receiver, and then a front-end analog filter 24 removes the high-frequency signal component whose signal is outside the band of interest to prevent subsequent A sampled data sampled by an analog-to-digital converter (ADC) 28 is distorted. Before the analog-to-digital converter 28 samples the signal, a Programmable Gain Amplitude (PGA) 26 is used to adjust the range of the signal input to the analog digital converter 28, such that the analog converter 28 is The analog waveform received can be sampled and quantized, and the sampled digital sample data is output to a feed forward equalizer 29, which does not add noise during transmission.

In succession, the feedforward equalizer 29 processes the digital sample data to eliminate noise added to the signal during the previous transmission of the signal, and eliminates residual symbol interference (ISI) to increase the output at the output of the equalizer 29. Signal-to-noise ratio (SNR). After equalization, the equalized symbols are further transmitted to the receiving unit (not shown) of the entity encoding sublayer 14 in the form of a data bit sequence, and then decoded and descrambled by the low density parity detecting decoder to reply data. To the original data block. Finally, after the media access control unit 12 confirms the data block transmitted by the entity code sublayer 14, it will transmit to the host.

As shown in the first figure, the copper transmission line 11 and the Ethernet receiver are coupled together by the mixer 10 to support full-duplex operation. Therefore, when the transmitter transmits a signal to the corresponding receiver, the signal will pass through the copper transmission line 11 and the two mixers 10 before the receiver detects the signal. The mixer 10 used in the 10G Ethernet network is generally a transformer, and its frequency response is high frequency passage, so the loss will occur when the transmission energy is lower than the filter frequency of the transformer. Based on the characteristics of the above-mentioned high-frequency transmission of the transformer, such an effect that is not desired to be transmitted by the channel is generally referred to as Baseline Wander (BLW), which causes an imbalance in the DC code used in the baseband transmission system. situation. When a baseline free phenomenon occurs, the baseline of the transmitted signal will be shifted upward or downward based on the polarity of the previous and current transmitted symbols. If a symbol with continuous positive or negative polarity is transmitted over a short time interval, the transformer will block the low frequency energy carried in the transmitted signal, so that the signal waveform after the blocking will be trimmed at the receiver and will result in The bit is wrong and even shortens the length. Based on the above factors, the receiver must compensate for the baseline free phenomenon.

Based on the above factors, various techniques for eliminating the baseline free phenomenon of the baseband communication system have been proposed, such as the following: [1] US Patent No. 6,140,857, filed on March 29, 1999 by the name of the same. "Method an apparatus for reducing baseline wander".

[2] "Automatic gain control for communication receivers" by U.S. Patent Application Publication No. 2003/0142659 A1, filed on Jan. 25, 2002.

[3] "Digital base-band Receiver" of U.S. Patent No. 6,618,436, filed on June 7, <RTIgt;

[4] "Digital baseline wander correction circuit" of U.S. Patent No. 6,154,003, filed on Sep. 11, 1998.

[5] "Receiver for baseline wandering compensation" by Jyh-Ting Lai, filed on July 12, 2002, which is hereby incorporated by reference.

[6] J.H. Baek, J.H. Hong, M.H. Sunwoo and K.Y. Kim, "EFFICIENT DIGITAL BASELINE WANDER ALGORITHM AND ITS ARCHITECTRE FOR FAST ETHERNET", IEEE Signal Processing Systems, 2004.

[7] U.S. Patent Publication/Announcement Nos. 6433608, 6140857, 6415503, 6618436, 20030142659, 20030206604.

The above techniques can be classified into three groups, the first group being the above [1], as shown in the second figure, which is an analog domain estimation and compensation baseline free, which includes a baseline free compensation circuit 30, an analogy A digital converter 32, a feedforward filter (FFF) 34, an adder 35, a slicer 36, and a feedback filter (FBF) 38. This way of eliminating baseline detachment in the analog domain, while relaxing the design requirements of the analog-to-digital converter 32, is comparable to the above-described method of digital domain compensation [3]-[6]. The consumption is high, and the circuit occupies a large area of the chip. In order to improve the first mode, CLLing and GCChou proposed another compensation method in [2] above, which is to estimate the baseline free in the digital domain and eliminate the baseline free in the analog domain, which includes a baseline as shown in the third figure. The free compensation circuit 30, an analog-to-digital converter 32, a feedforward filter 34, adders 35 and 37, a wiper 36, and a feedback filter 38. This approach may provide a preferred solution to reduce baseline detachment, however, the closed loop delay between estimating and eliminating baseline detachment is too long to easily maintain loop stability. In addition, this approach adds hardware, such as a digital analog converter and a low pass filter to eliminate baseline detach in the analog domain.

The third group mode is to estimate and eliminate the baseline free in the digital domain, such as the above [3], and the baseline free compensation circuit, as shown in the fourth figure, includes a baseline free compensation circuit 30, an analog-to-digital converter 32, and a A feedforward filter 34, an adder 35, a wiper 36, and a feedback filter 38. The baseline free comparator 30 includes a delay unit 301 and an adder 303. As shown in the fourth figure, the baseline free compensation circuit 30 includes a simple pre-determination circuit that subtracts the received samples from the previous samples to produce correction data. This pre-judgment circuit compensates for the way the baseline is free, its hardware circuit is simple and reduces the mutual influence of the feedforward filter 34 and the baseline free compensation circuit 30. However, since the baseline is freed only by using the current symbol and the previous symbol, when the transmitted symbol has a small DC component, an error may occur in eliminating the DC offset. Therefore, using this method will cause the use of error estimates to correct the signal, which will have a bad impact.

In the above, other methods for estimating and eliminating baseline liberation in the digital domain are described above [4]-[6]. The simple block diagram includes a baseline free compensation circuit 30, an analog-to-digital converter 32, a feedforward filter 34, adders 35 and 37, a wiper 36, and a feedback filter 38, as shown in FIG. And a baseline free estimation circuit 39. The compensation method uses the error signal as the offset value of the estimated DC, and the error signal is the difference between the input device (dotted line) or the output (solid line) of the judging device (the cropper 36) and the feedforward filter 34, and The baseline is freed before the front end of the feedforward filter 34 (dashed line) or after the output. The digital compensation circuit mentioned above can be effectively implemented in today's digital circuit technology.

It is an object of the present invention to provide a baseline free compensation apparatus and method for improving the performance of a network transmission system.

One embodiment of the present invention discloses a baseline free compensation apparatus and method for use in a transmitter having a communication system of a Tomlinson-Holoshma precoder THP. The invention is more suitable for 10G Ethernet transmission applications. The invention comprises an external judging device (scratch) and an additional arithmetic unit, and the additional judging device is configured to generate DC offset information (error signal), and the additional arithmetic unit is arranged after the baseline free compensation circuit to recover the compensated The symbol is a 16-bit quasi-pulse amplitude modulation signal. In addition, the present invention generates a complex error signal based on the difference between the input of the baseline free compensation circuit and the output of the judging device, which is different from the conventional techniques [4]-[6]. The error signals can be further weighted to reduce the effects of incorrect DC information generated by the baseline free compensation circuit. In this way, an appropriate and accurate DC offset information can be obtained to improve the current estimate of incorrect baseline detachment.

In order to provide a better understanding and understanding of the structural features and the achievable effects of the present invention, the preferred embodiments and detailed descriptions are as follows: the above-mentioned conventional techniques are not applicable to the transmission. The device has a communication system of Tomlinson-Harashima Precoder (THP). The Tomlinson-Holoshma precoder THP includes an adder, a feedback filter and an arithmetic unit for pre-equalizing the filter of the transmitting end to all channel responses of the equalizer located at the corresponding receiver. . In order to maintain the sampled value of the Thomsonson-Holoshma precoder THP output, to avoid the sample value being greater than the acceptable input range of the subsequent digital analog converter (see the first figure), the arithmetic unit is used for the folding operation of Tomlinson-He Luoxu The sample value output by the digital precoder THP is such that the output sample value is between -16 and 16. Since the arithmetic unit is added to the transmitter, it is necessary to set the relative arithmetic unit to the equalizer of the receiver (refer to the first figure) to restore the symbol received by the receiver to the original 16-bit quasi-pulse amplitude modulation. symbol. For this reason, if the above-mentioned digital baseline free compensation method is used in the communication system with the Thomson-Holozma precoder THP, a compensation error will occur.

The following is an example of the above problem, and it is assumed below that no other noise is input to the receiver. If the symbol received by the receiver does not have a baseline free phenomenon, the receiver's arithmetic unit can correctly reply the received symbol to the initial predefined value. However, if the symbol after equalization has a baseline free and its original value is about 15 or -15, the value of the symbol with the baseline free equalization converted by the arithmetic unit will be approximately -15 or 15 Instead, it is the initial value. The value of this error will be processed by the subsequent marker, and the final judgment value is obtained, and an error signal is fed back to the aforementioned digital baseline estimation circuit, so the error signal will provide completely opposite DC deviation information, so It will make the conventional baseline free compensation worse, including bit errors. In order to solve this problem, the present invention proposes a novel baseline free compensation circuit for eliminating the baseline free phenomenon, and is particularly suitable for a baseband transceiver system having a Thomson-Holozma precoder THP.

Please refer to the sixth figure, which is a block diagram of a preferred embodiment of the baseline free compensation of the present invention, which is applied to a 10G Ethernet receiving system. As shown, it includes a distortion-proof analog filter 40 coupled in series, a programmable gain amplifier (PGA) 42, an analog-to-digital converter 44 (ADC), an equalizer 46, and a first The arithmetic unit 48, a baseline free compensation circuit 50 and a determination unit 60, and an embodiment of the determination unit 60 is a scriber. The baseline free compensation circuit 50 of the present invention includes a first scriber 52, an adder 53, a baseline estimator circuit 54, a baseline free compensator 56 and a second arithmetic unit 59 for compensating for baseline detachment. . In order to clearly illustrate the baseline free compensation of the present invention, the sixth figure does not show other conventionally necessary functional blocks, such as an echo canceller, a cross-talk canceller, a gain control unit, and a timing reduction unit. And an adaptation unit, etc.

First, the analog filter 40 suppresses the received high frequency signal component of a received signal to prevent distortion of the sampled data sampled by the subsequent analog digital converter 44. In addition, the programmable gain amplifier 42 adjusts the input amplitude of the filtered analog signal to produce an analog signal having an appropriate voltage amplitude, such as to conform to the dynamic range acceptable to the subsequent analog digital converter 44. The analog-to-digital converter 44 generates a digital signal according to the analog signal outputted by the programmable gain amplifier 42. After the analog digital converter 42 samples and quantizes the sign of the analog signal, the digital signal generated after the sampling is transmitted to the equalizer. 46, to compensate for the signal attenuated by the imperfect channel.

Since the transmitting end of the transmission system has an arithmetic unit, the receiving end must also be provided with an arithmetic unit 48, which is coupled to the equalizer 46, and then equalizes the extracted sampling symbols in the folding operation equalization signal, and is located at 16 and Between -16, driving between 16 and -16 is due to the 16-bit quasi-pulse amplitude modulation applied to the 10G Ethernet system. Finally, as in the case of the general receiving end, the symbols are restored by the tracer 60 to the original 16-bit quasi-pulse amplitude modulation symbol, which is a 16 unconnected value and is located between 15 and -15. . However, if the baseline free phenomenon affects the equalized symbols, the offset symbols will cause subsequent arithmetic unit 48 operations to produce incorrect results.

The following is an example for the above scenario. It is assumed that the symbol value originally transmitted by the transmitting end is 15 and has a DC offset due to the influence of the baseline free, and the baseline free is 1.2, so the symbol value is 16.2. After that, after the operation unit is operated, the affected symbol value will be converted to -15.8. This error result will cause the subsequent clipper 60 to generate an error judgment when judging the symbol, and determine that the DC offset is -0.8, and vice versa. At the correct DC offset of 1.2, this erroneous DC offset will be compensated back to the baseline free compensation circuit, which will make the system less efficient.

In order to improve the performance of the existing baseline free compensation circuit applied to 10G Ethernet applications, the present invention proposes a new architecture baseline free compensation circuit to compensate the baseband communication with the Thomson-Holozma precoder THP at the transmitting end. The baseline free phenomenon of the system. The baseline free compensation circuit 50 of the present invention includes a baseline freezer 56, a baseline free estimation circuit 54, an additional first scriber 52, an adder 53 and an additional second arithmetic unit 59, the baseline free compensation circuit of the present invention. 50 can be surely eliminated from baseline by the following treatment. The symbol in the input signal processed by the first operation unit 48 has a baseline free phenomenon. The present invention first compensates the symbol having the baseline free phenomenon in the input signal by the baseline free compensator 56, and the baseline free compensator 56 receives the input signal. And generating an output signal according to a compensation signal generated by the baseline free estimation circuit 54. One embodiment of the baseline free compensator 56 is an adder that subtracts the estimated baseline free from the baseline free symbol based on the compensation signal. Thereafter, the additional first scriber 52 generates a first slash signal according to the output signal generated by the baseline free compensator 56, and the first scriber 56 maps the compensated symbol in the output signal to a 16-bit quasi-pulse wave. The amplitude is modulated by a predefined value, and the possible pulse amplitude modulation value of the compensated symbol is predetermined.

The adder 53 is coupled between the baseline free compensator 56 and the first scriber 52 for generating an error signal err to estimate the baseline detachment, and the adder 53 inputs the input signal of the baseline free compensator 56. The symbol is subtracted from the pre-determined 16-bit quasi-pulse amplitude modulation value of the symbol of the first sliced signal to generate an error signal err. The baseline estimator circuit 54 is coupled between the adder 53 and the baseline free compensator 56, and uses the error signal err to estimate the offset level of the baseline, and generates a compensation signal to provide a baseline free compensator 56 estimate. It is then used to eliminate the baseline detachment of the next symbol. Finally, if the baseline free compensator 56 does eliminate the baseline freeness in the received symbol, the second computing unit 59 is coupled to an output of the baseline free compensator 56 and generates an adjustment signal according to the signal number, and the second operation unit 59 converts The compensated symbol in the output signal is the appropriate signal level. For example, if the compensated symbol is outside the range between 16 and -16, the folding operation must be performed to make the symbol within the range to avoid the subsequent second cropper. 60 The situation of misjudgment. The second scriber 60 generates a second slashing signal according to the adjustment signal.

Please refer to the seventh figure, which is a block diagram of a preferred embodiment of the baseline free estimation circuit 54 of the present invention. As shown, the baseline free estimation circuit 54 includes a weighting unit 57, a filtering circuit 58 having a filter 582 and a dividing circuit 584, and a delay unit 59. The filter 582 includes a complex delay unit 5822 and a complex addition unit 5824. The weighting unit 57 is coupled to the baseline free compensator 56 and the adder 53 (see the sixth figure) to generate a weighted signal according to the input signal and the error signal err. The filter circuit 58 accumulates the weighted signals generated at different times by the filter 582 and outputs a filtered signal to generate the compensation signal. The error signals err are transmitted to the weighting unit 57. The weighting unit 57 generates a weighting result according to the following rule: if the absolute value of the uncompensated symbol in the input signal is greater than a threshold, the error signal err and a weighting factor are used. c is multiplied to output, and the value of the weighting factor c is between 0 and 1. If the absolute value of the uncompensated symbol in the input signal is equal to or less than the threshold, the error signal err is directly output as an output; The above output is a weighted signal, and a preferred implementation of the threshold is 15.

The above rule mainly obtains a comparison relationship between the input signal and the threshold. If the comparison indicates a first situation, that is, the value of the input signal is greater than the threshold, the weighting signal is generated according to the weighting factor c and the error signal err. If the comparison indicates a second situation, that is, the value of the input signal is equal to or less than the threshold value, the output error signal err is a weighted signal. The weighting factor c is used to mitigate the influence of the error signal err, which may be incorrect, on the compensation signal. The incorrect error signal err is derived from the operation of the first operation unit 48 being affected by the baseline free and having an amplitude of about 16 or -16. Excessive offset symbols on the left and right. If the weighting factor c is not used, the incorrect error signal err usually provides a DC offset migration that is opposite to the correct DC offset value, which will result in a more severe baseline detachment of the symbol, which will seriously reduce the system's efficacy.

The output of the weighting unit 57 is transmitted to the shift averaging filter 582, which includes N-1 delay units 5822 and N summing units 5824 for estimating the baseline of the offset. The delay units 5822 are connected in series for outputting the weighting signals at different times; the adding units 5824 are also connected in series for adding the weighted signals generated at different times to calculate the sum and output For a filter signal. After the error signals err are processed by the low pass filtered shift average filter 582, only the significant DCs contained in the low frequency signal components are retained. The filtering signal is transmitted to the dividing circuit 584. The dividing circuit 584 divides the filtering signal by N to generate a compensation signal and transmits it to the baseline free estimation circuit 54 via the delay unit 59. The continuation unit 59 will delay one clock cycle. The baseline free compensator 56 subtracts the sign in the input signal from the baseline free estimate of a clock cycle delayed by delay unit 59 to eliminate baseline detachment and reconstruct a symbol that does not have baseline detachment.

In order to confirm that the baseline free compensation method of the present invention can effectively eliminate the baseline detachment, the present invention is simulated by using the 10G Ethernet application as an example (see IEEE P802.3an Draft 3.0), and the simulation results will be described below. The above simulation is to protect the type 6 transmission line, the transmission length is about 100 meters, the above-mentioned analog transmission power is 5dBm and the added noise is additive white Gaussian noise (AWGN) and exceeds the bandwidth. 800MHz, in addition to the number of equalizers is 128, and the number of Thomson-Holozma precoder THP is also 128.

Please refer to the eighth figure, which shows the simulation result of simulating the output of the first arithmetic unit 48 (refer to the seventh figure). It can be seen from the figure that the signal without the baseline free compensation is equalized by the equalizer 46. The sign is shifted up or down over time, and the signal-to-noise ratio (SNR) obtained at the output of the wiper is only 23.6 dB. For the continuation, please refer to the ninth figure, which shows the simulation results simulating the output compensated by the compensation method of the present invention. It can be clearly seen from the diagram that the baseline free phenomenon has been eliminated, and the calculated signal noise ratio SNR can reach 33.8. dB, so effectively reducing the bit error rate significantly. It can be seen from the above simulation results that the compensation method of the present invention can increase the signal-to-noise ratio SNR by more than 10 dB, and can reduce the influence of the incorrect compensation result. The DC offset information provided by the incorrect compensation result is opposite to the correct DC offset. . In addition, since the compensation method of the present invention compensates in the digital domain, power consumption can be saved and the area occupied by the wafer can be reduced, and the wafer area can be effectively utilized, and the feedback loop delay is small, so that the stability of the system can be easily performed.

However, the above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and the shapes, structures, features, and spirits described in the claims are equivalently changed. Modifications are intended to be included in the scope of the patent application of the present invention.

10. . . mixer

11. . . Copper transmission line

12. . . Media access control unit

13. . . Media independent interface

14. . . Entity coding sublayer

16. . . Tomlinson-Holoshma precoder

18. . . Digital analog converter

20. . . Analog filter

twenty two. . . Line driver

twenty four. . . Analog filter

26. . . Programmable gain amplifier

28. . . Analog digital converter

29. . . Equalizer

30. . . Baseline free compensation circuit

301. . . Delay unit

303. . . Adder

32. . . Analog digital converter

34. . . Feedforward filter

35. . . Adder

36. . . Cutter

37. . . Adder

38. . . Feedback filter

39. . . Baseline free estimation circuit

40. . . Analog filter

42. . . Programmable gain amplifier

44. . . Analog digital converter

46. . . Equalizer

48. . . First arithmetic unit

50‧‧‧Baseline free compensation circuit

52‧‧‧First Cutter

53‧‧‧Adder

54‧‧‧Baseline Free Estimation Circuit

56‧‧‧Baseline free compensator

57‧‧‧weighting unit

58‧‧‧Filter circuit

582‧‧‧Filter

5822‧‧‧Delay unit

5824‧‧‧Addition unit

584‧‧‧Division circuit

59‧‧‧Delay unit

60‧‧‧Second cutting device

The first figure is a block diagram of a 10G Ethernet transceiver system of the prior art; the second diagram is a block diagram of a prior art; the third diagram is a block diagram of a prior art; and the fourth diagram is a block of the prior art. Figure 5 is a block diagram of a prior art free compensation; the seventh diagram is a block diagram of a baseline free estimation circuit of the present invention; The graph is a simulation result plot simulating the baseline free phenomenon without baseline free compensation; and the ninth graph is a simulation result simulating the baseline free phenomenon compensated by the baseline free compensation of the present invention.

40. . . Analog filter

42. . . Programmable gain amplifier

44. . . Analog digital converter

46. . . Equalizer

48. . . First arithmetic unit

50. . . Baseline free compensation circuit

52. . . First stroke

53. . . Adder

54. . . Baseline free estimation circuit

56. . . Baseline free compensator

59. . . Second arithmetic unit

60. . . Second cutter

Claims (17)

A baseline free compensation device includes: a baseline free compensator that receives an input signal and generates an output signal according to a compensation signal; all the wipers are coupled to the baseline free compensator, and generate all the strokes according to the output signal An adder coupled between the baseline free compensator and the scriber, and receiving the input signal and the severing signal to generate an error signal; and a baseline estimator circuit coupled to the signal The adder and the baseline free compensator generate the compensation signal according to the error signal. The compensation device of claim 1, wherein the baseline free estimation circuit comprises: a weighting unit coupled to the baseline free compensator and the adder, and generating a signal according to the input signal and the error signal And a filtering circuit coupled to the weighting unit and generating the compensation signal according to the weighting signal generated at different times. The compensating device of claim 2, wherein the filtering circuit further comprises: a filter coupled to the weighting unit, and accumulating the weighting signal generated at different times, and outputting a filtering signal; The dividing circuit is coupled to the filter and generates the compensation signal according to the filtering signal. The compensation device of claim 3, wherein the filter further comprises: a plurality of delay units coupled in series to output the weighted signals generated at different times; and a plurality of addition units coupled in series, plus The delay units output the weighted signals generated at different times to output the filtered signals. The compensating device of claim 1, further comprising: a first computing unit coupled to an input of the baseline free compensator, and generating the input signal according to a digital signal; and a second An arithmetic unit coupled to an output of the baseline free compensator and based on the output The signal produces an adjustment signal. An Ethernet receiver with a baseline free compensation device includes: an analog-to-digital converter that generates a digital signal according to a analog signal; an equalizer coupled to the analog digital converter and based on the digital The first computing unit is coupled to the equalizer and generates an input signal according to the digital signal; and a baseline free compensation circuit coupled to the first computing unit, the baseline is free The compensation circuit includes: a baseline free compensator that receives the input signal and generates an output signal according to a compensation signal; a first scriber coupled to the baseline free compensator and generates a first signal according to the output signal And an adder coupled between the baseline free compensator and the first clipper, and receiving the input signal and the first cut signal to generate an error signal; a baseline free estimate The circuit is coupled between the adder and the baseline free compensator, and generates the compensation signal according to the error signal; and a second computing unit coupled to the baseline Compensator, and generating an adjustment signal according to the output signal. The Ethernet receiver of claim 6, further comprising: a second scriber coupled to the second computing unit and generating a second slashing signal according to the adjusting signal. The Ethernet receiver according to claim 6, further comprising: an analog filter that filters a received signal to generate the filtered analog signal; and an amplifier coupled to the analog filter, And outputting the analog signal to the analog digital converter according to the filtered analog signal. The Ethernet receiver according to claim 6, wherein the baseline free estimation circuit comprises: a weighting unit coupled to the baseline free compensator and the adder, and according to the input signal and the The error signal generates a weighted signal; and a filter circuit is coupled to the weighting unit and generates the compensation signal according to the weighted signal generated at different times. The Ethernet receiver according to claim 9, wherein the filtering circuit further comprises: a filter coupled to the weighting unit, and accumulating the weighting signals generated at different times, and outputting a filtering And a dividing circuit coupled to the filter and generating the compensation signal according to the filtering signal. The Ethernet receiver according to claim 10, wherein the filter further comprises: a complex delay unit coupled in series to output the weighted signal generated at different times; and at least one adding unit, plus The delay units output the weighted signals generated at different times to output the filtered signals. . A method for compensating a baseline freely includes: receiving an input signal and generating an output signal according to a compensation signal; generating all the signal signals according to the output signal; receiving the input signal and the cutting signal to generate an error signal; The error signal generates the compensation signal. The method of claim 12, wherein the step of generating the compensation signal comprises: generating a weighted signal according to the input signal and the error signal; and generating the compensation signal according to the weighted signal generated at different times . The method of claim 13, wherein the step of generating the compensation signal according to the weighted signal generated at different times comprises: accumulating the weighted signal generated at different times, and outputting a filtered signal; The compensation signal is generated according to the filtered signal. The method of claim 14, wherein the step of outputting the filtering signal comprises: using a complex delay unit coupled in series, outputting the weighted signal generated at different times; and summing the delay unit outputs The filtered signal is generated by the weighted signal generated at different times. The method of claim 13, wherein the step of generating the weighted signal comprises: obtaining a comparison relationship between the input signal and a threshold value; wherein the comparison indicates a first situation, according to a weighting The factor and the error signal generate the weighted signal; and when the comparison indicates a second situation, the error signal is output as the weighted signal. The compensation method of claim 16, wherein the first situation indicates that the value of the input signal is greater than the threshold value, and the second situation indicates that the value is equal to or less than the threshold value.