TWI390851B - Spread-spectrum generator - Google Patents
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本發明關於一種展頻產生器,特別是關於一種可調整延遲時間的展頻產生器。The present invention relates to a spread spectrum generator, and more particularly to a spread spectrum generator with adjustable delay time.
在電子電路中,展頻產生器裝置通常被用來展開信號的頻率,以避免信號的能量集中於一特定頻率。並非用於展頻操作的時脈信號的頻率是一常數。上述時脈信號的能量集中於一信號頻譜頻調,而且其電磁干擾(electro-magnetic interference,EMI)是相當嚴重。對於多數電子裝置或封裝,電磁干擾是一普遍但討人厭的干擾,其可打斷、阻擋、衰減或限制裝置或整體電路的效能。In electronic circuits, spread spectrum generator devices are typically used to spread the frequency of the signal to avoid concentration of the signal's energy at a particular frequency. The frequency of the clock signal that is not used for the spread spectrum operation is a constant. The energy of the above clock signal is concentrated on a signal spectrum tone, and its electromagnetic-electromagnetic interference (EMI) is quite serious. For most electronic devices or packages, electromagnetic interference is a common but annoying disturbance that can interrupt, block, attenuate, or limit the performance of a device or an overall circuit.
為了避免由單一頻率的諧波的電磁干擾,便施加展頻技巧。展頻代表調變一時脈信號的頻率以便將時脈信號的能量分配至更多頻譜頻調以降低時脈信號的電磁干擾。因此,上述展頻技巧是最為流行用以解決電磁干擾的方法中一種。In order to avoid electromagnetic interference from harmonics of a single frequency, spread spectrum techniques are applied. The spread spectrum represents the frequency of the modulated one-clock signal to distribute the energy of the clock signal to more spectral tones to reduce the electromagnetic interference of the clock signal. Therefore, the above-mentioned spread spectrum technique is one of the most popular methods for solving electromagnetic interference.
因此,本發明提供一種展頻產生器,其能夠藉由調整輸入信號的延遲時間而達到一輸入信號的頻率調變。Accordingly, the present invention provides a spread spectrum generator capable of achieving frequency modulation of an input signal by adjusting a delay time of an input signal.
本發明提供一種展頻產生器,包括一延遲模組及一控制模組。延遲模組被一第一控制信號控制以將一輸入信號延遲一延遲時間,並因此產生一延遲信號。控制模組耦接至延遲模組,用以偵測延遲信號的一第一邊緣,並因此產生第一控制信號。The invention provides a spread spectrum generator, which comprises a delay module and a control module. The delay module is controlled by a first control signal to delay an input signal by a delay time and thereby generate a delayed signal. The control module is coupled to the delay module for detecting a first edge of the delayed signal and thus generating the first control signal.
根據本發明之一實施例,其中延遲模組包括一數位類比轉換器及一第一電壓控制延遲裝置。數位類比轉換器將一數位信號轉換為一電壓控制信號,其中數位信號藉由根據第一控制信號查詢一查詢表而被得到。第一電壓控制延遲裝置接收輸入信號,耦接至數位類比轉換器,用以根據電壓控制信號調整延遲時間以便產生延遲信號。According to an embodiment of the invention, the delay module includes a digital analog converter and a first voltage controlled delay device. The digital analog converter converts a digital signal into a voltage control signal, wherein the digital signal is obtained by querying a lookup table based on the first control signal. The first voltage controlled delay device receives the input signal and is coupled to the digital analog converter for adjusting the delay time according to the voltage control signal to generate the delayed signal.
根據本發明之一實施例,延遲模組包括多個第一延遲格及一多工器。多個第一延遲格相繼地延遲輸入信號,以及分別產生多個候選延遲信號,其中每一第一延遲格被一電壓控制信號控制以將輸入信號延遲一延遲時間;以及多工器被第一控制信號控制以選擇候選延遲信號之一以當作延遲信號。According to an embodiment of the invention, the delay module includes a plurality of first delay grids and a multiplexer. The plurality of first delay cells successively delay the input signals and respectively generate a plurality of candidate delay signals, wherein each of the first delay cells is controlled by a voltage control signal to delay the input signal by a delay time; and the multiplexer is first The control signal controls to select one of the candidate delay signals to be treated as a delayed signal.
根據本發明之一實施例,展頻產生器更包括一延遲鎖相迴路電路。延遲鎖相迴路電路耦接至第一延遲格,用以將一延遲參考信號鎖定一參考信號,並產生電壓控制信號以調整每一第一延遲格的延遲時間。According to an embodiment of the invention, the spread spectrum generator further includes a delay phase locked loop circuit. The delay-locked loop circuit is coupled to the first delay grid for locking a delay reference signal to a reference signal and generating a voltage control signal to adjust a delay time of each of the first delay bins.
根據本發明之一實施例,延遲鎖相迴路電路包括多個第二延遲格、一相位偵測器及一電荷泵電路。其中多個第二延遲格相繼地延遲參考信號,並因此產生延遲參考信號,其中每一第二延遲格被電壓控制信號控制以將參考信號延遲延遲時間。相位偵測器,接收參考信號及延遲參考信號,並根據參考信號及延遲參考信號之間的一相位差產生一第二控制信號。電荷泵電路,根據第二控制信號,充電或放電並因此產生電壓控制信號。According to an embodiment of the invention, the delay phase locked loop circuit includes a plurality of second delay cells, a phase detector and a charge pump circuit. Wherein the plurality of second delay cells successively delay the reference signal and thus generate a delayed reference signal, wherein each second delay bin is controlled by the voltage control signal to delay the reference signal by a delay time. The phase detector receives the reference signal and the delayed reference signal, and generates a second control signal according to a phase difference between the reference signal and the delayed reference signal. The charge pump circuit charges or discharges according to the second control signal and thus generates a voltage control signal.
根據本發明之一實施例,控制模組包括一偵測單元及一計數單元。偵測單元偵測延遲信號的一第一邊緣,並產生一偵測信號。計數單元耦接至偵測單元,用以計數將被產生的偵測信號的數目並因此產生第一控制信號。According to an embodiment of the invention, the control module includes a detecting unit and a counting unit. The detecting unit detects a first edge of the delayed signal and generates a detecting signal. The counting unit is coupled to the detecting unit for counting the number of detecting signals to be generated and thus generating the first control signal.
在本發明中,展頻產生器延遲格結構為基礎並利用電壓控制延遲線(VCDL)結構。配合VCDL結構,展頻產生器能夠靈活地調整延遲時間。此外,由於本發明採用一查詢表(look-up table),我們能夠藉由更改查詢表中對應的數值而調整延遲時間。In the present invention, the spread spectrum generator is based on a delay lattice structure and utilizes a voltage controlled delay line (VCDL) structure. With the VCDL structure, the spread spectrum generator has the flexibility to adjust the delay time. Furthermore, since the present invention employs a look-up table, we can adjust the delay time by changing the corresponding value in the lookup table.
為讓本發明之上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。The above described features and advantages of the present invention will be more apparent from the following description.
現將詳細參考本發明之幾個示範性實施例,在附圖中說明所述幾個示範性實施例之實例。另外,凡可能之處,在圖式及實施方式中使用相同標號的元件/構件代表相同或類似部分。Reference will now be made in detail to the exemplary embodiments embodiments In addition, wherever possible, the same reference numerals in the drawings
圖1繪示為用於時脈信號的不同方式的展頻操作的一示意圖。請參照圖1,圖1說明三種展頻方法,其包括一下展方法,一上展方法,以及一中展方法。其中下展方法展開低頻譜,一原始時脈信號頻譜被標記為100,且一下展時脈信號頻譜被標記為101。例如,原始時脈信號具有一週期T,且下展方法將原始時脈信號的週期平移0到nTd,換句話說,已移時脈信號的週期具有從T到T+nTd的週期。另一方面,上展方法展開高頻譜,且一上展時脈信號頻譜被標記為102。例如,原始時脈信號具有一週期T,且上展方法將原始時脈信號的週期平移0到(-nTd),換句話說,已移時脈信號的週期具有從T到T-nTd的週期。此外,中展方法展開附近頻譜,且一中展時脈信號頻譜被標記為103。例如,原始時脈信號具有一週期T,且中展方法將原始時脈信號的週期平移(-nTd/2)到nTd/2,換句話說,已移時脈信號的週期具有從T-(nTd)/2到T+(nTd)/2的週期。1 is a schematic diagram of a spread spectrum operation for different modes of a clock signal. Please refer to FIG. 1. FIG. 1 illustrates three methods of spreading, including a method of abbreviating, a method of displaying, and a method of performing a center. The downscaling method expands the low spectrum, a raw clock signal spectrum is labeled as 100, and the abrupt clock signal spectrum is labeled 101. For example, the original clock signal has a period T, and the downscaling method shifts the period of the original clock signal by 0 to nTd, in other words, the period of the shifted clock signal has a period from T to T+nTd. On the other hand, the upscaling method expands the high spectrum and the spectrum of an up-going clock signal is labeled 102. For example, the original clock signal has a period T, and the upscaling method shifts the period of the original clock signal by 0 to (-nTd). In other words, the period of the shifted clock signal has a period from T to T-nTd. . In addition, the midamble method unfolds the nearby spectrum, and the spectrum of a midamble clock signal is labeled 103. For example, the original clock signal has a period T, and the midamble method shifts the period of the original clock signal (-nTd/2) to nTd/2, in other words, the period of the shifted clock signal has a period from T-( The period from nTd)/2 to T+(nTd)/2.
例如,圖2繪示為中展方法中的輸入信號的一展開範圍。請參照圖2,輸入信號的週期被從5Td到(-5Td)週期地展開。因此,為了降低輸入信號的電磁干擾,輸入信號的能量被分配至更廣頻率範圍。為了實現可執行上述展頻操作的電路,以下揭示數種根據本發明之實施例的電路。For example, Figure 2 illustrates an expanded range of input signals in the midamble method. Referring to FIG. 2, the period of the input signal is periodically expanded from 5Td to (-5Td). Therefore, in order to reduce the electromagnetic interference of the input signal, the energy of the input signal is distributed to a wider frequency range. In order to implement a circuit that can perform the above-described spread spectrum operation, several circuits according to embodiments of the present invention are disclosed below.
圖3繪示為根據本發明之一實施例的一展頻產生器的一電路圖。請參照圖3,展頻產生器300包括一延遲模組310及一控制模組。3 is a circuit diagram of a spread spectrum generator in accordance with an embodiment of the present invention. Referring to FIG. 3, the spread spectrum generator 300 includes a delay module 310 and a control module.
延遲模組310接收一輸入信號及一控制信號CON1,其中延遲模組310根據控制信號CON1將輸入信號延遲一延遲時間。被延遲模組310延遲的輸入信號被當作一延遲信號。控制模組320耦接至延遲模組310,且控制模組320接收延遲信號並根據第一邊緣產生控制信號CON1,例如,延遲信號的正邊緣。如圖4中所示,以下將說明控制模組320的另一可能實現方式。The delay module 310 receives an input signal and a control signal CON1, wherein the delay module 310 delays the input signal by a delay time according to the control signal CON1. The input signal delayed by the delay module 310 is treated as a delayed signal. The control module 320 is coupled to the delay module 310, and the control module 320 receives the delay signal and generates a control signal CON1 according to the first edge, for example, a positive edge of the delayed signal. As shown in FIG. 4, another possible implementation of the control module 320 will be described below.
圖4繪示為根據本發明之一實施例的控制模組的一電路圖。請參照圖4,展頻產生器400包括一延遲模組310及一控制模組420,其中控制模組420包括一偵測單元421及一計數單元422。偵測單元421接收延遲信號並偵測延遲信號的一第一邊緣,例如,延遲信號的正邊緣,及偵測單元421產生一偵測信號。計數單元422耦接至偵測單元421並接收由偵測單元421產生的偵測信號。此外,計數單元422計算偵測信號的數目,以判斷延遲信號目前位於哪一週期,計數單元422並產生一控制信號CON1以調整延遲模組310。4 is a circuit diagram of a control module in accordance with an embodiment of the present invention. Referring to FIG. 4 , the spread spectrum generator 400 includes a delay module 310 and a control module 420 . The control module 420 includes a detecting unit 421 and a counting unit 422 . The detecting unit 421 receives the delay signal and detects a first edge of the delayed signal, for example, a positive edge of the delayed signal, and the detecting unit 421 generates a detection signal. The counting unit 422 is coupled to the detecting unit 421 and receives the detection signal generated by the detecting unit 421. In addition, the counting unit 422 calculates the number of detection signals to determine which cycle the delay signal is currently in, and the counting unit 422 generates a control signal CON1 to adjust the delay module 310.
例如,圖5繪示為根據本發明之一實施例的展頻產生器中的輸入信號及延遲信號的一波形。請參照圖4及圖5,由延遲模組310接收的一輸入信號具有一週期T。當延遲模組310接收輸入信號的正邊緣,延遲模組310將輸入信號延遲一延遲時間Td並輸出已延輸入信號以作為延遲信號。另外,偵測單元421接收延遲信號並偵測延遲信號的正邊緣,接著偵測單元421產生一偵測信號。計數單元422計算偵測信號的數目,換句話說,一偵測信號被接收,並產生一控制信號CON1以調整延遲模組310的延遲時間,例如,延遲時間被調為2Td。延遲模組310根據控制信號CON1將輸入信號延遲輸入信號於每個正邊緣中不同的延遲時間,換句話說,根據控制信號CON1,延遲時間被選取,其中控制模組420接收延遲信號並計算延遲信號的正邊緣的數目,並因此產生一控制信號CON1。因此,當延遲模組310接收輸入信號的2nd 、3rd 、4th 、及5th 正邊緣,延遲模組310將輸入信號分別延遲延遲時間2Td、4Td、7Td及11Td,並輸出已延輸入信號以作為延遲信號。For example, FIG. 5 illustrates a waveform of an input signal and a delayed signal in a spread spectrum generator according to an embodiment of the present invention. Referring to FIG. 4 and FIG. 5, an input signal received by the delay module 310 has a period T. When the delay module 310 receives the positive edge of the input signal, the delay module 310 delays the input signal by a delay time Td and outputs the delayed input signal as a delayed signal. In addition, the detecting unit 421 receives the delay signal and detects the positive edge of the delayed signal, and then the detecting unit 421 generates a detecting signal. The counting unit 422 calculates the number of detection signals, in other words, a detection signal is received, and generates a control signal CON1 to adjust the delay time of the delay module 310, for example, the delay time is adjusted to 2Td. The delay module 310 delays the input signal by a different delay time in each positive edge according to the control signal CON1. In other words, according to the control signal CON1, the delay time is selected, wherein the control module 420 receives the delay signal and calculates the delay. The number of positive edges of the signal and thus a control signal CON1. Thus, when the delay module 310 receives the input signal of the 2 nd, 3 rd, 4 th , and 5 th positive edge of the input signal delay modules 310 each delay time 2Td, 4Td, 7Td and 11Td, and outputs the delay input The signal acts as a delayed signal.
如圖6中所示,以下將說明延遲模組310的另一可能實現方式。圖6繪示為根據本發明之一實施例的延遲模組的一電路圖。請參照圖6,展頻產生器600包括一延遲模組610及一控制模組320,其中延遲模組610包括一電壓控制延遲裝置611、一數位類比轉換器(DAC)612及一查詢表613,例如,控制模組320的功能與控制模組420相同。電壓控制延遲裝置611接收輸入信號並根據一電壓控制信號調整延遲時間CON2以便產生延遲信號。電壓控制延遲裝置611可將分別位於不同正邊緣的輸入信號予以延遲一已選取的延遲時間,以執行一展頻操作。因此,配合展頻操作所執行的輸入信號的頻率不是一常數而是頻率的一展開範圍。As shown in FIG. 6, another possible implementation of the delay module 310 will be described below. 6 is a circuit diagram of a delay module in accordance with an embodiment of the present invention. Referring to FIG. 6 , the spread spectrum generator 600 includes a delay module 610 and a control module 320 . The delay module 610 includes a voltage control delay device 611 , a digital analog converter (DAC ) 612 , and a lookup table 613 . For example, the function of the control module 320 is the same as that of the control module 420. The voltage control delay means 611 receives the input signal and adjusts the delay time CON2 in accordance with a voltage control signal to generate a delayed signal. The voltage controlled delay device 611 can delay the input signals respectively located at different positive edges by a selected delay time to perform a spread spectrum operation. Therefore, the frequency of the input signal performed in conjunction with the spread spectrum operation is not a constant but an unfolded range of frequencies.
數位類比轉換器612將一數位信號轉換為一電壓控制信號CON2,其中數位信號藉由根據控制信號CON1查詢查詢表613而被得到。例如,控制模組320可根據延遲信號的正邊緣的數目產生控制信號CON1。查詢表613接收控制信號CON1,且控制信號CON1被當作一索引以查詢查詢表613。接著,查詢表613根據查詢查詢表613的結果發送數位信號至數位類比轉換器612。The digital analog converter 612 converts a digital signal into a voltage control signal CON2, wherein the digital signal is obtained by querying the lookup table 613 based on the control signal CON1. For example, control module 320 can generate control signal CON1 based on the number of positive edges of the delayed signal. The lookup table 613 receives the control signal CON1, and the control signal CON1 is treated as an index to query the lookup table 613. Next, the lookup table 613 sends a digital signal to the digital analog converter 612 based on the result of the query lookup table 613.
值得一提的是,查詢表613根據控制信號CON1發送數位信號,其中數位信號及控制信號CON1之間的關係可不為一線性曲線。由於電壓控制延遲裝置611根據從數位信號轉換而來的電壓控制信號CON2而調整延遲時間,藉由改變數位信號及控制信號CON1之間的關係,我們可調整延遲時間。It is worth mentioning that the lookup table 613 sends a digital signal according to the control signal CON1, wherein the relationship between the digital signal and the control signal CON1 may not be a linear curve. Since the voltage control delay means 611 adjusts the delay time based on the voltage control signal CON2 converted from the digital signal, by changing the relationship between the digital signal and the control signal CON1, we can adjust the delay time.
請參照圖3,將於下述,如圖7中所示,說明延遲模組310的其他可能的實現方式的其中一種。圖7繪示為根據本發明之一實施例之延遲模組的一電路圖。請參照圖7,展頻產生器700包括一延遲模組710及一控制模組320,其中延遲模組710包括多個延遲格711及一多工器712。例如,控制模組320與控制模組420具有相同的功能。多個延遲格711相繼地將輸入信號延遲一延遲時間Td,並分別產生多個候選延遲信號,其中延遲時間Td可被一電壓控制信號Vtrl調整。多工器712被控制信號CON1控制以選擇候選延遲信號之一以當作延遲信號。換句話說,每一候選延遲信號具有不同的週期,從T+(nTd)/2到T-(nTd)/2,其中T是輸入信號的週期,以及n是由延遲格711的數目所決定。Referring to FIG. 3, one of the other possible implementations of the delay module 310 will be described below, as shown in FIG. 7 is a circuit diagram of a delay module in accordance with an embodiment of the present invention. Referring to FIG. 7 , the spread spectrum generator 700 includes a delay module 710 and a control module 320 . The delay module 710 includes a plurality of delay grids 711 and a multiplexer 712 . For example, the control module 320 has the same function as the control module 420. The plurality of delay cells 711 successively delay the input signal by a delay time Td and respectively generate a plurality of candidate delay signals, wherein the delay time Td can be adjusted by a voltage control signal Vtrl. The multiplexer 712 is controlled by the control signal CON1 to select one of the candidate delay signals as a delayed signal. In other words, each candidate delay signal has a different period, from T+(nTd)/2 to T-(nTd)/2, where T is the period of the input signal, and n is determined by the number of delay bins 711.
請參照圖7,展頻產生器700的其他可能的實現方式的其中一種更包括一延遲鎖相迴路電路,如圖8中所示。圖8繪示為根據本發明之一實施例之展頻產生器的一電路圖。請參照圖8,展頻產生器800包括一延遲模組710、一控制模組320以及一延遲鎖相迴路電路830,其中延遲模組710包括多個延遲格711及一多工器712。多個延遲格711相繼地將輸入信號延遲一延遲時間Td,並分別產生多個候選延遲信號,其中每一延遲格711被一電壓控制信號Vtrl控制以將輸入信號延遲一延遲時間Td。多工器712被控制信號CON1控制以選擇候選延遲信號之一以當作延遲信號。延遲鎖相迴路電路830耦接至延遲格711,以將一延遲參考信號(Dref)鎖定一參考信號(ref),並產生電壓控制信號Vtrl以調整每一延遲格711的延遲時間Td。Referring to FIG. 7, one of the other possible implementations of the spread spectrum generator 700 further includes a delay phase locked loop circuit, as shown in FIG. FIG. 8 is a circuit diagram of a spread spectrum generator in accordance with an embodiment of the present invention. Referring to FIG. 8 , the spread spectrum generator 800 includes a delay module 710 , a control module 320 , and a delay lock loop circuit 830 . The delay module 710 includes a plurality of delay grids 711 and a multiplexer 712 . The plurality of delay bins 711 successively delay the input signal by a delay time Td and respectively generate a plurality of candidate delay signals, wherein each of the delay bins 711 is controlled by a voltage control signal Vtrl to delay the input signal by a delay time Td. The multiplexer 712 is controlled by the control signal CON1 to select one of the candidate delay signals as a delayed signal. The delay-locked loop circuit 830 is coupled to the delay grid 711 to lock a delay reference signal (Dref) to a reference signal (ref) and to generate a voltage control signal Vtrl to adjust the delay time Td of each delay bin 711.
例如,延遲鎖相迴路電路830包括一N-間隔VCDL 831、一相位偵測器832以及一電荷泵電路833。N-間隔VCDL 831相繼地延遲參考信號並因此產生延遲參考信號,其中N-間隔VCDL 831被電壓控制信號Vtrl控制以將參考信號延遲一延遲時間。相位偵測器832接收參考信號及延遲參考信號,且相位偵測器832根據參考信號及延遲參考信號之間的一相位差以產生一控制信號CON2。電荷泵電路833根據控制信號CON2,充電或放電並因此產生該電壓控制信號。For example, the delay phase locked loop circuit 830 includes an N-spaced VCDL 831, a phase detector 832, and a charge pump circuit 833. The N-interval VCDL 831 successively delays the reference signal and thus produces a delayed reference signal, wherein the N-interval VCDL 831 is controlled by the voltage control signal Vtrl to delay the reference signal by a delay time. The phase detector 832 receives the reference signal and the delayed reference signal, and the phase detector 832 generates a control signal CON2 according to a phase difference between the reference signal and the delayed reference signal. The charge pump circuit 833 charges or discharges according to the control signal CON2 and thus generates the voltage control signal.
因此,我們能夠透過延遲鎖相迴路電路830調整延遲格711的延遲時間Td,且用於延遲鎖相迴路電路830的參考信號被當作一預設信號,其用以產生延遲格711的延遲時間Td。Therefore, we can adjust the delay time Td of the delay lattice 711 through the delay phase locked loop circuit 830, and the reference signal for delaying the phase locked loop circuit 830 is regarded as a preset signal for generating the delay time of the delay lattice 711. Td.
綜上所述,本發明所提供的展頻產生器藉由將輸入信號延遲一延遲時間而調整一輸入信號的頻率。配合展頻產生器,一單一頻率的諧波造成的EMI能夠被大幅降低。此外,一延遲鎖相迴路電路被施加以設定延遲模組的延遲時間,以使我們能夠藉由選擇延遲鎖相迴路電路的參考信號的週期而更改輸入信號的展開範圍。In summary, the spread spectrum generator of the present invention adjusts the frequency of an input signal by delaying the input signal by a delay time. In conjunction with the spread spectrum generator, EMI caused by a single frequency harmonic can be greatly reduced. In addition, a delay-locked loop circuit is applied to set the delay time of the delay module so that we can change the spread range of the input signal by selecting the period of the reference signal of the delay-locked loop circuit.
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,故本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.
100...原始100. . . original
101...下展101. . . Exhibition
102...上展102. . . Exhibition
103...中展103. . . Exhibition
310、610、710...延遲模組310, 610, 710. . . Delay module
320、420...控制模組320, 420. . . Control module
421...偵測單元421. . . Detection unit
422...計數單元422. . . Counting unit
611...電壓控制延遲裝置611. . . Voltage controlled delay device
612...DAC612. . . DAC
613...查詢表613. . . Query list
711...延遲格711. . . Delay lattice
712...多工器712. . . Multiplexer
830...延遲鎖相迴路電路830. . . Delayed phase-locked loop circuit
831...N-間隔VCDL831. . . N-spaced VCDL
832...相位偵測器832. . . Phase detector
833...電壓泵電路833. . . Voltage pump circuit
伴隨的圖式被包括以提供本發明之進一步的理解,以及被納入並組成此說明書的一部份。圖式說明本發明之實施例,配合實施方式,用以解釋本發明之精神。The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification. The drawings illustrate the embodiments of the invention and, in conjunction with the embodiments,
圖1繪示為用於時脈信號的不同方式的傳統展頻操作的一示意圖。1 is a schematic diagram of a conventional spread spectrum operation for different ways of clock signals.
圖2繪示為中展方法中的輸入信號的一展開範圍。Figure 2 illustrates an expanded range of input signals in the mid-expansion method.
圖3繪示為根據本發明之一實施例的一展頻產生器的一電路圖。3 is a circuit diagram of a spread spectrum generator in accordance with an embodiment of the present invention.
圖4繪示為根據本發明之一實施例的控制模組的一電路圖。4 is a circuit diagram of a control module in accordance with an embodiment of the present invention.
圖5繪示為根據本發明之一實施例的展頻產生器中的輸入信號及延遲信號的一波形。FIG. 5 is a diagram showing waveforms of an input signal and a delayed signal in a spread spectrum generator according to an embodiment of the present invention.
圖6繪示為根據本發明之一實施例的延遲模組的一電路圖。6 is a circuit diagram of a delay module in accordance with an embodiment of the present invention.
圖7繪示為根據本發明之一實施例之延遲模組的一電路圖。7 is a circuit diagram of a delay module in accordance with an embodiment of the present invention.
圖8繪示為根據本發明之一實施例之展頻產生器的一電路圖。FIG. 8 is a circuit diagram of a spread spectrum generator in accordance with an embodiment of the present invention.
320...控制模組320. . . Control module
710...延遲模組710. . . Delay module
711...延遲格711. . . Delay lattice
712...多工器712. . . Multiplexer
830...延遲鎖相迴路電路830. . . Delayed phase-locked loop circuit
831...N-間隔VCDL831. . . N-spaced VCDL
832...相位偵測器832. . . Phase detector
833...電壓泵電路833. . . Voltage pump circuit
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