TWI387143B - Control structure for active layer of transistors - Google Patents
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Description
本發明是有關於一種電子元件結構，且特別是有關於一種電晶體主動層控制結構。The present invention relates to an electronic component structure, and more particularly to a transistor active layer control structure.
目前有部分電晶體材料，如有機電晶體，不論是高分子(polymer)或是小分子，在經過黃光製程以及蝕刻製程進行圖案化之後會有元件特性劣化或是失效的狀況。因此，像有機電晶體一般常用的圖案化方式為噴印(ink-jet)或是金屬遮罩(shadow mask)這兩種。例如美國專利公開號US2009/007225是揭露一種藉由噴印方式作為主動層材料圖案化方法；或是，在美國專利公開號US2008/0135947揭露一種使用金屬遮罩定義主動層圖案的方法。At present, some of the transistor materials, such as organic transistors, whether they are polymers or small molecules, have deteriorated or failed component characteristics after being patterned by a yellow process and an etching process. Therefore, a patterning method commonly used like an organic transistor is an ink-jet or a shadow mask. For example, U.S. Patent Publication No. US-A-2009/007, 225, the disclosure of which is incorporated herein by reference in its entirety in its entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all
然而這兩種方法在應用於高解析面板或是高密度元件時都會遇到瓶頸。噴印方式往往會因為墨滴大小有其極限，所以無法應用到更小尺寸的元件。至於金屬遮罩的方式則會在製作金屬遮罩時因為開孔率愈小愈密集，而發生製作不易以及遮罩本身彎曲等問題。However, both methods encounter bottlenecks when applied to high resolution panels or high density components. Printing methods tend to be applied to smaller components because of the size of the ink droplets. As for the metal mask, the metal mask is made of a metal mask because the opening ratio is smaller and denser, and the production is difficult and the mask itself is bent.
本發明提供一種電晶體主動層控制結構，以提升主動層的解析度並且阻斷兩個或兩個以上電晶體之間的串音(crosstalk)。The present invention provides a transistor active layer control structure to enhance the resolution of the active layer and to block crosstalk between two or more transistors.
本發明提出一種電晶體主動層控制結構，用以控制兩個或兩個以上的電晶體。上述控制結構包括一控制電極以及一介電層，其中控制電極位在電晶體之間，以便在電晶體之間產生一反向偏壓，而介電層位在主動層與控制電極之間。The invention proposes a transistor active layer control structure for controlling two or more transistors. The control structure includes a control electrode and a dielectric layer, wherein the control electrode is positioned between the transistors to create a reverse bias between the transistors, and the dielectric layer is between the active layer and the control electrode.
在本發明之一實施例中，上述主動層包括有機或無機半導體材料。In an embodiment of the invention, the active layer comprises an organic or inorganic semiconductor material.
在本發明之一實施例中，上述控制電極的長度大於或等於主動層的長度。In an embodiment of the invention, the length of the control electrode is greater than or equal to the length of the active layer.
在本發明之一實施例中，上述控制電極包括一無機材料電極、一有機材料電極或一由有機無機材料混合或堆疊所組成的電極。上述無機材料電極包括導電金屬、合金或透明導電膜；上述有機材料電極包括PEDOT或導電高分子。In an embodiment of the invention, the control electrode comprises an inorganic material electrode, an organic material electrode or an electrode composed of an organic inorganic material mixed or stacked. The inorganic material electrode includes a conductive metal, an alloy or a transparent conductive film; and the organic material electrode includes PEDOT or a conductive polymer.
在本發明之一實施例中，上述電晶體包括一閘極、一源極與一汲極、該主動層以及一閘極絕緣層。In an embodiment of the invention, the transistor includes a gate, a source and a drain, the active layer, and a gate insulating layer.
在本發明之一實施例中，源極與汲極位在閘極上、閘極絕緣層位在閘極以及源極與汲極之間，至於主動層則位在源極與汲極上。In an embodiment of the invention, the source and drain electrodes are on the gate, the gate insulating layer is between the gate and the source and the drain, and the active layer is on the source and the drain.
在本發明之一實施例中，源極與汲極位在閘極上、閘極絕緣層位在閘極以及源極與汲極之間，且主動層位在閘極絕緣層以及源極與汲極之間。In an embodiment of the invention, the source and drain electrodes are on the gate, the gate insulating layer is between the gate and the source and the drain, and the active layer is in the gate insulating layer and the source and the gate. Between the poles.
在本發明之一實施例中，閘極位在源極與汲極上、閘極絕緣層位在閘極以及源極與汲極之間，至於主動層是位在閘極絕緣層以及源極與汲極之間。In an embodiment of the invention, the gate is at the source and the drain, the gate insulating layer is between the gate and the source and the drain, and the active layer is located at the gate insulating layer and the source and the gate. Between bungee jumping.
在本發明之一實施例中，源極與汲極位在主動層上、閘極位在源極與汲極上，而閘極絕緣層是位在閘極以及源極與汲極之間。In one embodiment of the invention, the source and drain electrodes are on the active layer, the gate is on the source and drain, and the gate insulating layer is between the gate and the source and drain.
在本發明之一實施例中，上述介電層就是閘極絕緣層。In an embodiment of the invention, the dielectric layer is a gate insulating layer.
在本發明之一實施例中，上述控制電極可與源極和汲極位於同一平面。In an embodiment of the invention, the control electrode may be in the same plane as the source and the drain.
在本發明之一實施例中，上述控制電極可與閘極位於同一平面。In an embodiment of the invention, the control electrode may be in the same plane as the gate.
在本發明之一實施例中，上述控制電極可位於閘極以及源極與汲極之間。In an embodiment of the invention, the control electrode can be located between the gate and the source and the drain.
在本發明之一實施例中，上述控制電極可位於閘極以及源極與汲極之上或之下。In an embodiment of the invention, the control electrode can be located above or below the gate and the source and drain.
在本發明之一實施例中，上述控制電極與閘極、源極與汲極在空間上可有重疊或是無重疊。In an embodiment of the invention, the control electrode and the gate, the source and the drain may or may not overlap in space.
在本發明之一實施例中，上述控制電極可被供給偏壓而作開或關的動作。In an embodiment of the invention, the control electrode can be biased to open or close.
基於上述，本發明主要是利用一個控制電極以及一個介電層作為控制主動層是否被圖案化的開關，這個控制結構可以有效降低習知的金屬遮罩以及噴印製程方式在高解析度下的需求，同時可輕易阻斷兩個或兩個以上電晶體之間的串音。此外，本發明之控制結構中的控制電極還可視電路設計需要進行開/關的動作。Based on the above, the present invention mainly utilizes a control electrode and a dielectric layer as a switch for controlling whether the active layer is patterned. This control structure can effectively reduce the conventional metal mask and the printing process at high resolution. Demand, while easily blocking crosstalk between two or more transistors. In addition, the control electrode in the control structure of the present invention can also perform an on/off action according to the circuit design.
為讓本發明之上述特徵能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。In order to make the above-described features of the present invention more comprehensible, the following detailed description of the embodiments will be described in detail below.
以下實施例僅是用來更詳細地描述本發明之應用，並附圖來作說明。然而，本發明還可採用多種不同形式來實踐，且不應將其解釋為限於下列所述之實施例。在圖式中，為明確起見可能將各層的尺寸及相對尺寸作誇飾，而未按尺寸比例繪製。The following examples are only intended to describe the application of the invention in more detail and are illustrated by the accompanying drawings. However, the invention may be practiced in many different forms and should not be construed as being limited to the embodiments described below. In the drawings, the dimensions and relative sizes of the various layers may be exaggerated for clarity and not drawn to scale.
圖1是依照本發明之第一實施例之一種電晶體主動層控制結構的剖面示意圖。BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross-sectional view showing a transistor active layer control structure in accordance with a first embodiment of the present invention.
請參照圖1，本實施例顯示在基底100上有兩個電晶體102。每個電晶體102包括一閘極104、一源極106a與一汲極106b、主動層108以及閘極絕緣層110，且這兩個電晶體102共有同一主動層108。圖1的源極106a與汲極106b位在閘極104上、閘極絕緣層110是位在閘極104以及源極106a與汲極106b之間，至於主動層108則位在源極106a與汲極106b上。而控制結構112則包括一控制電極114以及一介電層(在第一實施例中就是閘極絕緣層110)，其中控制電極114位在電晶體102之間，以便在電晶體102之間產生一反向偏壓，且控制電極114在圖1中是與閘極104位於同一平面。而介電層則是位在主動層108與控制電極114之間的閘極絕緣層110。如此一來，藉由相同解析度製作的主動層108，即可運用在更小尺寸的電晶體102上，且設計彈性也變大。因此，第一實施例之控制結構112適合用在有機電晶體的領域，不過即使是傳統的非晶矽半導體主動層亦可使用。Referring to FIG. 1, this embodiment shows two transistors 102 on a substrate 100. Each of the transistors 102 includes a gate 104, a source 106a and a drain 106b, an active layer 108, and a gate insulating layer 110, and the two transistors 102 share the same active layer 108. The source 106a and the drain 106b of FIG. 1 are located on the gate 104, the gate insulating layer 110 is located between the gate 104 and the source 106a and the drain 106b, and the active layer 108 is located at the source 106a. On the bungee 106b. The control structure 112 includes a control electrode 114 and a dielectric layer (in the first embodiment, the gate insulating layer 110), wherein the control electrode 114 is located between the transistors 102 to be generated between the transistors 102. A reverse bias, and the control electrode 114 is in the same plane as the gate 104 in FIG. The dielectric layer is a gate insulating layer 110 between the active layer 108 and the control electrode 114. In this way, the active layer 108 fabricated by the same resolution can be applied to the transistor 102 of a smaller size, and the design flexibility is also increased. Therefore, the control structure 112 of the first embodiment is suitable for use in the field of organic transistors, but even a conventional amorphous germanium semiconductor active layer can be used.
請繼續參照圖1，本實施例中的主動層108例如有機或無機半導體材料，如高分子(polymer-based)半導體材料等。控制電極114例如是一無機材料電極(如：導電金屬、合金或透明導電膜)、一有機材料電極(如：PEDOT或導電高分子)或一由有機無機材料混合或堆疊所組成的電極。此外，在第一實施例中，控制電極114可被供給偏壓而視元件需求或是電路設計需求作開或關的動作。雖然圖1只繪示兩個電晶體102，但本實施例並不限於此；換言之，控制結構112也可設置在兩個以上的電晶體之間。而且，圖1中的控制電極114雖然是與閘極104、源極106a與汲極106b在空間上無重疊，但本實施例並不限於此；換言之，控制電極114也可與閘極104、源極106a與汲極106b在空間上有重疊。With continued reference to FIG. 1, the active layer 108 in this embodiment is, for example, an organic or inorganic semiconductor material, such as a polymer-based semiconductor material. The control electrode 114 is, for example, an inorganic material electrode (such as a conductive metal, an alloy or a transparent conductive film), an organic material electrode (such as PEDOT or a conductive polymer), or an electrode composed of an organic inorganic material mixed or stacked. Further, in the first embodiment, the control electrode 114 can be supplied with a bias voltage to turn on or off depending on component requirements or circuit design requirements. Although FIG. 1 only shows two transistors 102, the embodiment is not limited thereto; in other words, the control structure 112 may be disposed between two or more transistors. Moreover, although the control electrode 114 in FIG. 1 is spatially non-overlapping with the gate 104, the source 106a and the drain 106b, the embodiment is not limited thereto; in other words, the control electrode 114 may be connected to the gate 104, The source 106a and the drain 106b overlap in space.
圖2是依照本發明之第二實施例之一種電晶體主動層控制結構的剖面示意圖。2 is a cross-sectional view showing a transistor active layer control structure in accordance with a second embodiment of the present invention.
請參照圖2，本實施例顯示在基底200上有兩個電晶體202以及位在電晶體202之間的控制結構212。電晶體202和第一實施例一樣包括閘極204、源極206a與汲極206b、主動層208以及閘極絕緣層210。第二實施例和第一實施例最大差異在於，控制結構212中的控制電極214和源極206a與汲極206b位於同一平面，且為隔開控制電極214與主動層208，控制結構212需包括介電層216。至於主動層208與控制電極214的選擇可參照第一實施例所述，於此不再贅述。Referring to FIG. 2, the present embodiment shows two transistors 202 on the substrate 200 and a control structure 212 positioned between the transistors 202. The transistor 202 includes the gate 204, the source 206a and the drain 206b, the active layer 208, and the gate insulating layer 210 as in the first embodiment. The greatest difference between the second embodiment and the first embodiment is that the control electrode 214 and the source 206a in the control structure 212 are in the same plane as the drain 206b, and the control electrode 214 and the active layer 208 are separated, and the control structure 212 needs to include Dielectric layer 216. The selection of the active layer 208 and the control electrode 214 can be referred to the first embodiment, and details are not described herein again.
圖3是依照本發明之第三實施例之一種電晶體主動層控制結構的剖面示意圖。3 is a cross-sectional view showing a transistor active layer control structure in accordance with a third embodiment of the present invention.
請參照圖3，本實施例和前幾個實施例一樣，在基底300上有兩個電晶體302及位在電晶體302之間的控制結構312。電晶體302包括閘極304、源極306a與汲極306b、主動層308以及閘極絕緣層310。第三實施例和第一實施例最大差異在於，控制結構312中的控制電極314位於閘極304及源極306a與汲極306b之上，且控制結構312也具有一層介電層316，以隔開控制電極314與主動層308。至於主動層308與控制電極314的選擇可參照第一實施例所述，於此不再贅述。Referring to FIG. 3, the present embodiment has two transistors 302 and a control structure 312 positioned between the transistors 302 on the substrate 300 as in the previous embodiments. The transistor 302 includes a gate 304, a source 306a and a drain 306b, an active layer 308, and a gate insulating layer 310. The greatest difference between the third embodiment and the first embodiment is that the control electrode 314 in the control structure 312 is located above the gate 304 and the source 306a and the drain 306b, and the control structure 312 also has a dielectric layer 316 to separate Control electrode 314 is opened with active layer 308. The selection of the active layer 308 and the control electrode 314 can be referred to the first embodiment, and details are not described herein again.
以上的第一至第三實施例之電晶體屬於反轉共平面式結構(又稱bottom-gate bottom-contact，BGBC結構)。The transistors of the above first to third embodiments belong to a reverse-coplanar structure (also referred to as a bottom-gate bottom-contact, BGBC structure).
圖4是依照本發明之第四實施例之一種電晶體主動層控制結構的剖面示意圖。4 is a cross-sectional view showing a transistor active layer control structure in accordance with a fourth embodiment of the present invention.
請參照圖4，第四實施例顯示在基底400上有兩個反轉堆疊式結構(又稱BGTC結構)之電晶體402，包括閘極404、源極406a與汲極406b、主動層408以及閘極絕緣層410，其中源極406a與汲極406b位在閘極404上、閘極絕緣層410是位在閘極404以及源極406a與汲極406b之間，且主動層408位在閘極絕緣層410以及源極406a與汲極406b之間。而控制結構412位在電晶體402之間，並包括一控制電極414以及一介電層，且前述介電層就是位在主動層408與控制電極414之間的閘極絕緣層410。再者，控制電極414在圖4中是與閘極404位於同一平面。由於控制電極414位在電晶體402之間，因此可藉由施加電壓而產生一反向偏壓，來阻斷電晶體402之間的電流，以免發生串音(crosstalk)。至於主動層408與控制電極414的選擇、電晶體402的個數、控制電極414與閘極404、源極406a與汲極406b在空間上有無重疊等可參照第一實施例所述，於此不再贅述。Referring to FIG. 4, the fourth embodiment shows a transistor 402 having two inverted stacked structures (also referred to as a BGTC structure) on a substrate 400, including a gate 404, a source 406a and a drain 406b, and an active layer 408. The gate insulating layer 410, wherein the source 406a and the drain 406b are located on the gate 404, the gate insulating layer 410 is located between the gate 404 and the source 406a and the drain 406b, and the active layer 408 is located at the gate. The pole insulating layer 410 is between the source 406a and the drain 406b. The control structure 412 is located between the transistors 402 and includes a control electrode 414 and a dielectric layer, and the dielectric layer is a gate insulating layer 410 between the active layer 408 and the control electrode 414. Furthermore, the control electrode 414 is in the same plane as the gate 404 in FIG. Since the control electrode 414 is located between the transistors 402, a reverse bias can be generated by applying a voltage to block the current between the transistors 402 to avoid crosstalk. The selection of the active layer 408 and the control electrode 414, the number of the transistors 402, the control electrode 414 and the gate 404, the source 406a and the drain 406b may be spatially overlapped, etc., as described in the first embodiment. No longer.
圖5是依照本發明之第五實施例之一種電晶體主動層控制結構的剖面示意圖。Figure 5 is a cross-sectional view showing a transistor active layer control structure in accordance with a fifth embodiment of the present invention.
請參照圖5，此一實施例顯示在基底500上有兩個電晶體502和位在其間的控制結構512。前述電晶體502和第四實施例一樣包括閘極504、源極506a與汲極506b、主動層508以及閘極絕緣層510。但第五和第四實施例之差異在於，控制結構512中的控制電極514是位於閘極504以及源極506a與汲極506b之間，且為隔開控制電極514與主動層508，尚需一層介電層516。至於主動層508與控制電極514的選擇可參照第一實施例所述，於此不再贅述。Referring to FIG. 5, this embodiment shows two crystals 502 and a control structure 512 positioned therebetween on the substrate 500. The foregoing transistor 502 includes a gate 504, a source 506a and a drain 506b, an active layer 508, and a gate insulating layer 510 as in the fourth embodiment. However, the difference between the fifth and fourth embodiments is that the control electrode 514 in the control structure 512 is located between the gate 504 and the source 506a and the drain 506b, and is spaced apart from the control electrode 514 and the active layer 508. A dielectric layer 516. The selection of the active layer 508 and the control electrode 514 can be referred to the first embodiment, and details are not described herein again.
圖6是依照本發明之第六實施例之一種電晶體主動層控制結構的剖面示意圖。Figure 6 is a cross-sectional view showing a transistor active layer control structure in accordance with a sixth embodiment of the present invention.
請參照圖6，本實施例和第四、第五實施例一樣，在基底600上有電晶體602及控制結構612，其中每個電晶體602都有閘極604、源極606a與汲極606b、主動層608以及閘極絕緣層610。而第六實施例與第四實施例不同的部分在於控制結構612中的控制電極614是位於閘極604及源極606a與汲極606b之上，並藉由形成在主動層608表面的一層介電層616，來與主動層608互相隔開。其餘構件的選擇可參照第一實施例所述。Referring to FIG. 6, in this embodiment, as in the fourth and fifth embodiments, a substrate 602 and a control structure 612 are provided on the substrate 600, wherein each of the transistors 602 has a gate 604, a source 606a and a drain 606b. The active layer 608 and the gate insulating layer 610. The sixth embodiment differs from the fourth embodiment in that the control electrode 614 in the control structure 612 is located above the gate 604 and the source 606a and the drain 606b, and is formed by a layer formed on the surface of the active layer 608. Electrical layer 616 is spaced apart from active layer 608. The selection of the remaining components can be referred to the first embodiment.
圖7是依照本發明之第七實施例之一種電晶體主動層控制結構的剖面示意圖。Figure 7 is a cross-sectional view showing a transistor active layer control structure in accordance with a seventh embodiment of the present invention.
請參照圖7，第七實施例顯示在基底700上有兩個直接堆疊式結構(又稱TGBC結構)之電晶體702，包括閘極704、源極706a與汲極706b、主動層708以及閘極絕緣層710，其中閘極704位在源極706a與汲極706b上、閘極絕緣層710位在閘極704以及源極706a與汲極706b之間，至於主動層708是位在閘極絕緣層710以及源極706a與汲極706b之間。而在電晶體702之間的控制結構712則包括一控制電極714以及一介電層716。再者，控制電極714在圖7中是與源極706a與汲極706b位於同一平面，所以在製程上可與源極706a與汲極706b同時製作。Referring to FIG. 7, a seventh embodiment shows a transistor 702 having two directly stacked structures (also referred to as TGBC structures) on a substrate 700, including a gate 704, a source 706a and a drain 706b, an active layer 708, and a gate. a pole insulating layer 710, wherein the gate 704 is located on the source 706a and the drain 706b, the gate insulating layer 710 is located between the gate 704 and the source 706a and the drain 706b, and the active layer 708 is located at the gate The insulating layer 710 and the source 706a and the drain 706b. The control structure 712 between the transistors 702 includes a control electrode 714 and a dielectric layer 716. Furthermore, the control electrode 714 is disposed on the same plane as the source 706a and the drain 706b in FIG. 7, so that it can be fabricated simultaneously with the source 706a and the drain 706b in the process.
請繼續參照圖7，位在電晶體702之間的控制電極714可被施加電壓而產生一反向偏壓，所以能夠阻斷電晶體702之間的電流，以免發生串音。至於主動層708與控制電極714的選擇、電晶體702的個數等可參照第一實施例所述，於此不再贅述。Referring to FIG. 7, the control electrode 714 located between the transistors 702 can be applied with a voltage to generate a reverse bias, so that the current between the transistors 702 can be blocked to avoid crosstalk. The selection of the active layer 708 and the control electrode 714, the number of the transistors 702, and the like can be referred to the first embodiment, and details are not described herein again.
圖8是依照本發明之第八實施例之一種電晶體主動層控制結構的剖面示意圖。Figure 8 is a cross-sectional view showing a transistor active layer control structure in accordance with an eighth embodiment of the present invention.
請參照圖8，此一實施例顯示在基底800上有兩個電晶體802和位在其間的控制結構812。前述電晶體802之閘極804、源極806a與汲極806b、主動層808以及閘極絕緣層810和第七實施例的位置關係相同。不過，在第八實施例中，控制結構812中的控制電極814是與閘極804位於同一平面，所以控制電極814在製程上可與閘極804同時製作；控制結構812中的介電層則是位在主動層808與控制電極814之間的閘極絕緣層810。至於主動層808與控制電極814的選擇可參照第一實施例所述，於此不再贅述。Referring to Figure 8, this embodiment shows two crystals 802 on the substrate 800 and a control structure 812 positioned therebetween. The gate 804 of the transistor 802, the source 806a and the drain 806b, the active layer 808, and the gate insulating layer 810 have the same positional relationship as the seventh embodiment. However, in the eighth embodiment, the control electrode 814 in the control structure 812 is in the same plane as the gate 804, so the control electrode 814 can be fabricated simultaneously with the gate 804 in the process; the dielectric layer in the control structure 812 is Is a gate insulating layer 810 between the active layer 808 and the control electrode 814. The selection of the active layer 808 and the control electrode 814 can be referred to the first embodiment, and details are not described herein again.
圖9是依照本發明之第九實施例之一種電晶體主動層控制結構的剖面示意圖。Figure 9 is a cross-sectional view showing a transistor active layer control structure in accordance with a ninth embodiment of the present invention.
請參照圖9，本實施例顯示在基底900上有兩個直接共平面式結構(又稱TGTC結構)之電晶體902以及位於電晶體902之間的控制結構912。其中，電晶體902的源極906a與汲極906b位在主動層908上、閘極904位在源極906a與汲極906b上，而閘極絕緣層910是位在閘極904以及源極906a與汲極906b之間。而控制結構912包括位在閘極904以及源極906a與汲極906b之下的一控制電極914，以及介於主動層908與控制電極914之間的一介電層916。由於控制電極914可被施加電壓而產生一反向偏壓，所以能夠阻斷電晶體902之間的電流，以免發生串音。至於主動層908與控制電極914的選擇、電晶體902的個數、控制電極914與閘極904、源極906a與汲極906b在空間上有無重疊等可等可參照第一實施例所述，於此不再贅述。Referring to FIG. 9, the present embodiment shows a transistor 902 having two direct coplanar structures (also referred to as TGTC structures) on the substrate 900 and a control structure 912 between the transistors 902. The source 906a and the gate 906b of the transistor 902 are located on the active layer 908, the gate 904 is located on the source 906a and the drain 906b, and the gate insulating layer 910 is located at the gate 904 and the source 906a. Between the bungee and the 906b. The control structure 912 includes a control electrode 914 located below the gate 904 and the source 906a and the drain 906b, and a dielectric layer 916 between the active layer 908 and the control electrode 914. Since the control electrode 914 can be applied with a voltage to generate a reverse bias, the current between the transistors 902 can be blocked to avoid crosstalk. The selection of the active layer 908 and the control electrode 914, the number of the transistors 902, the control electrode 914 and the gate 904, the source 906a and the drain 906b may be spatially overlapped, etc., as described in the first embodiment. This will not be repeated here.
圖10是依照本發明之第十實施例之一種電晶體主動層控制結構的剖面示意圖。Figure 10 is a cross-sectional view showing a transistor active layer control structure in accordance with a tenth embodiment of the present invention.
請參照圖10，在基底1000上有兩個電晶體1002和位在其間的控制結構1012。前述電晶體1002之閘極1004、源極1006a與汲極1006b、主動層1008以及閘極絕緣層1010和第九實施例的位置關係相同。而第十實施例與第九實施例之差異在於，控制結構1012中的控制電極1014是與閘極1004位於同一平面，且控制結構1012中的介電層就是位在主動層1008與控制電極1014之間的閘極絕緣層1010。至於主動層1008與控制電極1014的選擇可參照第一實施例所述，於此不再贅述。Referring to Figure 10, there are two transistors 1002 on the substrate 1000 and a control structure 1012 positioned therebetween. The gate 1004 of the transistor 1002, the source 1006a and the drain 1006b, the active layer 1008, and the gate insulating layer 1010 have the same positional relationship as the ninth embodiment. The difference between the tenth embodiment and the ninth embodiment is that the control electrode 1014 in the control structure 1012 is in the same plane as the gate 1004, and the dielectric layer in the control structure 1012 is located on the active layer 1008 and the control electrode 1014. Between the gate insulating layer 1010. The selection of the active layer 1008 and the control electrode 1014 can be referred to the first embodiment, and details are not described herein again.
為驗證本發明之效果，以第一實施例之控制結構為實驗對象，測量其控制電極之電壓變化以及兩電晶體電壓差異對於漏電流的影響。In order to verify the effect of the present invention, the control structure of the first embodiment was taken as an experimental object, and the voltage change of the control electrode and the influence of the difference of the two transistor voltages on the leakage current were measured.
【實驗】【experiment】
首先，準備一個如第一實施例的元件，其中包含兩個電晶體TFT1和TFT2。每個電晶體TFT1和TFT2包括厚度100nm的銦錫氧化物(ITO)作為閘極104、厚度100nm的ITO作為源極106a與汲極106b、厚度100nm的五環素(pentacene)作為主動層108、厚度150nm的氧化矽(SiO2 )作為閘極絕緣層110。而控制結構112則包括厚度100nm的ITO作為控制閘極114，其俯視圖如圖11所示。在圖11中，控制電極114的長度L1大於主動層108的長度L2，但本發明不限於此，L1也可等於L2，以加強使電晶體TFT1和TFT2之間無串音的效果。First, an element as in the first embodiment is prepared which contains two transistor TFT1 and TFT2. Each of the transistors TFT1 and TFT2 includes indium tin oxide (ITO) having a thickness of 100 nm as a gate electrode 104, ITO having a thickness of 100 nm as a source 106a and a drain 106b, and a pentacen having a thickness of 100 nm as an active layer 108. Cerium oxide (SiO 2 ) having a thickness of 150 nm is used as the gate insulating layer 110. The control structure 112 includes ITO having a thickness of 100 nm as the control gate 114, and its top view is as shown in FIG. In FIG. 11, the length L1 of the control electrode 114 is larger than the length L2 of the active layer 108, but the present invention is not limited thereto, and L1 may be equal to L2 to enhance the effect of preventing crosstalk between the TFTs TFT1 and TFT2.
然後，比較控制電極114電壓(Vc)變化以及兩電晶體102電壓(VT1T2 )差異對於漏電流之影響，結果如圖12所示。當控制閘極114呈浮置狀態時，漏電流連10-6 A左右，但是一旦對控制閘極114施加電壓，漏電流會下降4個次方(order)。因此，可知本發明能輕易阻斷兩個或兩個以上電晶體之間的串音，並且能視電路設計需要使控制結構112中的控制電極114進行開/關的動作。Then, the voltage (Vc) change of the control electrode 114 and the influence of the difference between the voltages of the two transistors 102 (V T1T2 ) on the leakage current are compared, and the result is shown in FIG. When the control gate 114 is in a floating state, the leakage current is about 10 -6 A, but once a voltage is applied to the control gate 114, the leakage current is lowered by 4 orders. Thus, it can be seen that the present invention can easily block crosstalk between two or more transistors and can cause the control electrode 114 in the control structure 112 to be turned on/off depending on circuit design requirements.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.
100、200、300、400、500、600、700、800、900、1000．．．基底100, 200, 300, 400, 500, 600, 700, 800, 900, 1000. . . Base
102、202、302、402、502、602、702、802、902、1002、TFT1、TFT2．．．電晶體102, 202, 302, 402, 502, 602, 702, 802, 902, 1002, TFT1, TFT2. . . Transistor
104、204、304、404、504、604、704、804、904、1004．．．閘極104, 204, 304, 404, 504, 604, 704, 804, 904, 1004. . . Gate
106a、206a、306a、406a、506a、606a、706a、806a、906a、1006a．．．源極106a, 206a, 306a, 406a, 506a, 606a, 706a, 806a, 906a, 1006a. . . Source
106b、206b、306b、406b、506b、606b、706b、806b、906b、1006b．．．汲極106b, 206b, 306b, 406b, 506b, 606b, 706b, 806b, 906b, 1006b. . . Bungee
108、208、308、408、508、608、708、808、908、1008．．．主動層108, 208, 308, 408, 508, 608, 708, 808, 908, 1008. . . Active layer
110、210、310、410、510、610、710、810、910、1010．．．閘極絕緣層110, 210, 310, 410, 510, 610, 710, 810, 910, 1010. . . Gate insulation
112、212、312、412、512、612、712、812、912、1012．．．控制結構112, 212, 312, 412, 512, 612, 712, 812, 912, 1012. . . Control structure
114、214、314、414、514、614、714、814、914、1014．．．控制電極114, 214, 314, 414, 514, 614, 714, 814, 914, 1014. . . Control electrode
216、316、516、616、716、916．．．介電層216, 316, 516, 616, 716, 916. . . Dielectric layer
L1、L2．．．長度L1, L2. . . length
圖1是依照本發明之第一實施例之一種電晶體主動層控制結構的剖面示意圖。BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross-sectional view showing a transistor active layer control structure in accordance with a first embodiment of the present invention.
圖2是依照本發明之第二實施例之一種電晶體主動層控制結構的剖面示意圖。2 is a cross-sectional view showing a transistor active layer control structure in accordance with a second embodiment of the present invention.
圖3是依照本發明之第三實施例之一種電晶體主動層控制結構的剖面示意圖。3 is a cross-sectional view showing a transistor active layer control structure in accordance with a third embodiment of the present invention.
圖4是依照本發明之第四實施例之一種電晶體主動層控制結構的剖面示意圖。4 is a cross-sectional view showing a transistor active layer control structure in accordance with a fourth embodiment of the present invention.
圖5是依照本發明之第五實施例之一種電晶體主動層控制結構的剖面示意圖。Figure 5 is a cross-sectional view showing a transistor active layer control structure in accordance with a fifth embodiment of the present invention.
圖6是依照本發明之第六實施例之一種電晶體主動層控制結構的剖面示意圖。Figure 6 is a cross-sectional view showing a transistor active layer control structure in accordance with a sixth embodiment of the present invention.
圖7是依照本發明之第七實施例之一種電晶體主動層控制結構的剖面示意圖。Figure 7 is a cross-sectional view showing a transistor active layer control structure in accordance with a seventh embodiment of the present invention.
圖8是依照本發明之第八實施例之一種電晶體主動層控制結構的剖面示意圖。Figure 8 is a cross-sectional view showing a transistor active layer control structure in accordance with an eighth embodiment of the present invention.
圖9是依照本發明之第九實施例之一種電晶體主動層控制結構的剖面示意圖。Figure 9 is a cross-sectional view showing a transistor active layer control structure in accordance with a ninth embodiment of the present invention.
圖10是依照本發明之第十實施例之一種電晶體主動層控制結構的剖面示意圖。Figure 10 is a cross-sectional view showing a transistor active layer control structure in accordance with a tenth embodiment of the present invention.
圖11顯示圖1之結構的俯試圖。Figure 11 shows the attempt of the structure of Figure 1.
圖12是控制電極電壓(Vc)變化及電晶體電壓(VT1T2 )差異對於漏電流之間的關係曲線圖。Fig. 12 is a graph showing changes in control electrode voltage (Vc) and difference in transistor voltage (V T1T2 ) with respect to leakage current.
100．．．基底100. . . Base
102．．．電晶體102. . . Transistor
104．．．閘極104. . . Gate
106a．．．源極106a. . . Source
106b．．．汲極106b. . . Bungee
108．．．主動層108. . . Active layer
110．．．閘極絕緣層110. . . Gate insulation
112．．．控制結構112. . . Control structure
114．．．控制電極114. . . Control electrode
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| US20070096643A1 (en) * | 2005-10-14 | 2007-05-03 | Maglione Maria G | Organic electroluminiscent device and process for manufacturing the device |
| US20070278598A1 (en) * | 2006-05-30 | 2007-12-06 | Samsung Electronics Co., Ltd. | Transistor, a transistor arrangement and method thereof |
| US20080135947A1 (en) * | 2006-12-07 | 2008-06-12 | Koo Jae Bon | Organic inverter including surface-treated layer and method of manufacturing the same |
| US20080164807A1 (en) * | 2004-08-25 | 2008-07-10 | Novaled Gmbh | Component Based on Organic Light-Emitting Diodes and Method For Producing the Same |
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| US20080164807A1 (en) * | 2004-08-25 | 2008-07-10 | Novaled Gmbh | Component Based on Organic Light-Emitting Diodes and Method For Producing the Same |
| US20070096643A1 (en) * | 2005-10-14 | 2007-05-03 | Maglione Maria G | Organic electroluminiscent device and process for manufacturing the device |
| US20070278598A1 (en) * | 2006-05-30 | 2007-12-06 | Samsung Electronics Co., Ltd. | Transistor, a transistor arrangement and method thereof |
| US20080135947A1 (en) * | 2006-12-07 | 2008-06-12 | Koo Jae Bon | Organic inverter including surface-treated layer and method of manufacturing the same |
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