TWI385801B - Power transistor and transistor unit thereof - Google Patents

Description

Power transistor and the transistor unit used

This invention relates to a transistor structure, and more particularly to the structure of a power transistor.

With the advancement of electronic technology and the increasing dependence of electronic products, an electronic product with all-in-one function is likely to become the real mainstream of the market. Therefore, the technology of integrating multiple different functional circuits has become an important issue for modern electronic engineers.

When performing the above-mentioned circuit integration work, the first problem encountered is the so-called multi-group power supply problem. Traditionally, these different functional circuits are usually powered by their own power supply system, but in the cost and volume considerations, this approach is bound to be implemented. In view of this, the industry has proposed many different types of power generation devices (such as DC DC power converters and AC DC power converters) to solve the aforementioned problems.

However, in order to generate sufficient power, these power converters usually require a power transistor with a strong current drive capability. In addition to the bulky problem, the power transistor has current density, heat dissipation, on-resistance and current. Multiple problems such as uniformity and multiple circuit layouts. Therefore, in the conventional transistor layout technique, the layout of a so-called multi-finger structure for processing a large-area transistor cannot effectively overcome the above problems.

The present invention provides a transistor unit constructed using a ring structure to save its circuit area.

The invention provides a power transistor, wherein the transistor units formed by the annular structure are arranged in an array manner, thereby saving the circuit area thereof.

The invention provides a transistor unit, comprising a first gate, a second gate, a first doping region and a second doping region. Wherein the gate is formed by a first annular structure, the first doped region is disposed inside the first annular structure, and the second doped region is surrounded by the first annular structure. On the outside, a second annular structure is formed. The second gate is surrounded by the outside of the second doping region and forms a third annular structure.

The invention adopts a transistor unit having a ring structure to form a power transistor, so when a plurality of transistor units are required to be arranged together, the area occupied by the transistor on the wafer can be effectively reduced, in addition to effectively reducing In addition to cost, it also has the ability to reduce the on-resistance and increase the current density, current uniformity, heat dissipation and resistance to electromigration of the power transistor.

The above described features and advantages of the present invention will be more apparent from the following description.

A plurality of embodiments will be described below for the transistor unit and the power transistor of the present invention, and are illustrated by the following, in order to be understood by those skilled in the art and implemented.

Referring first to FIG. 1A, FIG. 1A illustrates a transistor unit of the present invention. A schematic of an embodiment. In this embodiment, the transistor unit 100 is a Metal-Oxide-Semiconductor Field Effective Transistor (MOSFET). The transistor unit 100 has a gate 110 formed by a ring structure, and the region surrounded by the gate 110 of the ring structure is the first doping region 120 of the transistor unit 100. In contrast, the region of the other annular structure surrounding the outer circumference of the gate 110 is the second doping region 130 of the transistor unit 100, and the periphery of the second doping region 130 is surrounded by the same ring structure. The gate 140.

As is well known to those of ordinary skill in the art, the two doped regions of the MOS field-effect transistor are their drain and source, respectively, and thus, when the first doped region 120 is the source of the transistor cell 100. The second doping region 130 is the drain of the transistor unit 100. In contrast, when the first doping region 120 is the drain of the transistor unit 100, the second doping region 130 is the source of the transistor unit 100. In addition, when the transistor unit 100 is used alone, the gates 110, 120 may be connected to each other by the gate wires LG to form a common gate of the transistor unit 100.

It should be noted that the ring structure (whether the gates 110, 150 or the first and second doping regions 120, 130) in the transistor unit 100 can be not only a circle as shown in FIG. 1A, but also An elliptical structure of a schematic view of another embodiment of the transistor unit of the present invention, as shown in FIG. 1B, may also be used.

For a more detailed description of such a ring-shaped transistor unit, please refer to FIG. 2 for a perspective cross-sectional view of the transistor unit 100 of the embodiment of the present invention. As can be clearly seen from the depiction of FIG. 2, the gate 110 of the annular structure, The gates 140 are respectively covered on the gate oxides 111 and 141 on the substrate 140, and the other regions formed on the substrate are the first doping region 120 and the second doping region 130, respectively. If the transistor unit 100 is a P-type MOS field-effect transistor, the first doping region 120 and the second doping region 130 are respectively P-polar doping regions, and if the transistor unit 100 is an N-type The gold-oxygen half field effect transistor, the first doping region 120 and the second doping region 130 are respectively N-polar doped regions.

The gate 110 of the ring structure is covered on the substrate 140, and at the same time, the portion surrounded by the first doping region 120 and the second doping region 130, when the gate 110 of the ring structure is appropriately biased. When pressed, the channel 150 is correspondingly produced. The so-called appropriate bias voltage is a positive polarity bias applied to the gate and the substrate of the N-type gold-oxygen half-field effect transistor, and the gate and the substrate between the P-type gold-oxygen half-field effect transistor are added. Upper negative polarity bias.

In addition, since the transistor unit 100 of the present embodiment forms the channel 150 under the gate 110 thereof, the channel 150 is also annular, so that the width of the channel 150 can be the radius r2 of the inner ring of the gate 110. The average value of r1 of the outer ring radius is the radius and the calculated circumference is long. The length of the channel 150 is the difference between the inner ring radius r2 of the gate 110 and the outer ring radius r1.

It should be noted here that the hierarchical relationship described above with respect to the transistor unit 100 illustrated in FIG. 2 is merely an embodiment and does not limit the invention thereto. For example, the gates 110 and 140 shown in FIG. 2 do not have to be directly covered on the substrate 170, and may be covered on a so-called well (not shown), and the process structure of the gold-oxygen half-field effect transistor. Is a common knowledge in the field What the person can know is not the focus of the present invention, and will not be described in detail here.

For an embodiment of the power transistor constructed using the transistor unit 100 of the above embodiment, please refer to FIG. 3, which illustrates a schematic diagram of an embodiment of the power transistor 300 of the present invention. In the present embodiment, the power transistor 300 includes seven transistor units, and the transistors include gates 3101 to 3107, gates 3401 to 3407, first dummy regions 3201 to 3207, and second dummy regions 3301. 3307. Wherein, the six transistor units surround a transistor unit, and the second doping region 3301 of the central transistor unit partially overlaps the second doping region 3302~3307 of the surrounding transistor.

Please refer to FIG. 4 for the wiring pattern of the power transistor 300. FIG. 4 illustrates a wiring embodiment of the embodiment of the power transistor 300 of the present invention. Since the seven transistor units in FIG. 4 are constructed to construct a power transistor 300. Therefore, each of the dipoles of all the transistor units must be electrically connected. Here, the first doping region of each of the transistor units is taken as an example of a crucible, corresponding to each of the transistor units to be connected. The connection points CON1~CON3 are formed on the drain first, and the wire L1 is formed above the CON1~CON3 of each connection by using the wire layer above the connection point, so that the first impurity regions 3201~3207 which are the drains can be connected, and Form a common bungee.

In the above description, the connection points may be formed in a contact layer or a VIA layer for connection as a wire in a semiconductor process, and the wire layer may be selected to have a conductive layer (generally a metal layer) connected to the connection points CON1 to CON3. ) to form. Similarly, the source of each transistor unit can also be electrically connected by the above method. Second connection with connection as source For example, the miscellaneous regions 3304 and 3305 are formed on the second doping regions 3304 and 3305, respectively, and the wires L2 are electrically connected to the second doping regions 3304 and 3305 through the connection points CON4 and CON5. A common source of power transistors 300 is formed.

In addition, regarding the manner in which the gates of the respective transistor units are electrically connected, since the gates of the inner ring of each of the transistor units are electrically connected to the gates of the outer regions of the adjacent transistor units, the power transistor 300 is The gates of all of the transistor units are directly electrically connected together. Therefore, no additional wires are needed for the connection.

It is particularly worth mentioning that the above-mentioned wire connection method can be easily implemented by those skilled in the art in the semiconductor manufacturing process. The above description is merely an example for the wire connection method of the embodiment of the present invention, and does not limit the range of the wire connection mode of the power transistor of the present invention.

Furthermore, the power transistor 300 in the embodiment of the present invention does not have to be arranged in seven different crystal units as shown in the figure, and there are other different numbers or different directions. Referring to FIG. 5A to FIG. 5E , FIG. 5A to FIG. 5E are schematic diagrams showing the arrangement of different transistor units of the power transistor 300 in the embodiment of the present invention. If the shape of the center point of the annular structure of each transistor unit (the center point of the first doping region) is described, the structure may be arranged in a straight line as shown in FIG. 5A to FIG. 5C, or may be as shown in FIG. 5D or Figure 5E shows the structure of the mesh. However, in order to prevent each of the transistor units from undergoing excessive variations from each other during manufacture, each of the transistor units may be arranged in a symmetrical manner.

In addition, the calculation method of the channel width length of the power transistor 300 refers to the calculation method of the channel width length of the transistor unit in the upper stage, and multiplies the channel width of the single transistor unit by the number of the transistor units in the power transistor 300. The total channel width of the power transistor 300 can be calculated.

In addition, in order to reduce the area occupied by the power transistor, an embodiment is proposed to explain the arrangement of the transistor unit. Please refer to FIG. 6. FIG. 6 illustrates an embodiment of an arrangement of transistor units in a power transistor of the present invention. In the illustration of FIG. 6, the center points A1 to A5 of the respective transistor units are equal to each other. This arrangement can closely combine the transistor units to save circuit area.

In summary, the present invention utilizes a transistor unit having a ring structure to arrange and combine power transistors to effectively closely arrange the transistor units. In addition to reducing the cost of the power transistor on the wafer, in addition to effectively reducing the cost, it also has the ability to reduce the on-resistance and improve the current density, current uniformity, heat dissipation and anti-electromigration of the power transistor.

Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100‧‧‧Optocell unit

110, 140, 3101~3107, 3401~3407‧‧‧ gate

120, 3201~3207‧‧‧First Miscellaneous Area

130, 3301~3307‧‧‧Second mixed area

170‧‧‧Base

150‧‧‧ channel

141, 111‧‧ ‧ gate oxide layer

300‧‧‧Power transistor

R1, r2‧‧‧ radius

CON1~CON3‧‧‧ connection point

L1, L2, LG‧‧‧ wires

A1~A5‧‧‧ Center Point

1A is a schematic view of an embodiment of a transistor unit of the present invention.

FIG. 1B is a schematic view of another embodiment of the transistor unit of the present invention.

2 is a perspective cross-sectional view of the transistor unit 100 of the embodiment of the present invention.

3 is a schematic diagram of an embodiment of a power transistor 300 of the present invention.

4 illustrates a wiring embodiment of an embodiment of a power transistor 300 of the present invention.

5A-5E are schematic diagrams showing the arrangement of different transistor units of the power transistor 300 in the embodiment of the present invention.

6 illustrates an embodiment of an arrangement of transistor cells in a power transistor of the present invention.

300‧‧‧Power transistor

3201~3203‧‧‧First Miscellaneous Area

3301~3307‧‧‧Second mixed area

3101~3107, 3401~3407‧‧‧ gate

Claims (14)

A transistor unit comprising: a first gate formed by a first annular structure; a first doped region disposed on an inner side of the first annular structure; and a second doped region surrounding the The first annular structure forms a second annular structure; and a second gate surrounds the outer side of the second doping region to form a third annular structure. The transistor unit of claim 1, wherein the first gate and the second gate are electrically connected by a gate wire. The transistor unit of claim 1, wherein the first doping region is a drain of the transistor unit, and the second doping region is a source of the transistor unit. The transistor unit of claim 1, wherein the first doping region is a source of the transistor unit, and the second doping region is a drain of the transistor unit. The transistor unit of claim 1, wherein the first, second and third annular structures are circular or elliptical. The transistor unit according to claim 1 is a gold oxide half field effect transistor. A power transistor includes: a plurality of transistor units, each of the transistor units including: a first gate formed by a first annular structure; and a first doped region disposed in the first ring The inner side of the structure; a second doping area surrounding the first annular structure to form a a second annular structure; and a second gate surrounding the second doped region to form a third annular structure; wherein the second doped region of each of the transistor units is adjacent to The second doping regions of the plurality of transistor units are partially overlapped, and the first gates of the plurality of transistor units are electrically connected to the second gates of the adjacent of the plurality of transistor units to form a common gate. And the first doping regions of the plurality of transistor units are electrically connected to each other by a first wire. The power transistor of claim 7, wherein the second wire further comprises at least one second doping region of the plurality of transistor units. The power transistor of claim 8, wherein the first wire is electrically connected to the first doping region of the transistor unit to form a common source of the power transistor, the second wire connection At least one second doping region of the plurality of transistor units to form a common drain of the power transistor. The power transistor of claim 8, wherein the first wire is electrically connected to the first doping region of the transistor unit to form a common drain of the power transistor, the second wire connection At least one second doping region of the plurality of transistor units to form a common source of the power transistor. The power transistor of claim 7, wherein the line connecting the center points of the first doping regions comprises forming a straight line, a curved line or a mesh structure. Such as the power transistor described in claim 7 of the patent scope, wherein each The center point of the first doping region of the transistor unit and the center point of the first doping region of the plurality of transistor units adjacent thereto are equal. The power transistor of claim 7, wherein the transistor units are symmetrically distributed. The power transistor as described in claim 7 is a gold oxide half field effect transistor.