TWI385528B - Arbitration device for system bus - Google Patents
Arbitration device for system bus Download PDFInfo
- Publication number
- TWI385528B TWI385528B TW97150059A TW97150059A TWI385528B TW I385528 B TWI385528 B TW I385528B TW 97150059 A TW97150059 A TW 97150059A TW 97150059 A TW97150059 A TW 97150059A TW I385528 B TWI385528 B TW I385528B
- Authority
- TW
- Taiwan
- Prior art keywords
- arbitration
- system bus
- unit
- external device
- output processing
- Prior art date
Links
Landscapes
- Bus Control (AREA)
Description
本發明是有關於一種仲裁裝置,特別是指一種適用於仲裁多層系統匯流排的優先權順序之仲裁裝置。The present invention relates to an arbitration apparatus, and more particularly to an arbitration apparatus suitable for arbitrating the priority order of a bus of a multi-layer system.
目前一般常見的系統匯流排仲裁裝置,都是採用單一仲裁演算法,例如:IBM公司的CoreConnect匯流排架構及ARM公司的AMBA匯流排架構,其所發表的產品內都是採用最高優先權演算法(First priority algorithm)做為其仲裁裝置的演算法。At present, the common system bus arbitration devices use a single arbitration algorithm, such as IBM's CoreConnect bus structure and ARM's AMBA bus structure. The products published are all using the highest priority algorithm. (First priority algorithm) is the algorithm for its arbitration device.
然而,此種侷限於單一演算法以作為不同應用的仲裁演算法,將會使得匯流排的資源無法適當被利用,進而影響整體系統的效能,舉例來說,在現今的行動電話中,因為附有其他影音功能,如:音樂播放、拍照、照片/短片瀏覽等各式不同功能的應用,當使用最高優先演算法作為行動電話中系統匯流排的仲裁演算法時,則其內部的相關功能元件將會被分別預先設定一由高而低的優先權,因為行動電話最重要的功能就是撥打或接收電話,因此假設行動電話內的基頻(Baseband)裝置具有最高優先權、彩色數位訊號處理(CDSP)裝置次之、MP3解碼裝置再次之等,然而,當使用者欲利用行動電話播放音樂時,MP3解碼裝置使用系統匯流排的時機可能會因為其優先權較低而造成取得系統匯流排的機會較少,導致音樂播放的過程並不順遂。However, this kind of arbitration algorithm limited to a single algorithm as a different application will make the resources of the bus bar not be properly utilized, thus affecting the overall system performance. For example, in today's mobile phones, because There are other audio and video functions, such as: music playback, photo taking, photo/video browsing and other different functions. When using the highest priority algorithm as the arbitration algorithm of the system bus in the mobile phone, the internal related functional components A high-low priority will be preset in advance, because the most important function of the mobile phone is to make or receive calls, so it is assumed that the baseband device in the mobile phone has the highest priority, color digital signal processing ( The CDSP) device is the second, the MP3 decoding device is again equal. However, when the user wants to use the mobile phone to play music, the timing of the MP3 decoding device using the system bus may cause the system bus to be obtained because of its lower priority. There are fewer opportunities, and the process of music playback is not smooth.
此外,目前系統匯流排仲裁裝置應用於多層系統匯流排系統時,大多是採用每一外部裝置經由一專屬的系統匯流排來進行存取,無論設計方式是每一外部裝置具有一專屬的系統匯流排以存取任一從屬裝置(Slave),或是每一從屬裝置具有一專屬的系統匯流排以供存取,皆無法有效達到共用系統匯流排的目的,因此,每一外部裝置存取任一從屬裝置時,只能從一條路徑進行存取,故即使有其他閒置的匯流排存在,則因為該閒置匯流排非屬於其專屬的系統匯流排,因此該外部裝置也無法使用,如此會造成系統匯流排的數量需要隨著外部裝置的數量而上升,進而造成成本增加。In addition, when the system bus arbitration device is applied to the multi-layer system bus system, most of the external devices are accessed through a dedicated system bus, regardless of the design method, each external device has a dedicated system convergence. The access to any slave device (Slave), or each slave device has a dedicated system bus for access, can not effectively achieve the purpose of the shared system bus, so each external device access When a slave device is accessed from only one path, even if there are other idle bus bars, the external device cannot be used because the idle bus bar does not belong to its exclusive system bus, which may result in The number of system bus bars needs to increase with the number of external devices, which in turn increases costs.
因此,歸納上述,習知設計共有以下幾項缺點:Therefore, in summary of the above, the conventional design has the following shortcomings:
一、無法有效共用系統匯流排:習知設計因為沒有有效的仲裁機制,因此,需要設計專屬系統匯流排以供每一外部裝置或是從屬裝置使用,其仲裁方式為當系統匯流排忙碌時,重新進行仲裁,而當系統匯流排閒置時,才將系統匯流排的使用權設定給欲進行存取的外部裝置;這樣會造成系統匯流排的數目隨外部裝置或是從薯裝置的數量增加,進而增加成本;1. It is impossible to effectively share the system bus: the conventional design has no effective arbitration mechanism. Therefore, it is necessary to design a dedicated system bus for use by each external device or slave device. The arbitration method is when the system bus is busy. Re-arbitration, and when the system bus is idle, the system bus usage right is set to the external device to be accessed; this will cause the number of system bus bars to increase with the number of external devices or from the potato device. Increasing costs;
二、容易造成同一裝置長時間佔用系統匯流排:習知設計藉由特定演算法進行一次仲裁時,容易造成某些外部裝置因為其傳輸特性的關係,易於取得系統匯流排的使用權,進而長時間佔用系統匯流排,同理,某些外部裝置因而長時間無法使用系統匯流排,而形成系統匯流排的資源分配不均,進而影響系統傳輸效能不彰;Second, it is easy to cause the same device to occupy the system bus for a long time: When a conventional design performs arbitration by a specific algorithm, it is easy to cause some external devices to easily obtain the right to use the system bus due to their transmission characteristics. Time occupies the system bus, similarly, some external devices can not use the system bus for a long time, and the resource allocation of the system bus is uneven, which affects the system transmission efficiency;
三、不易擴充應用於不同的產品上:習知設計採用在一仲裁裝置中內建一特定的仲裁演算法的作法,很難將一系統匯流排的應用做擴充,因為,不同的應用有可能會使得該特定的仲裁演算法效能不彰,導致匯流排的資源浪費或是產生較久的傳輸延遲,進而使得系統傳輸效能下降。Third, it is not easy to expand and apply to different products: the conventional design uses a specific arbitration algorithm built in an arbitration device, it is difficult to expand the application of a system bus, because different applications are possible This will make the specific arbitration algorithm ineffective, resulting in wasted resources of the bus or a long transmission delay, which will make the system transmission performance decline.
所以,如何有效開發一系統匯流排的仲裁裝置,一直是相關業界所高度關注的問題之一。Therefore, how to effectively develop an arbitration device for a system bus has always been one of the issues of great concern to the industry.
因此,本發明之目的,即在提供一種系統匯流排之仲裁裝置,適用於仲裁複數個外部裝置請求使用複數系統匯流排以存取另一裝置時的順序,其包含:一第一仲裁單元,包括m個仲裁模組,且每一仲裁模組電連接於n個外部裝置,並接收該等裝置提出存取系統匯流排的請求以進行仲裁而輸出一個仲裁結果;一第二仲裁單元,連接於該第一仲裁單元並接收所有仲裁模組的仲裁結果,且將該等仲裁結果進行仲裁以輸出一優先權順序;及一輸出處理單元,接收該優先權順序並判斷目前系統匯流排的使用狀態,當所有系統匯流排都處於閒置狀態時,該輸出處理單元將其中一條系統匯流排的使用權設定給具有最高優先權順序的外部裝置使用,當部分系統匯流排處於忙碌狀態且部分系統匯流排閒置時,該輸出處理單元依據優先權順序將處於閒置狀態的系統匯流排使用權設定給可以進行存取之外部裝置。Accordingly, it is an object of the present invention to provide an arbitration apparatus for a system bus that is adapted to arbitrate a plurality of external devices requesting the use of a plurality of system busses to access another device, comprising: a first arbitration unit, Including m arbitration modules, and each arbitration module is electrically connected to n external devices, and receives requests from the devices to access the system bus bar for arbitration to output an arbitration result; a second arbitration unit, connected And receiving, by the first arbitration unit, arbitration results of all arbitration modules, and arbitrating the arbitration results to output a priority order; and an output processing unit receiving the priority sequence and determining the current system bus usage State, when all system bus bars are idle, the output processing unit sets the usage right of one of the system bus bars to the external device with the highest priority order, when part of the system bus bar is busy and part of the system is converged When the row is idle, the output processing unit will be in the idle state of the system bus according to the priority order By weight can be set to the external device to access.
本發明之功效為:The effect of the invention is:
一、可有效共用系統匯流排:根據優先權順序排列出目前提出請求的裝置之順序,再由輸出處理單元判斷目前系統匯流排的使用狀態而設定系統匯流排的使用權給允許其請求之外部裝置,因此,當具有最高優先權的外部裝置無法進行存取時,仍可由次高優先權的外部裝置進行存取;1. The system bus can be effectively shared: the order of the currently requested device is arranged according to the priority order, and then the output processing unit determines the current state of use of the system bus and sets the usage right of the system bus to the outside of the request. The device, therefore, can be accessed by the next highest priority external device when the external device with the highest priority cannot be accessed;
二、有效提升系統匯流排的效能:藉由二階段仲裁方式,使得每一裝置取得系統匯流排存取權的機會更為平均,以避免同一裝置長時間佔用系統匯流排的頻寬;及Second, effectively improve the efficiency of the system bus: by means of the two-stage arbitration, the opportunity for each device to obtain access to the system bus is more even, to avoid the bandwidth of the system bus for the same device for a long time;
三、易於擴充應用在不同的產品上:藉由外部輸入的控制碼提供複數種仲裁演算法的組合,可以讓使用者根據不同的使用模式而動態設定適當的仲裁演算法組合,進而使得本發明可以更廣泛地應用於不同的產品中。3. It is easy to expand and apply to different products: by providing a combination of multiple arbitration algorithms by externally input control codes, the user can dynamically set appropriate arbitration algorithm combinations according to different usage modes, thereby making the present invention Can be more widely used in different products.
有關本發明之前述及其他技術內容、特點與功效,在以下配合參考圖式之二個較佳實施例的詳細說明中,將可清楚的呈現。The above and other technical contents, features and advantages of the present invention will be apparent from the following detailed description of the preferred embodiments of the invention.
參閱圖1,本發明系統匯流排之仲裁裝置的第一較佳實施例適用於仲裁複數個外部裝置901~916請求使用二系統匯流排8以存取另一裝置時的優先權順序,包含:一第一仲裁單元11、一第二仲裁單元12、一控制單元13,及一輸出處理單元14。Referring to Figure 1, a first preferred embodiment of the arbitration apparatus for a system bus of the present invention is adapted to arbitrate a priority order in which a plurality of external devices 901-916 request to use a two-system bus 8 to access another device, including: A first arbitration unit 11, a second arbitration unit 12, a control unit 13, and an output processing unit 14.
該第一仲裁單元11包括四個仲裁模組,分別為一第一仲裁模組111、一第二仲裁模組112、一第三仲裁模組113、一第四仲裁模組114,且每一仲裁模組111~114都內建固定優先權演算法(Fixed priority algorithm)、平均循環演算法(Round-Robin algorithm)、先進先服務演算法(First-come-first-service algorithm),及隨機存取演算法(Random access algorithm)等四種不同的仲裁演算法,每一仲裁模組111~114分別接收一由控制單元13所傳送之二位元控制訊號,以設定對應仲裁模組內部之仲裁演算法,例如:當控制訊號為11時,該仲裁模組將依照先進先服務演算法作為仲裁演算法。The first arbitration unit 11 includes four arbitration modules, which are a first arbitration module 111, a second arbitration module 112, a third arbitration module 113, and a fourth arbitration module 114, and each The arbitration modules 111~114 all have a built-in fixed priority algorithm, a Round-Robin algorithm, a First-come-first-service algorithm, and a random access memory. Four different arbitration algorithms, such as a random access algorithm, each of the arbitration modules 111-114 receives a binary control signal transmitted by the control unit 13 to set an arbitration within the corresponding arbitration module. Algorithm, for example, when the control signal is 11, the arbitration module will use the advanced first service algorithm as the arbitration algorithm.
每一仲裁模組111~114分別連接四個外部裝置,並依據所設定的仲裁演算法進行系統匯流排8使用權的仲裁,最後輸出一個決定出哪一個外部裝置可得到匯流排使用權的仲裁結果。例如:第一仲裁模組111分別連接裝置901至裝置904並輸出一仲裁結果A,同理,第二仲裁模組112分別連接裝置905至裝置908並輸出一仲裁結果B、第三仲裁模組113分別連接裝置909至裝置912並輸出一仲裁結果C、第四仲裁模組114分別連接裝置913至裝置916並輸出一仲裁結果D。Each arbitration module 111-114 is connected to four external devices, and performs arbitration of the usage rights of the system bus 8 according to the set arbitration algorithm, and finally outputs an arbitration that determines which external device can obtain the right to use the bus. result. For example, the first arbitration module 111 connects the device 901 to the device 904 and outputs an arbitration result A. Similarly, the second arbitration module 112 connects the device 905 to the device 908 and outputs an arbitration result B and a third arbitration module. 113 respectively connects the device 909 to the device 912 and outputs an arbitration result C. The fourth arbitration module 114 connects the device 913 to the device 916 and outputs an arbitration result D.
該第二仲裁單元12中也內建固定優先權、平均循環、先進先服務,及隨機存取等四個仲裁演算法,並接收一由控制單元13所傳送之二位元控制訊號,以設定該第二仲裁單元12內部對應之仲裁演算法,例如:當控制訊號為11時,該第二仲裁單元12將依照先進先服務演算法作為仲裁演算法。The second arbitration unit 12 also has built in four arbitration algorithms, such as fixed priority, average cycle, advanced first service, and random access, and receives a binary control signal transmitted by the control unit 13 to set The arbitration algorithm corresponding to the second arbitration unit 12, for example, when the control signal is 11, the second arbitration unit 12 will use the advanced service algorithm as the arbitration algorithm.
該第二仲裁單元12接收由第一仲裁單元11之每一仲裁模組111~114所輸出的仲裁結果A~D,依據設定的仲裁演算法進行系統匯流排8使用權的仲裁,最後輸出一組優先權順序(Priority order)至輸出處理單元14中,該優先權順序代表該第二仲裁單元12所決定所有提出請求之外部裝置使用系統匯流排的順序。The second arbitration unit 12 receives the arbitration results A~D outputted by each of the arbitration modules 111-114 of the first arbitration unit 11, and performs arbitration of the usage rights of the system bus 8 according to the set arbitration algorithm, and finally outputs one. The priority order is assigned to the output processing unit 14, which represents the order in which the second arbitration unit 12 determines that all of the requesting external devices use the system bus.
該控制單元13接收一由外部輸入(如:使用者的輸入)之十位元控制碼,並將該對應的控制碼傳送至該第一仲裁單元11之每一仲裁模組111~114及第二仲裁單元12中,舉例來說,將控制碼之第零、第一位元定義為第二仲裁單元12的控制訊號,則該控制單元13會將此二位元傳送至該第二仲裁單元12中,使得該第二仲裁單元12調整對應的仲裁演算法,其餘八位元亦分別定義為四個仲裁模組111~114的控制訊號,並由控制單元傳送對應的二位元控制訊號至對應的仲裁模組中,以調整每一仲裁模組111~114中的仲裁演算法。The control unit 13 receives a tens control code input by an external input (eg, user input), and transmits the corresponding control code to each of the arbitration modules 111-114 and the first arbitration unit 11 In the second arbitration unit 12, for example, the zeroth and first bits of the control code are defined as the control signals of the second arbitration unit 12, and the control unit 13 transmits the two bits to the second arbitration unit. 12, the second arbitration unit 12 is adjusted to the corresponding arbitration algorithm, and the remaining eight bits are also defined as the control signals of the four arbitration modules 111-114, and the corresponding two-bit control signals are transmitted by the control unit to In the corresponding arbitration module, the arbitration algorithm in each arbitration module 111-114 is adjusted.
舉例來說,假設該控制碼由高至低的位元順序依次代表為第一仲裁模組111的控制訊號、第二仲裁模組112的控制訊號、第三仲裁模組113的控制訊號、第四仲裁模組114的控制訊號、第二仲裁單元12的控制訊號,且每一控制訊號之二位元為00時代表固定優先權演算法,控制訊號之二位元為01時代表平均循環演算法,控制訊號之二位元為10時代表先進先服務演算法,控制訊號之二位元為11時代表隨機存取演算法,則當使用者輸入之控制碼為00_0110_1011時,則代表第一仲裁模組111選取固定優先權演算法為仲裁演算法、第二仲裁模組112選取平均循環演算法為仲裁演算法、第三仲裁模組113選取先進先服務演算法為仲裁演算法、第四仲裁模組114選取先進先服務演算法為仲裁演算法、第二仲裁單元12選取隨機存取演算法為仲裁演算法。For example, it is assumed that the control code is sequentially represented by the control signal of the first arbitration module 111, the control signal of the second arbitration module 112, the control signal of the third arbitration module 113, and the The control signal of the fourth arbitration module 114 and the control signal of the second arbitration unit 12, and each of the control signals has a fixed priority algorithm when the two bits are 00, and the average cyclic calculation when the two bits of the control signal are 01. In the method, the two bits of the control signal are 10 hours for the advanced first service algorithm, and the two bits of the control signal are 11 hours for the random access algorithm. When the user inputs the control code 00_0110_1011, it represents the first The arbitration module 111 selects the fixed priority algorithm as the arbitration algorithm, the second arbitration module 112 selects the average loop algorithm as the arbitration algorithm, and the third arbitration module 113 selects the advanced first service algorithm as the arbitration algorithm, and the fourth The arbitration module 114 selects the advanced first service algorithm as the arbitration algorithm, and the second arbitration unit 12 selects the random access algorithm as the arbitration algorithm.
由於每一仲裁模組111~114及第二仲裁單元12的仲裁演算法皆可由外部控制,因此假設在一行動電話中,需使用音樂播放功能時,即可藉由外部設定的控制碼將與音樂播放功能相關裝置連接之仲裁模組111~114切換為適當的仲裁演算法(或也進一步將第二仲裁單元12切換為適當的仲裁演算法),如:平均循環演算法(Round-Robin algorithm),使得MP3解碼裝置可以與其他裝置有較為平均的機會取得系統匯流排8的使用權,則可以提升音樂播放模式的效能,而當行動電話回復到通話模式時,則切換回最高優先權演算法以保持通話的順暢性,因此,動態調整行動電話的系統匯流排仲裁演算法,可以有效兼顧通話功能與其他多媒體功能之應用。Since the arbitration algorithms of each of the arbitration modules 111-114 and the second arbitration unit 12 can be externally controlled, it is assumed that when a music playing function is required in a mobile phone, the externally set control code can be used. The arbitration module 111~114 connected to the music playback function related device switches to an appropriate arbitration algorithm (or further switches the second arbitration unit 12 to an appropriate arbitration algorithm), such as a Round-Robin algorithm. ), so that the MP3 decoding device can have a relatively equal opportunity to obtain the right to use the system bus 8 with other devices, thereby improving the performance of the music playing mode, and when the mobile phone returns to the call mode, switching back to the highest priority calculation. In order to maintain the smoothness of the call, the system bus arbitration algorithm that dynamically adjusts the mobile phone can effectively balance the call function with other multimedia functions.
以本實施例為例,在16個外接裝置的情形下,因為對應控制碼的位元數為10位元,因此,一共具有1024種不同仲裁演算法的組何方式,當具有本發明仲裁裝置之系統匯流應用於不同的產品上時,亦可隨著不同產品的特色而動態調整出仲裁演算法的組合,所以可以有效保持系統匯流排的傳輸效率,而不受到不同的產品應用特性而改變。Taking this embodiment as an example, in the case of 16 external devices, since the number of bits corresponding to the control code is 10 bits, there are a total of 1024 different arbitration algorithms in the group, when there is an arbitration device of the present invention. When the system convergence is applied to different products, the combination of arbitration algorithms can be dynamically adjusted according to the characteristics of different products, so that the transmission efficiency of the system bus can be effectively maintained without being changed by different product application characteristics. .
該輸出處理單元14包括一儲存器141、一判斷器142,及一處理器143。該儲存器141用以根據該第二仲裁單元12輸出之優先權順序,依序儲存有提出請求之外部裝置的識別名稱(ID)及每一外部裝置欲存取的裝置位址;該判斷器142用以判斷該等系統匯流排8目前的狀態;該處理器143依據該判斷器142的判斷結果決定使用每一系統匯流排的外部裝置。其中,該判斷器142判斷該等系統匯流排8目前的狀態如以下三種情形:The output processing unit 14 includes a storage unit 141, a determiner 142, and a processor 143. The storage unit 141 is configured to sequentially store the identification name (ID) of the requesting external device and the device address that each external device wants to access according to the priority order of the output of the second arbitration unit 12; the determiner 142 is used to determine the current state of the system bus 8; the processor 143 determines the external device using each system bus according to the judgment result of the determiner 142. The determiner 142 determines the current status of the system bus 8 as follows:
一、當所有系統匯流排8都處於閒置狀態時:該處理器143將其中一條系統匯流排的使用權設定給具有最高優先權順序的外部裝置使用,並標記其存取裝置的位址為使用中狀態,且將另一條也閒置的系統匯流排的使用權設定給具有次高優先權順序的外部裝置使用,並標記其存取裝置的位址為使用中狀態;1. When all system bus bars 8 are in an idle state: the processor 143 sets the usage right of one of the system bus bars to the external device having the highest priority order, and marks the address of the access device as using Medium state, and the use right of another system bus that is also idle is set to be used by an external device having the next highest priority order, and the address of the access device is marked as an in-use state;
二、當其中一系統匯流排8處於忙碌狀態時,該處理器143依照優先權順序逐次比對該等外部裝置的存取裝置位址與目前使用系統匯流排上的外部裝置之存取裝置位址,當比對相等時,表示該外部裝置欲存取之裝置正在被其他外部裝置存取中,因此依序取出下一優先權順序的外部裝置再次進行比對,直到比對不相等時,則將另一處於閒置狀態下的系統匯流排使用權設定給該外部裝置進行存取,並標記其存取裝置的位址為使用中狀態;2. When one of the system bus bars 8 is in a busy state, the processor 143 sequentially compares the access device addresses of the external devices with the access device bits of the external devices on the current system bus in accordance with the priority order. Address, when the comparison is equal, indicating that the device to be accessed by the external device is being accessed by other external devices, so the external devices in the next priority order are sequentially taken out and compared again until the comparison is not equal. And setting another system bus usage right in an idle state to the external device for access, and marking the address of the access device as an in-use state;
三、當所有系統匯流排8都處於忙碌狀態時:該處理器143會清除儲存器141,並重新進行仲裁。3. When all system bus bars 8 are busy: the processor 143 will clear the memory 141 and re-arbitrate.
在此舉一例說明輸出處理單元14的處理方式:假設外部裝置901及外部裝置915提出使用系統匯流排的請求,經過第一、第二仲裁單元11、12仲裁之後的優先權順序為外部裝置915優於外部裝置901,則在輸出處理單元中,會將外部裝置915之ID及其欲存取的裝置位址(0010)、外部裝置901之ID及其欲存取的裝置位址(0111)依序儲存於儲存器141中,當該判斷器142判斷其中一系統匯流排正在進行位址(0010)的裝置存取動作時,則該處理器143依照優先權順序由儲存器141中取出外部裝置915及其存取裝置位址(0010),並且與正在系統匯流排上進行存取的裝置位址進行比對,當比對結果相等時,表示外部裝置915欲存取的裝置正在被其他外部裝置存取中,因此,該處理器143將依照優先權順序取出下一個外部裝置901及其存取裝置位址(0111)再次進行比對,當比對結果不相等時,表示該外部裝置901欲存取的裝置目前正處於閒置狀態,可以被該外部裝置901進行存取,因此,該處理器143將處於閒置狀態的系統匯流排使用權設定給該外部裝置901進行存取。An example of the processing of the output processing unit 14 is as follows: assuming that the external device 901 and the external device 915 make a request to use the system bus, the priority order after arbitration by the first and second arbitration units 11, 12 is the external device 915. Compared with the external device 901, in the output processing unit, the ID of the external device 915 and the device address (0010) to be accessed, the ID of the external device 901, and the device address to be accessed (0111) Stored in the storage unit 141 in sequence, when the determiner 142 determines that one of the system bus bars is performing the device access operation of the address (0010), the processor 143 takes the external storage from the storage unit 141 in accordance with the priority order. The device 915 and its access device address (0010) are compared with the device address being accessed on the system bus. When the comparison results are equal, the device indicating that the external device 915 is to be accessed is being used by the other device. The external device is accessed. Therefore, the processor 143 takes out the next external device 901 and its access device address (0111) in accordance with the priority order and compares them again. When the comparison result is not equal, the external device is indicated. The device to be accessed 901 is currently in an idle state and can be accessed by the external device 901. Therefore, the processor 143 sets the system bus usage right in the idle state to the external device 901 for access.
值得注意的是,雖然第一實施例中是以應用於二個系統匯流排8為例做說明,但並不以此為限。It should be noted that although the first embodiment is applied to the two system bus bars 8 as an example, it is not limited thereto.
參閱圖2,本發明之第二較佳實施例與第一實施例類似,不同的地方在於第一仲裁單元11所包括的仲裁模組數和每一仲裁模組連接的外部裝置個數。Referring to FIG. 2, the second preferred embodiment of the present invention is similar to the first embodiment. The difference lies in the number of arbitration modules included in the first arbitration unit 11 and the number of external devices connected to each arbitration module.
在本發明之第二較佳實施例中,該第一仲裁單元11包括m個仲裁模組,且每一仲裁模組內建P種不同的仲裁演算法,其中,每一仲裁模組連接n個外部裝置,並輸出一仲裁結果。此外,每一仲裁模組分別接收一由該控制單元13所傳送之位元控制訊號,以設定該仲裁模組內部對應之仲裁演算法。In the second preferred embodiment of the present invention, the first arbitration unit 11 includes m arbitration modules, and each arbitration module has built in a plurality of different arbitration algorithms, wherein each arbitration module is connected to n. An external device and output an arbitration result. In addition, each arbitration module receives a transmission by the control unit 13 The bit control signal is used to set an arbitration algorithm corresponding to the arbitration module.
該第二仲裁單元12中也內建P種不同的仲裁演算法,且分別接收由第一仲裁單元11之每一仲裁模組所輸出的仲裁結果,以輸出一優先權順序至輸出處理單元。此外,該第二仲裁單元12接收一由控制單元13所傳送之位元控制訊號,以設定該第二仲裁單元12內部對應之仲裁演算法。The second arbitration unit 12 also has built in P different arbitration algorithms, and respectively receives the arbitration results output by each arbitration module of the first arbitration unit 11 to output a priority sequence to the output processing unit. In addition, the second arbitration unit 12 receives a transmission by the control unit 13. The bit control signal is used to set an arbitration algorithm corresponding to the interior of the second arbitration unit 12.
該控制單元13接收一由外部輸入之K位元控制碼,並將該對應的控制碼傳送至該第一仲裁單元11之每一仲裁模組及第二仲裁單元12中,其中,控制碼的位元數K計算如下:The control unit 13 receives an externally input K-bit control code, and transmits the corresponding control code to each of the arbitration modules and the second arbitration unit 12 of the first arbitration unit 11, wherein the control code The number of bits K is calculated as follows:
藉由第二較佳實施例的說明,本發明系統匯流排8仲裁裝置可以內建複數個不同的仲裁演算法,同時,藉由對應調整控制碼的位元數,可以使得第一仲裁單元11內之每一仲裁模組及第二仲裁單元12內之仲裁演算法可以動態調整。According to the description of the second preferred embodiment, the system bus 8 arbitration apparatus of the present invention can internally implement a plurality of different arbitration algorithms, and at the same time, the first arbitration unit 11 can be caused by correspondingly adjusting the number of bits of the control code. The arbitration algorithm in each arbitration module and the second arbitration unit 12 can be dynamically adjusted.
綜上所述,本發明之系統匯流排仲裁裝置具有以下幾項優點:In summary, the system bus arbitration device of the present invention has the following advantages:
一、可有效共用系統匯流排:當本發明應用於多層系統匯流排系統時,因為每一外部裝置有複數條路徑可以進行存取,所以不需要專屬的系統匯流排,而且根據第二仲裁單元的優先權順序,排列出目前提出請求的裝置之優先權順序,再由輸出處理單元判斷目前系統匯流排的使用狀態而設定系統匯流排的使用權給允許其請求之外部裝置,因此,當具有最高優先權的外部裝置無法進行存取時,仍可由次高優先權的外部裝置進行存取,因此本發明可以有效達到共用匯流排的目的;1. Effectively sharing the system busbar: When the present invention is applied to a multi-layer system busbar system, since each external device has multiple paths for access, a dedicated system busbar is not required, and according to the second arbitration unit Priority order, which ranks the priority order of the device that is currently requesting, and then the output processing unit determines the current state of use of the system bus and sets the usage right of the system bus to the external device that allows the request, therefore, when When the highest priority external device cannot be accessed, it can still be accessed by the next highest priority external device, so the present invention can effectively achieve the purpose of sharing the bus bar;
二、有效提升系統匯流排的效能:藉由二階段仲裁方式,使得每一裝置取得系統匯流排存取權的機會更為平均,因此可以避免同一裝置長時間佔用系統匯流排的頻寬,進而造成系統傳輸效率下降的情形發生;及Second, effectively improve the efficiency of the system bus: by means of the two-stage arbitration, each device has a more uniform access to the system bus access, thus avoiding the same device occupying the bandwidth of the system bus for a long time, and then Causing a situation in which the transmission efficiency of the system is degraded; and
三、易於擴充應用在不同的產品上:藉由控制單元接收外部輸入的控制碼提供複數種仲裁演算法的組合,可以讓使用者根據不同的使用模式而動態設定適當的仲裁演算法組合,進而使得本發明可以更廣泛地應用於不同的產品中。3. It is easy to expand and apply to different products: the control unit receives externally input control codes to provide a combination of multiple arbitration algorithms, which allows the user to dynamically set appropriate arbitration algorithm combinations according to different usage modes. The invention can be applied more broadly to different products.
故確實能達成本發明之目的。Therefore, the object of the present invention can be achieved.
惟以上所述者,僅為本發明之較佳實施例而已,當不能以此限定本發明實施之範圍,即大凡依本發明申請專利範圍及發明說明內容所作之簡單的等效變化與修飾,皆仍屬本發明專利涵蓋之範圍內。The above is only the preferred embodiment of the present invention, and the scope of the invention is not limited thereto, that is, the simple equivalent changes and modifications made by the scope of the invention and the description of the invention are All remain within the scope of the invention patent.
11‧‧‧第一仲裁單元11‧‧‧First Arbitration Unit
111‧‧‧第一仲裁模組111‧‧‧First Arbitration Module
112‧‧‧第二仲裁模組112‧‧‧Second Arbitration Module
113‧‧‧第三仲裁模組113‧‧‧ Third Arbitration Module
114‧‧‧第四仲裁模組114‧‧‧fourth arbitration module
12‧‧‧第二仲裁單元12‧‧‧Second Arbitration Unit
13‧‧‧控制單元13‧‧‧Control unit
14‧‧‧輸出處理單元14‧‧‧Output processing unit
141‧‧‧儲存器141‧‧‧Storage
142‧‧‧判斷器142‧‧‧ judge
143‧‧‧處理器143‧‧‧ processor
8‧‧‧系統匯流排8‧‧‧System Bus
901~916‧‧‧外部裝置901~916‧‧‧External device
圖1是本發明系統匯流排仲裁裝置之第一較佳實施例之方塊圖;及1 is a block diagram of a first preferred embodiment of a system bus arbitration device of the present invention; and
圖2是本發明系統匯流排仲裁裝置之第二較佳實施例之方塊圖。Figure 2 is a block diagram of a second preferred embodiment of the system bus arbitration device of the present invention.
11...第一仲裁單元11. . . First arbitration unit
111...第一仲裁模組111. . . First arbitration module
112...第二仲裁模組112. . . Second arbitration module
113...第三仲裁模組113. . . Third arbitration module
114...第四仲裁模組114. . . Fourth arbitration module
12...第二仲裁單元12. . . Second arbitration unit
13...控制單元13. . . control unit
14...輸出處理單元14. . . Output processing unit
141...儲存器141. . . Storage
142...判斷器142. . . Judger
143...處理器143. . . processor
8...系統匯流排8. . . System bus
901~916...外部裝置901~916. . . External device
Claims (8)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW97150059A TWI385528B (en) | 2008-12-22 | 2008-12-22 | Arbitration device for system bus |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW97150059A TWI385528B (en) | 2008-12-22 | 2008-12-22 | Arbitration device for system bus |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201025022A TW201025022A (en) | 2010-07-01 |
TWI385528B true TWI385528B (en) | 2013-02-11 |
Family
ID=44852406
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW97150059A TWI385528B (en) | 2008-12-22 | 2008-12-22 | Arbitration device for system bus |
Country Status (1)
Country | Link |
---|---|
TW (1) | TWI385528B (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI244001B (en) * | 2004-01-09 | 2005-11-21 | Magima Digital Information Co | An arbiter and the method thereof |
WO2007031912A1 (en) * | 2005-09-14 | 2007-03-22 | Koninklijke Philips Electronics N.V. | Method and system for bus arbitration |
-
2008
- 2008-12-22 TW TW97150059A patent/TWI385528B/en not_active IP Right Cessation
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI244001B (en) * | 2004-01-09 | 2005-11-21 | Magima Digital Information Co | An arbiter and the method thereof |
WO2007031912A1 (en) * | 2005-09-14 | 2007-03-22 | Koninklijke Philips Electronics N.V. | Method and system for bus arbitration |
Non-Patent Citations (1)
Title |
---|
陳育宏, 多層匯流排架構仲裁器之設計及實作, 陳育宏, 中華民國九十六年六月。 * |
Also Published As
Publication number | Publication date |
---|---|
TW201025022A (en) | 2010-07-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9396154B2 (en) | Multi-core processor for managing data packets in communication network | |
US7554355B2 (en) | Crossbar switch architecture for multi-processor SoC platform | |
US20070016709A1 (en) | Bus control system and a method thereof | |
US7908416B2 (en) | Data processing unit and bus arbitration unit | |
JP2012507820A (en) | Switch interface stacked die memory architecture | |
US6122680A (en) | Multiple channel data communication buffer with separate single port transmit and receive memories having a unique channel for each communication port and with fixed arbitration | |
EP1709543A2 (en) | A multiple address two channel bus structure | |
US7555593B1 (en) | Simultaneous multi-threading in a content addressable memory | |
EP3777059B1 (en) | Queue in a network switch | |
CN116028413A (en) | Bus arbiter, bus arbitration method, device and medium | |
US20120089759A1 (en) | Arbitrating Stream Transactions Based on Information Related to the Stream Transaction(s) | |
TW201423403A (en) | Efficient processing of access requests for a shared resource | |
US20070067531A1 (en) | Multi-master interconnect arbitration with time division priority circulation and programmable bandwidth/latency allocation | |
US9697118B1 (en) | Memory controller with interleaving and arbitration scheme | |
TWI385528B (en) | Arbitration device for system bus | |
JP2003271545A (en) | Data processing system | |
US7865645B2 (en) | Bus arbiter, bus device and system for granting successive requests by a master without rearbitration | |
US9282051B2 (en) | Credit-based resource allocator circuit | |
WO2022110681A1 (en) | Returning method and returning control apparatus for command response information, and electronic device | |
US20080270668A1 (en) | Method to Hide or Reduce Access Latency of a Slow Peripheral in a Pipelined Direct Memory Access System | |
CN111078598B (en) | Memory module data access control method, data access device and chip | |
US20230229612A1 (en) | Dynamic equality of service in a switch network | |
KR100581196B1 (en) | System on chip bus architecture providing multiple channel | |
KR20120066999A (en) | Direct memory access controller and operating method thereof | |
Shi et al. | Optimization of shared memory controller for multi-core system |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |