TWI384616B - Memory device with organic thin-film transistor (otft) structure - Google Patents

Memory device with organic thin-film transistor (otft) structure Download PDF

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TWI384616B
TWI384616B TW98130835A TW98130835A TWI384616B TW I384616 B TWI384616 B TW I384616B TW 98130835 A TW98130835 A TW 98130835A TW 98130835 A TW98130835 A TW 98130835A TW I384616 B TWI384616 B TW I384616B
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dielectric layer
layer
memory device
organic
charge trap
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TW201110341A (en
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chun yuan Huang
Ying Chih Chen
Tsung Syun Huang
Chiao Yang Cheng
Yan Kuin Su
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Univ Nat Cheng Kung
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Description

具備有機多介電層之記憶體元件Memory component with organic multi-dielectric layer

本發明是有關於一種有機記憶體元件,特別是有關於一種具備多介電層之有機記憶體元件。The present invention relates to an organic memory device, and more particularly to an organic memory device having a plurality of dielectric layers.

目前將有機薄膜電晶體與相當成熟之半導體製程技術結合,於不同型式的元件結構下,製作出具有非揮發性之有機記憶體元件,其有別於其他記憶體元件技術,如磁性記憶體元件及相變化記憶體元件等。在邏輯元件的操作上,負責提供或儲存資料,因此在急速發展之奈米元件技術領域佔有一席之地。At present, organic thin film transistors are combined with quite mature semiconductor process technology to produce non-volatile organic memory components under different types of device structures, which are different from other memory device technologies, such as magnetic memory components. And phase change memory components, etc. In the operation of logic components, responsible for providing or storing data, it has a place in the field of rapidly developing nano component technology.

已知的有機記憶體元件類型基本上可分為雙穩態雙端點元件及電晶體式三端點元件。其中雙穩態雙端點元件主要有電阻式及電容式結構。電晶體式記憶體元件其優點在於技術較成熟且結構製作彈性高。比較目前有機薄膜電晶體式之記憶體元件,基本作法有下列兩種:Known types of organic memory components are basically classified into bistable dual-end elements and transistor-type three-terminal elements. Among them, the bistable dual-end components mainly have a resistive and capacitive structure. The advantages of the transistor type memory element are that the technology is mature and the structure is highly flexible. Comparing the current organic thin film transistor type memory elements, there are two basic methods:

(1)以鐵電材料(ferroelectric materials)作為有機電晶體之絕緣層時,在閘極偏壓下,鐵電材料會產生感應電偶極而使薄膜內部極化(electric polarization)並打開通道,產生通道電流。但其缺點如下:一般若使用旋轉塗佈法製作鐵電絕緣層,絕緣層厚度無法有效降低,而使得操作電壓(寫入/抹除資料之偏壓)過高;再者單純以鐵電材料為絕緣層會造成嚴重的漏電流,使元件無法正常操作。另外若使用其他材料阻擋漏電流,卻會造成鐵電材料之極化效應喪失,以致記憶保留時間過短,元件亦無法使用。(1) When ferroelectric materials are used as the insulating layer of the organic transistor, under the gate bias, the ferroelectric material generates an induced electric dipole to electrically polarize the film and open the channel. Generate channel current. However, the disadvantages are as follows: Generally, if the ferroelectric insulating layer is formed by the spin coating method, the thickness of the insulating layer cannot be effectively reduced, and the operating voltage (bias of writing/erasing data) is too high; The insulation layer will cause severe leakage current, which will make the components unable to operate normally. In addition, if other materials are used to block the leakage current, the polarization effect of the ferroelectric material is lost, so that the memory retention time is too short and the components cannot be used.

(2)使用駐極體材料(electret)作為絕緣層,駐極體受到外加電場影響產生極化,因能長久保持極化強度而使得記憶保留時間可大幅延長,但目前現有的文獻指出,使用單層駐極體聚合物做為絕緣層,容易產生漏電流過大的缺點,而且一般具有駐極體特性之高分子聚合物其介電常數都不高,無法有效降低臨界電流。因此在習知之有機記憶體元件中,存在著漏電流過大及記憶保留時間過短的缺點,確有其必要改進之空間。(2) Using electret material as the insulating layer, the electret is polarized by the applied electric field, and the memory retention time can be greatly prolonged due to the long-term polarization maintaining, but the current literature indicates that the use A single-layer electret polymer is used as an insulating layer, which is prone to excessive leakage current, and a polymer having an electret characteristic generally has a low dielectric constant and cannot effectively reduce a critical current. Therefore, in the conventional organic memory element, there is a disadvantage that the leakage current is too large and the memory retention time is too short, and there is room for improvement.

有鑑於習知技術之問題,本發明之目的就是在提供一種具有有效延長元件記憶功能之記憶體元件,並用以解決漏電流過大之缺點。In view of the problems of the prior art, the object of the present invention is to provide a memory component having an effective function of extending the memory of the component, and to solve the disadvantage of excessive leakage current.

根據本發明之目的,提出一種具備有機多介電層之記憶體元件,其係包含一基板、一閘極電極、一多介電層、一半導體通道層、一汲極電極及一源極電極。其中基板係一氧化銦錫玻璃基板或氧化銦錫塑膠基板如聚對苯二甲二乙酯(poly(ethylene terephthalate),PET)或環烯烴共聚合物(cyclic olefin copolymer,COC)。閘極電極形成於基板上,多介電層形成於閘極電極上,半導體通道層、一汲極電極及一源極電極皆形成於多介電層上,且汲極電極及源極電極皆與半導體通道層電性接觸。According to an object of the present invention, a memory device having an organic multi-dielectric layer is provided, which comprises a substrate, a gate electrode, a multi-dielectric layer, a semiconductor channel layer, a drain electrode and a source electrode. . The substrate is an indium tin oxide glass substrate or an indium tin oxide plastic substrate such as poly(ethylene terephthalate, PET) or a cyclic olefin copolymer (COC). The gate electrode is formed on the substrate, the multi-dielectric layer is formed on the gate electrode, the semiconductor channel layer, a drain electrode and a source electrode are all formed on the multi-dielectric layer, and the drain electrode and the source electrode are both Electrically contacting the semiconductor channel layer.

根據本發明之目的,更提出一種多介電層,其係包含至少一第一電荷捕捉層、至少一漏電阻擋層及至少一第二電荷捕捉層。漏電阻擋層位於第一電荷捕捉層及第二電荷捕捉層之間。第一電荷捕捉層、第二電荷捕捉層及漏電阻擋層其主要材料皆為有機高分子聚合物。In accordance with the purpose of the present invention, a multi-dielectric layer is further provided comprising at least a first charge trapping layer, at least one leakage barrier layer, and at least one second charge trapping layer. The leakage barrier layer is between the first charge trap layer and the second charge trap layer. The main materials of the first charge trap layer, the second charge trap layer and the leakage barrier layer are all organic polymer polymers.

承上所述,因依本發明之多介電層記憶體元件,其可具有一或多個下述優點:As described above, the multi-dielectric memory element according to the present invention may have one or more of the following advantages:

(1)此具備有機多介電層之記憶體元件之高分子聚合物材料比之鐵電材料便宜許多。(1) The polymer material having the memory element of the organic multi-dielectric layer is much cheaper than the ferroelectric material.

(2)此具備有機多介電層之記憶體元件藉由高分子聚合物組成之多介電層結構,有效改善漏電流過大之缺點。(2) The memory element having the organic multi-dielectric layer is effective in improving the leakage current excessively by the multi-dielectric layer structure composed of the polymer.

(3)此具備有機多介電層之記憶體元件藉由高分子聚合物組成之多介電層結構,聚合物中之大量氫氧基可捕捉電荷,有效延長記憶效應,可對元件做多次讀寫動作。(3) The memory component with the organic multi-dielectric layer has a multi-dielectric layer structure composed of a polymer, and a large amount of hydroxyl groups in the polymer can capture charges, thereby effectively prolonging the memory effect, and can be used for components. Secondary read and write actions.

(4)此具備有機多介電層之記憶體元件之塑膠基板係一可撓式之材料,大大增加使用之方便性,如用以無線射頻辨識標籤(RFID)上。(4) The plastic substrate having the memory component of the organic multi-dielectric layer is a flexible material, which greatly increases the convenience of use, such as on a radio frequency identification tag (RFID).

以下將參照相關圖式,說明依本發明之具備有機多介電層之記憶體元件之實施例,為使便於理解,下述實施例中之相同元件係以相同之符號標示來說明。The embodiments of the memory device having the organic multi-dielectric layer according to the present invention will be described below with reference to the related drawings. For the sake of understanding, the same components in the following embodiments are denoted by the same reference numerals.

請參閱第1圖及第2圖,其分別為本發明之具備有機多介電層之記憶體元件(頂接觸式)之示意圖,及本發明之具備有機多介電層之記憶體元件(底接觸式)之示意圖。圖中,具備有機多介電層之記憶體元件包含一基板100、一閘極電極110、一多介電層160、一半導體通道層130、一源極電極140及一汲極電極150。其中閘極電極110形成於基板100上,多介電層160形成於閘極電極110上,半導體通道層130、源極電極140及汲極電極150皆形成於多介電層160上,其中源極電極140及汲極電極150皆與半導體通道130電性接觸。Please refer to FIG. 1 and FIG. 2 , which are respectively schematic diagrams of a memory device (top contact type) having an organic multi-dielectric layer, and a memory device having an organic multi-dielectric layer of the present invention. Schematic diagram of contact type). In the figure, a memory device having an organic multi-dielectric layer includes a substrate 100, a gate electrode 110, a multi-dielectric layer 160, a semiconductor channel layer 130, a source electrode 140, and a drain electrode 150. The gate electrode 110 is formed on the substrate 100, the multi-dielectric layer 160 is formed on the gate electrode 110, and the semiconductor channel layer 130, the source electrode 140 and the drain electrode 150 are formed on the multi-dielectric layer 160, wherein the source Both the electrode electrode 140 and the drain electrode 150 are in electrical contact with the semiconductor channel 130.

如上述之具備有機多介電層之記憶體元件,其製作方法如下:基板100係為氧化銦錫玻璃基板或為氧化銦錫塑膠基板,於此基板100使用標準光微影蝕刻術(Photo-Lithography)或網版印刷方式定義圖案,並以濕式蝕刻方式製作圖案化之閘極電極110,經過簡單之淨化(先後置於丙酮和異丙醇溶液中以超音波震盪)以完成基板100和閘極電極110之處理。其中塑膠基板(PET或COC)為可撓式之材料,大大增加使用之方便性。The memory device having the organic multi-dielectric layer is as follows: the substrate 100 is an indium tin oxide glass substrate or an indium tin oxide plastic substrate, and the substrate 100 is etched using standard photolithography (Photo- The pattern is defined by Lithography or screen printing, and the patterned gate electrode 110 is formed by wet etching, and after simple purification (sequentially placed in acetone and isopropanol solution to ultrasonically oscillate) to complete the substrate 100 and The processing of the gate electrode 110. Among them, the plastic substrate (PET or COC) is a flexible material, which greatly increases the convenience of use.

接下來,將具有氫氧基之有機高分子聚合物之多介電層160形成於閘極電極110上,多介電層160具有至少一第一電荷捕捉層120、至少一漏電阻擋層121及至少一第二電荷捕捉層122。多介電層160製作方式如下:首先將聚甲基丙烯酸乙酯(PHEMA)溶於甲醇中,聚甲基丙烯酸乙酯(PHEMA)濃度為0~20%,聚甲基丙烯酸甲酯(PMMA)溶於甲苯中,聚甲基丙烯酸甲酯(PMMA)濃度為0~20%,並旋轉塗佈於基板100及閘極電極110上,其塗佈方式或有滾輪塗佈、噴墨塗佈及網版印刷,並加熱蒸發溶劑使成薄膜;聚甲基丙烯酸乙酯(PHEMA)和聚甲基丙烯酸甲酯(PMMA)厚度皆為0~1微米,其中聚甲基丙烯酸乙酯(PHEMA)即形成第一電荷捕捉層120及第二電荷捕捉層122,聚甲基丙烯酸甲酯(PMMA)即形成漏電阻擋層121。Next, a multi-dielectric layer 160 of an organic polymer having a hydroxyl group is formed on the gate electrode 110. The multi-dielectric layer 160 has at least a first charge trap layer 120, at least one leakage barrier layer 121, and At least one second charge trapping layer 122. The multi-dielectric layer 160 is prepared as follows: First, polyethyl methacrylate (PHEMA) is dissolved in methanol, and the concentration of polyethyl methacrylate (PHEMA) is 0-20%, and polymethyl methacrylate (PMMA). Dissolved in toluene, polymethyl methacrylate (PMMA) concentration of 0~20%, and spin-coated on the substrate 100 and the gate electrode 110, the coating method or roller coating, inkjet coating and Screen printing, and heating to evaporate the solvent to form a film; polyethyl methacrylate (PHEMA) and polymethyl methacrylate (PMMA) are all 0 to 1 micron in thickness, of which polyethyl methacrylate (PHEMA) is The first charge trap layer 120 and the second charge trap layer 122 are formed, and the polymethyl methacrylate (PMMA) forms the leakage barrier layer 121.

特別說明第一電荷捕捉層120及第二電荷捕捉層122之主要功能為用以打開半導體通道層並捕捉及累積電荷使元件具有記憶效應,而漏電阻擋層121能有效減少源極及閘極間之漏電流。Specifically, the main functions of the first charge trap layer 120 and the second charge trap layer 122 are to open the semiconductor channel layer and capture and accumulate charges to make the device have a memory effect, and the leakage barrier layer 121 can effectively reduce the source and the gate. Leakage current.

其中第一電荷捕捉層120及第二電荷捕捉層122之具氫氧基之有機高分子聚合物亦能使用具有高密度氫氧基之聚乙烯醇(polyvinyl alcohol,PVA)或聚對位乙烯基酚(poly(4-vinyl phenol),PVP);一般而言,相同材料之分子量越高,其氫氧基越多,氫氧基之主要作用在於使聚合物薄膜表面呈現更高的極性,如此可形成更多的載子陷阱以捕捉電荷。另外,漏電阻擋層121之使用材料亦能使用有機或無機材料,如聚苯乙烯(Polystyrene,PS)、二氧化矽(SiO2 )及氮化矽(SiNx )等,又或能為高介電係數材料。The organic polymer having a hydroxyl group of the first charge trap layer 120 and the second charge trap layer 122 can also use a polyvinyl alcohol (PVA) or a poly-para-vinyl group having a high-density hydroxyl group. Poly(4-vinyl phenol), PVP; in general, the higher the molecular weight of the same material, the more hydroxyl groups, the main role of the hydroxyl group is to make the surface of the polymer film appear more polar, so More carrier traps can be formed to capture charge. In addition, the material used for the leakage barrier layer 121 can also use organic or inorganic materials, such as polystyrene (PS), cerium oxide (SiO 2 ), tantalum nitride (SiN x ), etc., or can be high-medium. Electrical coefficient material.

完成多介電層160結構後,使用熱蒸鍍技術,鍍上並五苯(Pentacene)以形成半導體通道層130,其厚度以60nm為最佳,隨後並鍍上源極電極140及汲極電極150金屬金(Au)。因此,此結構係為先鍍上半導體通道層130,再鍍上源極電極140及汲極電極金屬150,稱此結構為頂接觸式有機多介電層之記憶體元件;反之,若結構係為先鍍上源極電極140及汲極電極金屬150,再鍍上半導體通道層130,稱此結構為底接觸式有機多介電層之記憶體元件。After completing the structure of the multi-dielectric layer 160, pentacene is plated using a thermal evaporation technique to form a semiconductor channel layer 130 having a thickness of 60 nm, followed by plating of the source electrode 140 and the drain electrode. 150 metal gold (Au). Therefore, the structure is first plated with a semiconductor channel layer 130, and then plated with a source electrode 140 and a drain electrode metal 150, which is referred to as a memory element of a top contact organic multi-dielectric layer; The source electrode 140 and the drain electrode metal 150 are first plated, and then the semiconductor channel layer 130 is plated, and the structure is referred to as a memory element of the bottom contact organic multi-dielectric layer.

請參閱第3圖及第4圖,其分別為係為本發明之電荷捕捉效應(P型通道層)之示意圖,及本發明之電荷捕捉效應(N型通道層)之示意圖。圖中包含一電荷捕捉層200、一半導體通道層210、一源極電極230及一汲極電極220。其中半導體通道層210以並五苯(Pentacene)等P型半導體為組成材料者,稱之P型通道層;半導體通道層210以富勒烯衍生物(PCBM)等N型半導體材料旋轉塗佈於電荷捕捉層200上者,稱之N型通道層。Please refer to FIG. 3 and FIG. 4, which are schematic diagrams showing the charge trapping effect (P-type channel layer) of the present invention, and the charge trapping effect (N-type channel layer) of the present invention. The figure includes a charge trapping layer 200, a semiconductor channel layer 210, a source electrode 230 and a drain electrode 220. The semiconductor channel layer 210 is made of a P-type semiconductor such as pentacene, and is called a P-type channel layer; the semiconductor channel layer 210 is spin-coated with an N-type semiconductor material such as a fullerene derivative (PCBM). The charge trapping layer 200 is referred to as an N-type channel layer.

請參閱第5圖及第6圖,其分別為本發明之記憶保留時間測試曲線圖,及本發明之重複ON/OFF狀態切換響應圖。如第5圖所示,當閘極施加逆向偏壓時,電子從半導體通道層注入電荷捕捉層,並在介面間被捕捉而逐漸累積。當移除閘極偏壓後,介面間累積的電子不會完全消退,因此可於一段長時間內,維持半導體通道層打開並產生汲極至源極電流。第5圖清楚表示,將汲極至源極電壓固定於-40伏特,施加閘極偏壓-60伏特並維持500秒之後,將閘極偏壓回復0伏特並量測(讀取)通道電流值,汲極至源極電流從4×10-6 安培減少至2×10-8 安培,之後經過多次量測(讀取)亦不會造成汲極至源極電流明顯減少,雖然此時電流值比之起始值已大幅降低,但相對於元件之off狀態(汲極至源極電流~7×10-10 安培),仍達到接近102 倍之電流開關比。估計此記憶保留時間超過100小時,因此能有效延長記憶效應。第6圖之元件重複讀寫操作曲線並沒有觀察到因多次操作而影響電荷捕捉層之電荷捕捉效率。Please refer to FIG. 5 and FIG. 6 , which are respectively a memory retention time test curve diagram of the present invention, and a repeated ON/OFF state switching response diagram of the present invention. As shown in Fig. 5, when a reverse bias is applied to the gate, electrons are injected from the semiconductor channel layer into the charge trapping layer and are captured between the interfaces to gradually accumulate. When the gate bias is removed, the electrons accumulated between the interfaces do not completely subside, so the semiconductor channel layer can be opened and a drain-to-source current can be generated for a long period of time. Figure 5 clearly shows that the drain-to-source voltage is fixed at -40 volts, the gate bias is applied to -60 volts and maintained for 500 seconds, the gate bias is returned to 0 volts and the channel current is measured (read). The value of the drain-to-source current is reduced from 4×10 -6 amps to 2×10 -8 amps. After repeated measurements (reading), the drain-to-source current is not significantly reduced, although start value than the current value has been reduced substantially, but the elements with respect to the off state (drain to source current amps ~ 7 × 10 -10), still reached nearly 102 times the ratio of the current switch. It is estimated that this memory retention time exceeds 100 hours, so it can effectively extend the memory effect. The repeated read and write operation curves of the elements of Fig. 6 did not observe the charge trapping efficiency of the charge trapping layer due to multiple operations.

以上所述僅為舉例性,而非為限制性者。任何未脫離本發明之精神與範疇,而對其進行之等效修改或變更,均應包含於後附之申請專利範圍中。The above is intended to be illustrative only and not limiting. Any equivalent modifications or alterations to the spirit and scope of the invention are intended to be included in the scope of the appended claims.

100...基板100. . . Substrate

110...閘極電極110. . . Gate electrode

120...第一電荷捕捉層120. . . First charge trapping layer

121...漏電阻擋層121. . . Leakage barrier

122...第二電荷捕捉層122. . . Second charge trapping layer

130...半導體通道層130. . . Semiconductor channel layer

140...源極電極140. . . Source electrode

150...汲極電極150. . . Bipolar electrode

160...多介電層160. . . Multiple dielectric layer

200...第一電荷捕捉層200. . . First charge trapping layer

210...半導體通道層210. . . Semiconductor channel layer

220...汲極電極220. . . Bipolar electrode

以及as well as

230...源極電極230. . . Source electrode

第1圖 係為本發明之具備有機多介電層之記憶體元件(頂接觸式)之示意圖;1 is a schematic view showing a memory element (top contact type) having an organic multi-dielectric layer of the present invention;

第2圖 係為本發明之具備有機多介電層之記憶體元件(底接觸式)之示意圖;2 is a schematic view showing a memory element (bottom contact type) having an organic multi-dielectric layer of the present invention;

第3圖 係為本發明之電荷捕捉效應(P型通道層)之示意圖;Figure 3 is a schematic view showing the charge trapping effect (P-type channel layer) of the present invention;

第4圖 係為本發明之電荷捕捉效應(N型通道層)之示意圖;Figure 4 is a schematic view showing the charge trapping effect (N-type channel layer) of the present invention;

第5圖 係為本發明之記憶保留時間測試曲線圖;以及Figure 5 is a graph of the memory retention time test of the present invention;

第6圖 係為本發明之重複ON/OFF狀態切換響應圖。Fig. 6 is a diagram showing the repeated ON/OFF state switching response of the present invention.

100...基板100. . . Substrate

110...閘極電極110. . . Gate electrode

120...第一電荷捕捉層120. . . First charge trapping layer

121...漏電阻擋層121. . . Leakage barrier

122...第二電荷捕捉層122. . . Second charge trapping layer

130...半導體通道層130. . . Semiconductor channel layer

140...源極電極140. . . Source electrode

以及as well as

150...汲極電極150. . . Bipolar electrode

Claims (16)

一種具備有機多介電層之記憶體元件,其包含:一基板;一閘極電極,係形成於該基板上;一多介電層,係形成於該閘極電極上,該多介電層主要材料係有機高分子聚合物,該多介電層係用於打開半導體通道層並捕捉電荷使元件具有記憶效應,同時介電層中部分材料用以降低漏電流;一半導體通道層,係形成於該多介電層上;一汲極電極,係形成在該多介電層上,且與該半導體通道層電性接觸;以及一源極電極,係形成在該多介電層上,且與該半導體通道層電性接觸。A memory device having an organic multi-dielectric layer, comprising: a substrate; a gate electrode formed on the substrate; a multi-dielectric layer formed on the gate electrode, the multi-dielectric layer The main material is an organic high molecular polymer, which is used to open a semiconductor channel layer and capture charges to make the device have a memory effect, while some materials in the dielectric layer are used to reduce leakage current; a semiconductor channel layer is formed. On the multi-dielectric layer; a drain electrode is formed on the multi-dielectric layer and is in electrical contact with the semiconductor channel layer; and a source electrode is formed on the multi-dielectric layer, and Electrically contacting the semiconductor channel layer. 如申請專利範圍第1項所述之具備有機多介電層之記憶體元件,其中該基板係一氧化銦錫玻璃基板或氧化銦錫塑膠基板。The memory device having an organic multi-dielectric layer according to claim 1, wherein the substrate is an indium tin oxide glass substrate or an indium tin oxide plastic substrate. 如申請專利範圍第2項所述之具備有機多介電層之記憶體元件,其中該氧化銦錫塑膠基板係為氧化銦錫鍍於聚對苯二甲二乙酯(poly(ethylene terephthalate),PET)或環烯烴共聚合物(cyclic olefin copolymer(COC))上。The memory device having an organic multi-dielectric layer according to the second aspect of the invention, wherein the indium tin oxide plastic substrate is plated with indium tin oxide (poly(ethylene terephthalate), PET) or cyclic olefin copolymer (COC). 如申請專利範圍第1項所述之具備有機多介電層之記憶體元件,其中該有機高分子聚合物具有氫氧基。The memory device having an organic multi-dielectric layer according to claim 1, wherein the organic high molecular polymer has a hydroxyl group. 如申請專利範圍第1項所述之具備有機多介電層之記憶體元件,其中該多介電層係包含至少一第一電荷捕捉層、至少一漏電阻擋層及至少一第二電荷捕捉層,且該漏電阻擋層係位於該第一電荷捕捉層及該第二電荷捕捉層之間。The memory device having an organic multi-dielectric layer according to claim 1, wherein the multi-dielectric layer comprises at least a first charge trapping layer, at least one leakage barrier layer, and at least a second charge trapping layer And the leakage barrier layer is located between the first charge trap layer and the second charge trap layer. 如申請專利範圍第5項所述之具備有機多介電層之記憶體元件,其中該第一電荷捕捉層及第二電荷捕捉層之主要材料係為聚甲基丙烯酸乙酯(PHEMA)溶於甲醇中,該聚甲基丙烯酸乙酯(PHEMA)濃度係大於0且小於等於20%。The memory device having an organic multi-dielectric layer according to claim 5, wherein the main material of the first charge trap layer and the second charge trap layer is polyethyl methacrylate (PHEMA) dissolved. In methanol, the polyethyl methacrylate (PHEMA) concentration is greater than 0 and less than or equal to 20%. 如申請專利範圍第5項所述之具備有機多介電層之記憶體元件,其中該第一電荷捕捉層及該第二電荷捕捉層厚度係大於0且小於1微米。The memory device having an organic multi-dielectric layer according to claim 5, wherein the first charge trap layer and the second charge trap layer have a thickness greater than 0 and less than 1 micron. 如申請專利範圍第5項所述之具備有機多介電層之記憶體元件,其中該第一電荷捕捉層及該第二電荷捕捉層用以形成載子陷阱以捕捉並累積電荷。The memory device having an organic multi-dielectric layer according to claim 5, wherein the first charge trap layer and the second charge trap layer are used to form a carrier trap to capture and accumulate charges. 如申請專利範圍第5項所述之具備有機多介電層之記憶體元件,其中該漏電阻擋層之主要材料係為聚甲基丙烯酸甲酯(PMMA)溶於甲苯中,該聚甲基丙烯酸甲酯(PMMA)濃度係大於0且小於等於20%。The memory device having an organic multi-dielectric layer according to claim 5, wherein the main material of the leakage barrier layer is polymethyl methacrylate (PMMA) dissolved in toluene, the polymethacrylic acid. The methyl ester (PMMA) concentration is greater than 0 and less than or equal to 20%. 如申請專利範圍第5項所述之具備有機多介電層之記憶體元件,其中該漏電阻擋層厚度係大於0且小於1微米。A memory device having an organic poly dielectric layer as described in claim 5, wherein the leakage barrier layer has a thickness greater than 0 and less than 1 micron. 如申請專利範圍第5項所述之具備有機多介電層之記憶體元件,其中該漏電阻擋層用以降低該源極電極及該閘極電極間之漏電流。The memory device having an organic multi-dielectric layer according to claim 5, wherein the leakage barrier layer is configured to reduce leakage current between the source electrode and the gate electrode. 如申請專利範圍第1項所述之具備有機多介電層之記憶體元件,其中該半導體通道層係以P型半導體材料熱蒸鍍而成之P型通道層。The memory device having an organic multi-dielectric layer according to claim 1, wherein the semiconductor channel layer is a P-type channel layer formed by thermal evaporation of a P-type semiconductor material. 如申請專利範圍第12項所述之具備有機多介電層之記憶體元件,其中該P型半導體材料為並五苯(Pentacene)。A memory device having an organic multi-dielectric layer according to claim 12, wherein the P-type semiconductor material is pentacene. 如申請專利範圍第1項所述之具備有機多介電層之記憶體元件,其中該半導體通道層係以N型半導體材料組成之N型通道層。The memory device having an organic multi-dielectric layer according to claim 1, wherein the semiconductor channel layer is an N-type channel layer composed of an N-type semiconductor material. 如申請專利範圍第14項所述之具備有機多介電層之記憶體元件,其中該N型半導體材料為富勒烯衍生物(PCBM)。A memory device having an organic poly dielectric layer as described in claim 14, wherein the N-type semiconductor material is a fullerene derivative (PCBM). 如申請專利範圍第1項所述之具備有機多介電層之記憶體元件,其中該閘極電極、該汲極電極及該源極電極係為金屬或金屬氧化物結構。A memory device having an organic multi-dielectric layer according to claim 1, wherein the gate electrode, the drain electrode, and the source electrode are metal or metal oxide structures.
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