TWI384608B - Integrate circuit and embeded control circuit - Google Patents

Description

Integrated circuit and embedded control circuit

The present invention relates to a control circuit, and more particularly to a control circuit for controlling an operating mode of an integrated circuit and having electrostatic discharge protection.

Certain integrated circuits, such as flash memory, need to be supplied with different levels of voltage to operate in different modes of operation, such as reading, erasing, writing, and the like. In order to supply the control voltage required by the flash memory in different operation modes, in the power supply of the flash memory, a power selection circuit needs to be configured to select the operating voltage required for the flash memory.

1 is a circuit diagram of a selection circuit of a conventional power supply. Referring to FIG. 1 , the conventional selection circuit 100 includes a high voltage tracking module 110 , a level shift module 120 , and a switch module 130 . In the high voltage tracking module 110, a high voltage selection module 112 and well biasing modules 114 and 116 are included. The high voltage selection module 112 provides a voltage VPPI to the level shifting module 120 and the well biasing modules 114 and 116 for use. Well bias modules 114 and 116 provide voltages HVDD and HVPP, respectively, to account as well biases for PMOS transistors 132 and 134.

The level shifting module 120 includes level shifters 122 and 124. The level shifters 122 and 124 can be coupled to the bias voltage VPPI to convert the lower level control signals ENVDD and ENVPP into higher level control signals ZVDON and ZVPON and send them to the switch module 130. .

Switch module 130 includes PMOS transistors 132 and 134. The PMOS transistor 132 receives the voltage source VD1, the gate terminal receives the control signal ZVDON, and the source terminal is coupled to the source terminal of the PMOS transistor 134 to output a control voltage VPPIN1. In addition, the 汲 terminal of the PMOS transistor 134 is also coupled to the voltage source VP1, and the gate terminal is coupled to the control signal ZVPON.

When the flash memory is to be read, the control signal ZVDON can be pulled down to a low potential, so that the PMOS transistor 132 is turned on. At this time, the level of the control voltage VPPIN1 output by the switch module may be equal to the power source VD1. In contrast, when the flash memory is to be subjected to a write operation, the control signal ZVPON can be pulled down to a low potential, and the PMOS transistor 134 is turned on. Thereby, the potential of the control voltage VPPIN1 can be the potential of the voltage source VP1.

Although a power selection circuit is disposed in the power supply, different control voltages can be sent according to the operation mode of the flash memory, however, the volume of the overall circuit is not easily reduced.

Accordingly, the present invention provides an integrated circuit in which a control circuit for a power supply can be embedded in an external anti-static protection (ESD) circuit.

In addition, the present invention also provides a control circuit of a plurality of different embodiments, which can be embedded in an integrated circuit and can control the integrated circuit to perform different operations.

The invention provides an integrated circuit comprising an internal circuit, a plurality of signal pads, a first power switch and a second power switch. The internal circuit has at least one power terminal and one function signal terminal, and the signal pad includes at least a first signal pad and a second signal pad, wherein the first signal pad can be coupled to the power terminal of the internal circuit. In addition, the first power switch can determine whether to turn the input of the first signal pad to the function signal end of the internal circuit according to the first switching signal. In contrast, the second power switch can determine whether to turn the input of the second signal pad to the function signal terminal according to a second switching signal.

In some embodiments, the power switch can be a power transistor.

From another point of view, the present invention also provides a control circuit that can control the power switch to determine whether the power switch transmits the input of a signal pad to the function signal terminal of an integrated circuit. The control circuit of the present invention may include an inverter, a capacitor, an electrostatic protection switch, and a reverse gate. The input of the inverter can be grounded through the capacitor and receive the input of the pad to output a reverse signal to the ESD protection switch. Therefore, the ESD protection switch can determine whether to ground the signal pad according to the reverse signal. In addition, the input end of the inverter can also be coupled to the first input end of the reverse gate, and the second input end of the reverse gate can receive a reverse gate signal. In addition, the output of the anti-gate can also be coupled to the power switch to determine the state of the power switch according to the inputs of the first input and the second input.

From another point of view, the present invention further provides a control circuit for another power switch, including an inverter, a capacitor, a high voltage selection circuit, an electrostatic protection switch, and an anti-gate. The input of the inverter can be grounded through the capacitor and receive the output of the high voltage selection circuit. In addition, the inverter has a high voltage terminal and a low voltage terminal, wherein the high voltage terminal is coupled to the signal pad, and the low voltage terminal is coupled to a low voltage signal. Thereby, the inverter can output a reverse signal to the static electricity protection switch according to the state of the input end, and can cause the static electricity protection switch to determine whether to ground the signal welding pad according to the direction signal. In addition, the input end of the inverter can also be coupled to the first input end of the anti-gate, and the second input end and the output end of the anti-gate can be respectively coupled with a gate signal and a power switch to determine the power. The state of the switch.

In an embodiment of the invention, the high voltage selection circuit includes a first PMOS transistor and a second PMOS transistor. The source terminal of the first PMOS transistor is coupled to a high voltage source, and the gate terminal thereof is coupled to the signal pad. In addition, the source terminal and the gate terminal of the second PMOS transistor are respectively coupled to the gate terminal and the source terminal of the first PMOS transistor, and the 汲 terminal of the second PMOS transistor is coupled to the 汲 terminal of the first PMOS transistor. To the input of the inverter.

Since the control circuit of the present invention can be embedded in the integrated circuit, the present invention can effectively reduce the volume of the overall circuit as well as the hardware cost. In addition, the integrated circuit of the present invention can be operated differently by changing the state of the power switch.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

2 is a circuit block diagram of an integrated circuit in accordance with a preferred embodiment of the present invention. Referring to FIG. 2, the integrated circuit 200 provided in this embodiment may be an electronic erasable programmable read only memory device including an internal circuit 202 and a plurality of signal pads, such as 204 and 206. The internal circuit 202 has a power terminal VDD and a function signal terminal VPP. The power terminal VDD can be coupled to one of the signal pads, such as the signal pad 204. More specifically, the function signal terminal VPP can be coupled to another signal pad, such as the signal pad 206, through the embedded pad circuits 210 and 230.

In the actual operation of the integrated circuit 200, the signal pads 204 and 206 can be applied with voltage sources V1 and V2, respectively, during some operational cycles. These operation cycles are, for example, a stylized cycle or a read cycle. In the following embodiments, the potential of the voltage source V2 may be greater than the potential of the voltage source V1, but the invention is not limited thereto.

The pad circuits 210 and 230 are similar in structure and include power switches 212 and 232, respectively, and gate control circuits 214 and 234, respectively. The power switches 212 and 232 can respectively couple the signal pads 204 and 206 to the function signal terminal VPP. The gate control circuits 214 and 234 can respectively output the switching signals SW1 and SW2 to the corresponding power switches 212 and 232 to determine the state of both.

In this embodiment, power switches 212 and 232 may each include a power transistor, such as PMOS transistors P1 and P2. The source terminal and the drain terminal of the PMOS transistor P1 can be respectively coupled to the signal pad 204 and the function signal terminal VPP, and the gate terminal of the PMOS transistor P1 can be coupled to the gate control circuit 214 to receive the switching signal SW1. Similarly, the source and drain terminals of the PMOS transistor P2 can be coupled to the signal pad 206 and the function signal terminal VPP, respectively, and the gate terminal can be coupled to the corresponding gate control circuit 234 to receive the switching signal SW2.

In other embodiments, pad circuits 210 and 230 can also be configured with well control circuits 216 and 236, respectively. Well control circuit 216 can be coupled to power switches 212 and 232, respectively, and outputs a well control voltage HVDD and HVPP to power switches 212 and 232. Thereby, the driving ability of the PMOS transistors P1 and P2 due to the body effect is prevented from being lowered.

Several embodiments are provided below and the corresponding diagrams are incorporated to illustrate gate control circuits 214 and 234. However, it is known in the art that the following embodiments can be applied to the control circuits of other switches in addition to the gate control circuit of FIG. 2, and the following description will not be repeated for this point. .

First embodiment

FIG. 3A is a circuit diagram of a gate control circuit 214 in accordance with a first embodiment of the present invention. Referring to FIG. 3A, the gate control circuit 214 includes an inverter 302, an electrostatic discharge protection switch 304, a capacitor 306, and a reverse gate 308. The input terminal A1 of the inverter 302 can be coupled to the signal pad 204 through the resistor 310. In addition, the input terminal A1 of the inverter 302 can also be coupled to the first input end of the anti-gate 308, and the second input end and the output end of the anti-gate 308 can respectively receive a reverse gate signal NA1, and It is coupled to the gate terminal of the PMOS transistor P1. In the present embodiment, the anti-gate 308 has a high voltage terminal, and its potential can be the potential of the well control voltage HVDD.

Referring to FIG. 3A, the output of the inverter 302 can be coupled to the ESD protection switch 304, and the ESD protection switch 304 can couple the signal pad 204 to the low voltage VSS. In the present embodiment, the potential of the low voltage VSS is, for example, a ground potential. Therefore, in order to make the description concise, the low voltage VSS is assumed to be grounded as follows.

In the present embodiment, the inverter 302 may include an NMOS transistor N1 and a PMOS transistor P3. Wherein, the source terminal of the NMOS transistor N1 is grounded, and the 汲 terminal and the gate terminal are respectively coupled to the 汲 terminal and the gate terminal of the PMOS transistor P3, and the gate terminal of the NMOS transistor N1 is also coupled to the input of the NAND gate 308. End A1. In addition, the source terminal of the PMOS transistor P3 can be coupled to the signal pad 204, and the drain terminal can be coupled to the ESD protection switch 304 through the output terminal of the NMOS transistor N1 through the output of the inverter 302. .

The ESD protection switch 304 can also be implemented using an NMOS transistor N2. The source terminal of the NMOS transistor N2 can be grounded, the drain terminal can be coupled to the signal pad 204, and the gate terminal can be coupled to the output of the inverter 302.

FIG. 3B is a circuit diagram of a gate control circuit 234 in accordance with a first embodiment of the present invention. Referring to FIG. 3B, the circuit structure of the gate control circuit 234 is identical to that of the gate control circuit 214, and includes an inverter 322, an electrostatic discharge protection switch 324, a capacitor 326, and an inverse gate 328. Similarly, the input terminal A2 of the inverter 322 can be coupled to the high potential through the resistor 330 and the high voltage selection circuit, and can be coupled to the first input terminal of the NAND gate 328. The second input end of the anti-gate 328 can receive the anti-gate signal NA2, and the output end can be coupled to the gate end of the PMOS transistor P2. In addition, the anti-gate 328 also has a high voltage end. The potential can be the potential of the well control voltage HVPP. However, in the present embodiment, the potential is not required to be so high, and the reason will be described in detail later.

Similarly, the inverter 322 may also include a PMOS transistor P4 and an NMOS transistor N3. The source terminal of the NMOS transistor N3 can also be grounded, and the 汲 terminal and the gate terminal can be coupled to the 汲 terminal and the gate terminal of the PMOS transistor P4, respectively. In addition, the gate terminal and the drain terminal of the PMOS transistor P4 can be respectively coupled to the input terminal A2 and the output terminal of the inverter 322, and the source terminal of the PMOS transistor P4 can be coupled to the signal pad 206.

In addition, the ESD protection switch 324 can also be implemented using the NMOS transistor N4. Similarly, the source terminal of the NMOS transistor N4 can be grounded, the gate terminal can be coupled to the output of the inverter 322, and the drain terminal can be coupled to the signal pad 206.

In particular, the gate control circuit 234 further includes a high voltage selection circuit 333 that can be coupled to the input terminal A2 of the inverter 322 through the resistor 330 and can be coupled to the high voltage terminal of the inverse gate 328. .

4 is a circuit diagram of a high voltage selection circuit in accordance with a preferred embodiment of the present invention. Referring to FIG. 4, the high voltage selection circuit 333 includes PMOS transistors P5 and P6. The source terminals of the PMOS transistors P5 and P6 can be coupled to the voltage source V3 and the signal pad 206, respectively. The 汲 terminal of each PMOS transistor is coupled to the NMOS terminal of the other PMOS transistor in addition to being coupled to its own N-type well to form an internal power supply output terminal Vx. Additionally, the gate terminals of each PMOS transistor are cross-coupled to the source terminals of each other. By switching between the PMOS transistors P5 and P6, a higher voltage can be selected as the output voltage of the internal power supply output terminal Vx in the voltage source V3 and the signal pad 206. In this embodiment, the input signal Vx can also be sent to the high voltage end of the NAND gate 328.

FIG. 5 is a table showing the status of signals inside a gate control circuit according to the first embodiment of the present invention. Referring to FIGS. 2, 3A, 3B and 5 in combination, when the integrated circuit 200 is required to perform the writing operation, the inverse gate signals NA1 and NA2 can be made low (L) and high (H), respectively. At this time, the reverse gate 308 will output the switching signal SW1 of the state H to the PMOS transistor P1 because the potential of one of the input terminals is L, causing the PMOS transistor P1 to be turned off.

Referring to FIG. 4 in combination, on the other hand, in the gate control circuit 234, since the signal pad 206 is applied with the voltage source V2, the potential of the voltage source V2 can be greater than the potential of the voltage source V3, causing the PMOS transistor P5 to be turned off. And the PMOS transistor P6 is turned on. At this time, the potential of the input terminal signal Vx is the potential of the voltage source V2. In other words, the potential of the input terminal A2 of the inverter 322 is H. Therefore, in the state where the input terminal is H, the reverse gate 328 outputs the switching signal SW2 of the state L to the PMOS transistor P2 to be turned on. Further, since the potential of the input terminal A2 of the inverter 322 is V2, the reverse signal INV2 of the state L is output to the NMOS transistor N4, and the NMOS transistor N4 is turned off. Thereby, the potential of the voltage source V2 can be sent to the function signal terminal VPP via the PMOS transistor P2, and the integrated circuit can be programmed.

In contrast, if the integrated circuit 200 enters the read cycle, the inverse gate signals NA1 and NA2 can be made H and L, respectively. At this time, the reverse gate 328 in the gate control circuit 234 will turn off the switching signal SW2 of the state H to the PMOS transistor P2 because the state of one of the input terminals is L. In contrast, the gate 308 in the gate control circuit 214 may have a potential of the voltage source V1 at its first input terminal, and a potential of the second input terminal is also H, and the switching signal SW1 of the output state is L. PMOS transistor P1. In addition, since the input terminal A1 of the inverter 302 is V1, the reverse signal INV1 of the state L can be output to the NMOS transistor N2, and the NMOS transistor N2 can be turned off. Thereby, the potential of the voltage source V1 can be sent to the function signal terminal VPP via the PMOS transistor P1 to cause the integrated circuit 200 to perform a read operation.

On the other hand, if the electrostatic discharge of the signal pad 204 occurs, the input terminal A1 of the inverter 302 couples the input terminal A1 to the low voltage VSS because the capacitor 306 cannot instantaneously change the state of the state. At this time, the gate 308 is also turned on because the potential of one of the input terminals A1 is L, so that the switching signal SW1 of the output state H is supplied to the PMOS transistor P1. Further, since the potential of the input terminal A1 of the inverter 302 is VSS, the reverse signal INV1 of the state H can be output to the NMOS transistor N2 and turned on. Thereby, the current of the electrostatic discharge is not sent to the internal circuit 202, but can be discharged in accordance with the path through which the NMOS transistor N2 is turned on.

Similarly, if the signal pad 206 is electrostatically discharged, the input signal Vx output from the high voltage selection circuit 333 is forcibly pulled up to a very high potential in a short time. At this time, since the potential across the capacitor 326 cannot be changed in a short time, the capacitor 326 couples the low voltage VSS to the input terminal A2 of the inverter 322. At this time, the NAND gate 328 will output a switching signal SW2 of the state H to turn off the PMOS transistor P2 because the potential of one of the input terminals is L. In addition, the inverter 322 outputs a reverse signal INV2 of state H to the NMOS transistor N4 to turn it on. Thereby, the current of the electrostatic discharge is blocked by the power switch 232, and is discharged according to the path in which the NMOS transistor N4 is turned on, thereby avoiding the inflow of the internal circuit 202 and causing damage to the integrated circuit 200.

Second embodiment

FIG. 6A is a circuit diagram of a gate control circuit 214 in accordance with a second embodiment of the present invention. Referring to FIG. 6A, in the embodiment, the gate control circuit 214 further includes an inverter 602. The input terminal receives an operation signal ZENVDD, and generates an anti-gate signal NA1 according to the operation signal ZENVDD. 308. In addition, the inverter 602 has a high voltage terminal coupled to the signal pad 204 for receiving the voltage signal V1.

FIG. 6B is a circuit diagram of a gate control circuit 234 in accordance with a second embodiment of the present invention. Referring to FIG. 6B, similarly, in the gate control circuit 234, an inverter 612 may be disposed, and an input terminal is coupled to an operation signal ZENVPP to output a reverse gate signal NA2 to the inverse gate 328. The inverter 612 also has a high voltage terminal, which can be coupled to the input signal Vx output by the high voltage selection circuit 333.

In some alternative embodiments, the gate control circuit 234 may further include a buffer 614 having an input coupled to the output of the NAND gate 328, and the output of the buffer 614 may be coupled to the gate terminal of the PMOS transistor P2. Thereby, the switching signal SW2 generated by the gate 328 can be transmitted to the PMOS transistor P2 through the buffer 614. Similarly, the buffer 614 also has a high voltage terminal, which can also be coupled to the input signal Vx output by the high voltage selection circuit 333.

Third embodiment

FIG. 7A is a circuit diagram of a gate control circuit 214 in accordance with a third embodiment of the present invention. Referring to FIG. 7A, in the embodiment, the gate control circuit 214 may further include an anti-gate 702 and an NMOS transistor N5. The first input end of the anti-gate 702 can be coupled to the operation signal ZENVDD, the second input end can be coupled to the input end A1 of the inverter 302, and the output end can be coupled to the gate end of the NMOS transistor N5. In addition, the source terminal and the NMOS terminal of the NMOS transistor N5 may be coupled to the source terminal and the NMOS terminal of the PMOS transistor P1, respectively.

8 is a table showing the status of signals inside a gate control circuit in accordance with the second and third embodiments of the present invention. Referring to FIG. 7A and FIG. 8 together, during the writing period, the operation signal ZENVDD may be H, so the gate signal NA1 may be L. In addition, since the potential of the input terminal A1 of the inverter 302 is also H during the writing period, the output of the inverse gate 702 is L, causing the NMOS transistor N5 to be turned off.

In contrast, during the read cycle, the control signal ZENVDD is L, so that the reverse gate signal NA1 is H. In addition, the NAND gate 702 will send a state H to the gate terminal of the NMOS transistor N5 because one of the input terminals is L, so that the NMOS transistor N5 is turned on.

FIG. 7B is a circuit diagram of a gate control circuit 234 in accordance with a third embodiment of the present invention. Referring to FIG. 7B, in the embodiment, the gate control circuit 234 can also have a reverse gate 712 and an NMOS transistor N6, and the coupling relationship and operation principle of the two can be referred to by those skilled in the art. The description of the gate 702 and the NMOS transistor N5 will not be repeated here.

Fourth embodiment

Referring back to FIG. 2, FIG. 4 and FIG. 5, the gate control circuit 234 outputs a switching signal SW2 of state H during the read cycle to turn off the PMOS transistor P2. At this time, it is not necessary to apply a V2 voltage on the signal pad 206. In some embodiments, the potential of the signal pad 206 may be V1, VSS, or even floating during the read cycle. However, if the potential V2 on the signal pad 206 rises to the equipotential in synchronization with the potential of the voltage source V3, the potential of the output terminal Vx of the high voltage selection circuit 333 is equal to the potential of the voltage source V2 minus the voltage of the diode. drop.

FIG. 9A is a circuit diagram of a gate control circuit 234 in accordance with a fourth embodiment of the present invention. Referring to FIG. 9A, in order to meet the above situation, in the embodiment, the gate control circuit 234 can also be configured with a diode 902, the anode end of which can be coupled to the signal pad 206, and the cathode end can be coupled to the PMOS. The source terminal of the transistor P4. By the voltage drop of the diode 902, the potential V2 of the signal pad 206 and the voltage source V3 rise to the equipotential level, and the input signal Vx is only the potential of the voltage source V2. The case of the voltage drop of the diode.

The gate control circuit disclosed in FIGS. 9B and 9C is also the same as FIG. 9A except that the PMOS transistors P7 and P8 are used in place of the diode 802. In FIG. 9B, the source terminal of the PMOS transistor P7 can be coupled to the signal pad 206, and the gate terminal and the drain terminal can be coupled to the gate terminal and the source terminal of the PMOS transistor P4, respectively. In addition, in FIG. 9C, the source terminal of the PMOS transistor P8 can also be coupled to the signal pad 206, and the gate terminal and the drain terminal can be coupled to the source terminal of the PMOS transistor P4.

FIG. 10A is a circuit diagram of a well control circuit 216 in accordance with a preferred embodiment of the present invention. Referring to FIG. 10A, the well control circuit 216 includes PMOS transistors P9 and P10. The source terminals of the PMOS transistors P9 and P10 are respectively coupled to the voltage V1 of the signal pad 204 and the voltage terminal VDDIN, and the sum of the two is connected with the N-well of the circuit, and the other PMOS. The germanium terminals of the transistor are connected in common to form a well control voltage HVDD to the well end of the PMOS transistor P1 to avoid a decrease in driving capability of the PMOS transistor due to the bulk effect.

In the present embodiment, the well control voltage HVDD can be further turned to the high voltage terminal of the gate 308 in the gate control circuit 214 to enable the PMOS transistor P1 to operate normally.

FIG. 10B is a circuit diagram of a well control circuit 236 in accordance with a preferred embodiment of the present invention. Referring to FIG. 10B, like well control circuit 216, well control circuit 236 also includes PMOS transistors P11 and P12. The source terminals of the PMOS transistors P11 and P12 are respectively coupled to the voltage V2 of the signal pad 206 and the voltage terminal VPPIN2, and the 汲 terminals of the PMOS transistors are connected to the N-type well terminal and the other PMOS battery. The germanium terminal of the crystal is connected in common to output the well control voltage HVPP to the PMOS transistor P2 to avoid the driving capability of the PMOS transistor due to the bulk effect.

In some embodiments, the well control voltage HVPP can also be sent to the high voltage terminals of the gate control circuit 234 and the gate 328 and the inverter 612. However, since the gate control circuit 234 is only turned on during the write period, the PMOS transistor P2 is turned on. Therefore, in some alternative embodiments, the high voltage terminals of the anti-gate 328 and the inverter 612 need not be coupled to the well control voltage HVPP, but may be coupled to the input signal Vx.

In summary, since the gate control circuit of the present invention can be embedded in the integrated circuit, the integrated circuit provided by the present invention can have a small volume. Further, since the present invention turns off the power switch after the occurrence of the electrostatic discharge, and the electrostatic discharge protection switch is turned on, the present invention can sufficiently protect the internal circuit of the integrated circuit from the electrostatic discharge.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

100. . . Selection circuit

110. . . High voltage tracking module

112. . . High voltage selection module

114, 116. . . Well bias module

120. . . Level offset module

122, 124. . . Level shifter

130. . . Switch module

132, 134, P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12. . . PMOS transistor

200. . . Integrated circuit

202. . . Internal circuit

204, 206. . . Signal pad

210, 230. . . Pad circuit

212, 232. . . Power switch

214, 234. . . Gate control circuit

302, 322, 602, 612. . . Inverter

304, 324. . . Electrostatic discharge protection switch

306, 326. . . capacitance

308, 328, 702, 712. . . Reverse gate

310, 330. . . resistance

333. . . High voltage selection circuit

614. . . buffer

902. . . Dipole

A1, A2. . . Inverter input

INV1, INV2. . . Reverse signal

N1, N2, N3, N4, N5, N6. . . NMOS transistor

NA1, NA2. . . Anti-gate signal

SW1, SW2. . . Switch signal

V1, V2, V3, VD1, VP1. . . power source

VDD. . . Power terminal

VPP. . . Functional signal end

VPPI, HVDD, HVPP, HVDD, VPPIN1, VPPIN2, VDDIN, ENVDD, ENVPP. . . Control voltage

VSS. . . low voltage

Vx. . . Input signal

ZENVDD, ZENVPP. . . Operation signal

1 is a circuit diagram of a selection circuit of a conventional power supply.

2 is a circuit block diagram of an integrated circuit in accordance with a preferred embodiment of the present invention.

3A and 3B are circuit diagrams respectively showing a gate control circuit in accordance with a first embodiment of the present invention.

4 is a circuit diagram of a high voltage selection circuit in accordance with a preferred embodiment of the present invention.

FIG. 5 is a table showing the status of signals inside a gate control circuit according to the first embodiment of the present invention.

6A and 6B are circuit diagrams respectively showing a gate control circuit in accordance with a second embodiment of the present invention.

7A and 7B are circuit diagrams respectively showing a gate control circuit in accordance with a third embodiment of the present invention. .

8 is a table showing the status of signals inside a gate control circuit in accordance with the second and third embodiments of the present invention.

9A, 9B and 9C are circuit diagrams respectively showing a gate control circuit in accordance with a fourth embodiment of the present invention.

10A and 10B are circuit diagrams of a well control circuit in accordance with a preferred embodiment of the present invention.

200. . . Integrated circuit

202. . . Internal circuit

204, 206. . . Signal pad

210, 230. . . Pad circuit

212, 232. . . Power switch

214, 234. . . Gate control circuit

HVDD, HVPP. . . Well control voltage

P1, P2. . . PMOS transistor

SW1, SW2. . . Switch signal

V1, V2. . . power source

VDD. . . Power terminal

VPP. . . Functional signal end

VPPIN2, VDDIN. . . Control voltage

Claims (13)

An integrated circuit includes: an internal circuit having at least one power terminal and a functional signal terminal; and a plurality of signal pads having at least a first signal pad and a second signal pad, wherein the first signal soldering The pad is coupled to the power terminal; a first power switch determines whether to turn the input of the first signal pad to the function signal end according to a first switching signal; and a second power switch according to a second The switching signal determines whether the input of the second signal pad is turned on to the function signal terminal. The integrated circuit of claim 1, wherein the first power switch is a first power transistor, and a source terminal is coupled to the signal pad, and an antenna terminal is coupled to the function signal terminal, and The gate terminal receives the first switching signal, and the well terminal is coupled to a well control voltage signal. The integrated circuit of claim 2, further comprising a first gate control circuit coupled to the gate terminal of the first power transistor to generate the first switching signal, and the first gate The control circuit includes: a first inverter receiving the input of the first pad to output a first reverse signal; a first capacitor coupling the input of the first inverter to the ground; a first static protection switch coupled to the first inverter to determine whether to ground the first signal pad according to the first reverse signal; and a first reverse gate coupled to the first input end To the input end of the first inverter, the second input terminal receives a first anti-gate signal, and the output end is coupled to the gate terminal of the first power transistor to output the first switching signal . The integrated circuit of claim 2, further comprising a first well control circuit coupled to the well end of the first power transistor, wherein the first well control circuit has: a first PMOS transistor The source terminal is coupled to the first signal pad, the gate terminal is coupled to a control voltage signal, and the 汲 terminal is coupled to its own well terminal; and a second PMOS transistor is coupled to the source terminal. Connected to the control voltage, the gate terminal is coupled to the first signal pad, and the second terminal of the second PMOS transistor is coupled to its own well terminal and to the first terminal of the first PMOS transistor The first power transistor is coupled to the first power transistor to output the first well control voltage. The integrated circuit of claim 1, wherein the second power switch is a second power transistor, the source terminal is coupled to the signal pad, and the terminal is coupled to the function signal terminal. The extreme receives the second switching signal and the well terminal is coupled to a well control voltage. The integrated circuit of claim 5, further comprising a second gate control circuit coupled to the gate terminal of the second power transistor to generate the second switching signal, and the second gate The control circuit includes: a second inverter having a high voltage terminal and a low voltage terminal, wherein the high voltage terminal is coupled to the second signal pad, and the low voltage terminal is grounded, and the second inverter Further, a second reverse signal is output according to the state of the input end; a second capacitor is grounded to the input of the second inverter; and a high voltage selection circuit is coupled to the input end of the second inverter; a second static electricity protection switch coupled to the second inverter to determine whether to ground the second signal pad according to the second reverse signal; and a second reverse gate coupled to the first input end Connected to the input end of the second inverter, the second input terminal receives a second reverse gate signal, and the output terminal is coupled to the gate terminal of the second power transistor to output the second switch Signal. The integrated circuit of claim 6, wherein the high voltage selection circuit comprises: a third PMOS transistor having a source terminal coupled to a voltage source and a gate terminal coupled to the second signal electrode a pad, the other end of which is connected to its own well terminal; and a fourth PMOS transistor whose source terminal and gate terminal are respectively coupled to the gate terminal and the source terminal of the third PMOS transistor, and the fourth PMOS The germanium terminal of the transistor is coupled to the input terminal of the second inverter in conjunction with the drain terminal of the third PMOS transistor. The integrated circuit of claim 5, further comprising a second well control circuit coupled to the second power transistor to output a second well control voltage to determine the channel of the second power transistor And the second well control circuit has: a fifth PMOS transistor having a source terminal coupled to the signal pad, and a gate terminal coupled to the functional signal terminal and a second terminal coupled to the terminal And a sixth PMOS transistor, the source terminal and the gate terminal are respectively coupled to the gate terminal and the source terminal of the fifth PMOS transistor, and the PMOS terminal of the sixth PMOS transistor is opposite to the fifth PMOS The 汲 terminal of the transistor is commonly coupled to the second power transistor to output the second well control voltage. A control circuit for a power switch, wherein the power switch is configured to couple a signal pad to a function signal end of an integrated circuit, and the control circuit includes: an inverter for receiving an input of the pad to Outputting a reverse signal; a capacitor, grounding the input of the inverter; and an electrostatic protection switch coupled to the inverter to determine whether to ground the signal pad according to the reverse signal; The first input end of the gate is coupled to the input end of the inverter, the second input end receives a reverse gate signal, and the output end is coupled to the power switch to determine its state. The control circuit of claim 9, wherein the static protection switch is an NMOS transistor, the source terminal of which is coupled to the signal pad, the electrode is extremely grounded, and the gate terminal receives the reverse signal. A control circuit for a power switch, wherein the power switch is configured to couple a signal pad to a function signal end of an integrated circuit, and the control circuit comprises: an inverter having a high voltage end and a low a voltage terminal, wherein the high voltage terminal is coupled to the signal pad, and the low voltage terminal is coupled to a low voltage signal, and the inverter outputs a reverse signal according to a state of the input end thereof; The input of the inverter is grounded; a high voltage selection circuit is coupled to the input end of the inverter; and an electrostatic protection switch coupled to the inverter to determine whether to solder the signal according to the reverse signal a grounding pad; and a reverse gate having a first input coupled to the input of the inverter, a second input receiving a reverse gate signal, and an output coupled to the power switch to Determine its status. The control circuit of claim 11, wherein the high voltage selection circuit comprises: a first PMOS transistor having a source terminal coupled to a high voltage source and a gate terminal coupled to the signal pad; And a second PMOS transistor, the source terminal and the gate terminal are respectively coupled to the gate terminal and the source terminal of the first PMOS transistor, and the 汲 terminal of the second PMOS transistor is opposite to the first PMOS transistor Extremely coupled to the input of the inverter. The control circuit of claim 11, wherein the static protection switch is an NMOS transistor, the source terminal of which is coupled to the signal pad, the ground electrode is extremely grounded, and the gate terminal receives the reverse signal.