TWI384608B - Integrate circuit and embeded control circuit - Google Patents
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Description
本發明是有關於一種控制電路,且特別是有關於一種用於控制積體電路之工作模式,並具有靜電放電防護的控制電路。The present invention relates to a control circuit, and more particularly to a control circuit for controlling an operating mode of an integrated circuit and having electrostatic discharge protection.
某些特定的積體電路,例如快閃記憶體,需要被供應不同位準的電壓,使其工作在不同的操作模式,例如讀取、抹除、寫入等動作。而為了供應快閃記憶體在不同操作模式下所需要的控制電壓,在快閃記憶體的電源供應器中,還需要配置一電源選擇電路,以選擇快閃記憶體所需的工作電壓。Certain integrated circuits, such as flash memory, need to be supplied with different levels of voltage to operate in different modes of operation, such as reading, erasing, writing, and the like. In order to supply the control voltage required by the flash memory in different operation modes, in the power supply of the flash memory, a power selection circuit needs to be configured to select the operating voltage required for the flash memory.
圖1繪示為習知之電源供應器之選擇電路的電路圖。請參照圖1,習知的選擇電路100中,包括高電壓追蹤模組110、位準偏移模組120和開關模組130。在高電壓追蹤模組110中,包括高壓選擇模組112和井偏壓模組114和116。高壓選擇模組112會提供一電壓VPPI給位準偏移模組120,以及井偏壓模組114和116來使用。而井偏壓模組114和116則會分別提供電壓HVDD和HVPP,以當作PMOS電晶體132和134的井偏壓。1 is a circuit diagram of a selection circuit of a conventional power supply. Referring to FIG. 1 , the conventional selection circuit 100 includes a high voltage tracking module 110 , a level shift module 120 , and a switch module 130 . In the high voltage tracking module 110, a high voltage selection module 112 and well biasing modules 114 and 116 are included. The high voltage selection module 112 provides a voltage VPPI to the level shifting module 120 and the well biasing modules 114 and 116 for use. Well bias modules 114 and 116 provide voltages HVDD and HVPP, respectively, to account as well biases for PMOS transistors 132 and 134.
位準偏移模組120包括位準偏移器122和124。位準偏移器122和124可以耦接偏壓VPPI,以將較低位準的控制訊號ENVDD和ENVPP,轉換為較高位準的控制訊號ZVDON和ZVPON,並將其送至開關模組130中。The level shifting module 120 includes level shifters 122 and 124. The level shifters 122 and 124 can be coupled to the bias voltage VPPI to convert the lower level control signals ENVDD and ENVPP into higher level control signals ZVDON and ZVPON and send them to the switch module 130. .
開關模組130包括PMOS電晶體132和134。其中,PMOS電晶體132的汲極端接收電壓源VD1,閘極端接收控制訊號ZVDON,而源極端則與PMOS電晶體134的源極端互相耦接,以輸出一控制電壓VPPIN1。另外,PMOS電晶體134的汲極端也耦接電壓源VP1,而閘極端則是耦接控制訊號ZVPON。Switch module 130 includes PMOS transistors 132 and 134. The PMOS transistor 132 receives the voltage source VD1, the gate terminal receives the control signal ZVDON, and the source terminal is coupled to the source terminal of the PMOS transistor 134 to output a control voltage VPPIN1. In addition, the 汲 terminal of the PMOS transistor 134 is also coupled to the voltage source VP1, and the gate terminal is coupled to the control signal ZVPON.
當快閃記憶體要進行讀取的操作時,則控制訊號ZVDON可以下拉至低電位,使得PMOS電晶體132導通。此時,開關模組所輸出的控制電壓VPPIN1的位準可以等於電源VD1。相對地,當快閃記憶體要進行寫入操作時,則控制訊號ZVPON則可以下拉至低電位,而使得PMOS電晶體134導通。藉此,控制電壓VPPIN1的電位就可以是電壓源VP1的電位。When the flash memory is to be read, the control signal ZVDON can be pulled down to a low potential, so that the PMOS transistor 132 is turned on. At this time, the level of the control voltage VPPIN1 output by the switch module may be equal to the power source VD1. In contrast, when the flash memory is to be subjected to a write operation, the control signal ZVPON can be pulled down to a low potential, and the PMOS transistor 134 is turned on. Thereby, the potential of the control voltage VPPIN1 can be the potential of the voltage source VP1.
雖然在電源供應器中配置有電源選擇電路,可以依據快閃記憶體的操作模式而送出不同位準的控制電壓,然而,卻會使得整體電路的體積不容易縮小。Although a power selection circuit is disposed in the power supply, different control voltages can be sent according to the operation mode of the flash memory, however, the volume of the overall circuit is not easily reduced.
因此,本發明提供一種積體電路,可以在外部防靜電保護(ESD)電路內嵌有電源的控制電路。Accordingly, the present invention provides an integrated circuit in which a control circuit for a power supply can be embedded in an external anti-static protection (ESD) circuit.
另外,本發明也提供多個不同實施例的控制電路,可以內嵌在積體電路中,並可以控制積體電路進行不同的運作。In addition, the present invention also provides a control circuit of a plurality of different embodiments, which can be embedded in an integrated circuit and can control the integrated circuit to perform different operations.
本發明提供一種積體電路,包括一內部電路、多個訊號焊墊、一第一功率開關和一第二功率開關。內部電路至少具有一電源端和一功能訊號端,而訊號焊墊則至少包括一第一訊號焊墊和一第二訊號焊墊,其中第一訊號焊墊可以耦接至內部電路的電源端。另外,第一功率開關可以依據第一開關訊號而決定是否將第一訊號焊墊的輸入導通至內部電路的功能訊號端。相對地,第二功率開關則可以依據一第二開關訊號而決定是否將該第二訊號焊墊的輸入導通至該功能訊號端。The invention provides an integrated circuit comprising an internal circuit, a plurality of signal pads, a first power switch and a second power switch. The internal circuit has at least one power terminal and one function signal terminal, and the signal pad includes at least a first signal pad and a second signal pad, wherein the first signal pad can be coupled to the power terminal of the internal circuit. In addition, the first power switch can determine whether to turn the input of the first signal pad to the function signal end of the internal circuit according to the first switching signal. In contrast, the second power switch can determine whether to turn the input of the second signal pad to the function signal terminal according to a second switching signal.
在一些實施例中,功率開關可以是一功率電晶體。In some embodiments, the power switch can be a power transistor.
從另一觀點來看,本發明也提供一種控制電路,可以控制上述的功率開關,以決定功率開關是否將一訊號焊墊的輸入傳送至一積體電路的功能訊號端。本發明之控制電路可以包括反向器、電容、靜電防護開關和一反及閘。反向器的輸入可以透過電容接地,並且接收焊墊的輸入,以輸出一反向訊號給靜電防護開關。藉此,靜電防護開關可以依據反向訊號而決定是否將訊號焊墊接地。另外,反向器的輸入端還可以耦接反及閘的第一輸入端,而反及閘的第二輸入端則可以接收一反及閘訊號。此外,反及閘的輸出端還可以耦接功率開關,以依據第一輸入端和第二輸入端的輸入而決定功率開關的狀態。From another point of view, the present invention also provides a control circuit that can control the power switch to determine whether the power switch transmits the input of a signal pad to the function signal terminal of an integrated circuit. The control circuit of the present invention may include an inverter, a capacitor, an electrostatic protection switch, and a reverse gate. The input of the inverter can be grounded through the capacitor and receive the input of the pad to output a reverse signal to the ESD protection switch. Therefore, the ESD protection switch can determine whether to ground the signal pad according to the reverse signal. In addition, the input end of the inverter can also be coupled to the first input end of the reverse gate, and the second input end of the reverse gate can receive a reverse gate signal. In addition, the output of the anti-gate can also be coupled to the power switch to determine the state of the power switch according to the inputs of the first input and the second input.
從另一觀點來看,本發明更提供另一種功率開關的控制電路,包括反向器、電容、高電壓選擇電路、靜電防護開關和反及閘。反向器的輸入可以透過電容接地,並且接收高電壓選擇電路的輸出。另外,反向器還具有高電壓端和低電壓端,其中高電壓端耦接訊號焊墊,而低電壓端則耦接一低電壓訊號。藉此,反向器就可以依據輸入端的狀態而輸出反向訊號給靜電防護開關,並且可以使得靜電防護開關依據該向訊號而決定是否將訊號焊墊接地。此外,反向器的輸入端還可以耦接反及閘的第一輸入端,而反及閘的第二輸入端和輸出端則可以分別耦接一反及閘訊號和功率開關,以決定功率開關的狀態。From another point of view, the present invention further provides a control circuit for another power switch, including an inverter, a capacitor, a high voltage selection circuit, an electrostatic protection switch, and an anti-gate. The input of the inverter can be grounded through the capacitor and receive the output of the high voltage selection circuit. In addition, the inverter has a high voltage terminal and a low voltage terminal, wherein the high voltage terminal is coupled to the signal pad, and the low voltage terminal is coupled to a low voltage signal. Thereby, the inverter can output a reverse signal to the static electricity protection switch according to the state of the input end, and can cause the static electricity protection switch to determine whether to ground the signal welding pad according to the direction signal. In addition, the input end of the inverter can also be coupled to the first input end of the anti-gate, and the second input end and the output end of the anti-gate can be respectively coupled with a gate signal and a power switch to determine the power. The state of the switch.
在本發明之一實施例中,高電壓選擇電路包括第一PMOS電晶體和第二PMOS電晶體。第一PMOS電晶體的源極端耦接一高電壓源,而其閘極端則耦接訊號焊墊。另外,第二PMOS電晶體的源極端和閘極端分別耦接第一PMOS電晶體的閘極端和源極端,而第二PMOS電晶體的汲極端則與第一PMOS電晶體的汲極端共同耦接至反向器的輸入端。In an embodiment of the invention, the high voltage selection circuit includes a first PMOS transistor and a second PMOS transistor. The source terminal of the first PMOS transistor is coupled to a high voltage source, and the gate terminal thereof is coupled to the signal pad. In addition, the source terminal and the gate terminal of the second PMOS transistor are respectively coupled to the gate terminal and the source terminal of the first PMOS transistor, and the 汲 terminal of the second PMOS transistor is coupled to the 汲 terminal of the first PMOS transistor. To the input of the inverter.
由於本發明的控制電路可以內嵌在積體電路中,因此本發明可以有效地降低整體電路的體積以及硬體成本。另外,藉由功率開關的狀態改變,就可以使本發明之積體電路進行不同的動作。Since the control circuit of the present invention can be embedded in the integrated circuit, the present invention can effectively reduce the volume of the overall circuit as well as the hardware cost. In addition, the integrated circuit of the present invention can be operated differently by changing the state of the power switch.
為讓本發明之上述和其他目的、特徵和優點能更明顯易懂,下文特舉較佳實施例,並配合所附圖式,作詳細說明如下。The above and other objects, features and advantages of the present invention will become more <RTIgt;
圖2繪示為依照本發明之一較佳實施例的一種積體電路的電路方塊圖。請參照圖2,本實施例所提供的積體電路200可以是電子式可抹除可程式唯讀記憶元件,其包括一內部電路202以及多個訊號焊墊,例如204和206。內部電路202具有一電源端VDD和一功能訊號端VPP。其中,電源端VDD可以耦接其中一訊號焊墊,例如訊號焊墊204。較特別的是,功能訊號端VPP則可以透過內嵌的焊墊電路210和230而耦接至另一訊號焊墊,例如訊號焊墊206。2 is a circuit block diagram of an integrated circuit in accordance with a preferred embodiment of the present invention. Referring to FIG. 2, the integrated circuit 200 provided in this embodiment may be an electronic erasable programmable read only memory device including an internal circuit 202 and a plurality of signal pads, such as 204 and 206. The internal circuit 202 has a power terminal VDD and a function signal terminal VPP. The power terminal VDD can be coupled to one of the signal pads, such as the signal pad 204. More specifically, the function signal terminal VPP can be coupled to another signal pad, such as the signal pad 206, through the embedded pad circuits 210 and 230.
在積體電路200實際的操作上,訊號焊墊204和206在一些操作週期期間,可以被分別施加電壓源V1和V2。而這些操作週期例如是程式化週期或是讀取週期。在以下的實施例中,電壓源V2的電位可以大於電壓源V1的電位,惟本發明並不以此為限。In the actual operation of the integrated circuit 200, the signal pads 204 and 206 can be applied with voltage sources V1 and V2, respectively, during some operational cycles. These operation cycles are, for example, a stylized cycle or a read cycle. In the following embodiments, the potential of the voltage source V2 may be greater than the potential of the voltage source V1, but the invention is not limited thereto.
焊墊電路210和230二者的結構相似,都分別包括功率開關212和232、以及閘極控制電路214和234。其中,功率開關212和232,可以分別將訊號焊墊204和206耦接至功能訊號端VPP。而閘極控制電路214和234則可以分別輸出開關訊號SW1和SW2給對應的功率開關212和232,以決定二者的狀態。The pad circuits 210 and 230 are similar in structure and include power switches 212 and 232, respectively, and gate control circuits 214 and 234, respectively. The power switches 212 and 232 can respectively couple the signal pads 204 and 206 to the function signal terminal VPP. The gate control circuits 214 and 234 can respectively output the switching signals SW1 and SW2 to the corresponding power switches 212 and 232 to determine the state of both.
在本實施例中,功率開關212和232可以分別包括一功率電晶體,例如PMOS電晶體P1和P2。其中,PMOS電晶體P1的源極端和汲極端可以分別耦接訊號焊墊204和功能訊號端VPP,而PMOS電晶體P1的閘極端則可以耦接閘極控制電路214,以接收開關訊號SW1。類似地,PMOS電晶體P2的源極端和汲極端可以分別耦接訊號焊墊206和功能訊號端VPP,而其閘極端則可以耦接對應的閘極控制電路234,以接收開關訊號SW2。In this embodiment, power switches 212 and 232 may each include a power transistor, such as PMOS transistors P1 and P2. The source terminal and the drain terminal of the PMOS transistor P1 can be respectively coupled to the signal pad 204 and the function signal terminal VPP, and the gate terminal of the PMOS transistor P1 can be coupled to the gate control circuit 214 to receive the switching signal SW1. Similarly, the source and drain terminals of the PMOS transistor P2 can be coupled to the signal pad 206 and the function signal terminal VPP, respectively, and the gate terminal can be coupled to the corresponding gate control circuit 234 to receive the switching signal SW2.
在另外一些實施例中,焊墊電路210和230還可以分別配置井控制電路216和236。井控制電路216可以分別耦接功率開關212和232,並且輸出一井控制電壓HVDD和HVPP給功率開關212和232。藉此,來避免PMOS電晶體P1和P2因本體效應(Body effect)所造成驅動能力的下降。In other embodiments, pad circuits 210 and 230 can also be configured with well control circuits 216 and 236, respectively. Well control circuit 216 can be coupled to power switches 212 and 232, respectively, and outputs a well control voltage HVDD and HVPP to power switches 212 and 232. Thereby, the driving ability of the PMOS transistors P1 and P2 due to the body effect is prevented from being lowered.
以下提供幾個實施例並合併對應的圖示,來說明閘極控制電路214和234。然而本領域具有通常知識當知,以下的實施例除了可以適用於圖2的閘極控制電路之外,還可以適用於其他開關的控制電路,並且以下的敘述將不會針對此點再行贅述。Several embodiments are provided below and the corresponding diagrams are incorporated to illustrate gate control circuits 214 and 234. However, it is known in the art that the following embodiments can be applied to the control circuits of other switches in addition to the gate control circuit of FIG. 2, and the following description will not be repeated for this point. .
圖3A繪示為依照本發明第一實施例的一種閘極控制電路214的電路圖。請參照圖3A,閘極控制電路214包括反向器302、靜電放電防護開關304、電容306和反及閘308。反向器302的輸入端A1可以透過電阻310耦接至訊號焊墊204。另外,反向器302的輸入端A1還可以耦接反及閘308的第一輸入端,而反及閘308的第二輸入端和輸出端,則可以分別接收一反及閘訊號NA1,並且耦接至PMOS電晶體P1的閘極端。在本實施例中,反及閘308具有一高電壓端,其電位可以是井控制電壓HVDD的電位。FIG. 3A is a circuit diagram of a gate control circuit 214 in accordance with a first embodiment of the present invention. Referring to FIG. 3A, the gate control circuit 214 includes an inverter 302, an electrostatic discharge protection switch 304, a capacitor 306, and a reverse gate 308. The input terminal A1 of the inverter 302 can be coupled to the signal pad 204 through the resistor 310. In addition, the input terminal A1 of the inverter 302 can also be coupled to the first input end of the anti-gate 308, and the second input end and the output end of the anti-gate 308 can respectively receive a reverse gate signal NA1, and It is coupled to the gate terminal of the PMOS transistor P1. In the present embodiment, the anti-gate 308 has a high voltage terminal, and its potential can be the potential of the well control voltage HVDD.
請繼續參照圖3A,反向器302的輸出端則可以耦接靜電放電防護開關304,而靜電放電防護開關304則可以將訊號焊墊204耦接至低電壓VSS。在本實施例中,低電壓VSS的電位例如是接地電位。因此,為了使敘述能夠簡明,因此下述皆將低電壓VSS當作接地。Referring to FIG. 3A, the output of the inverter 302 can be coupled to the ESD protection switch 304, and the ESD protection switch 304 can couple the signal pad 204 to the low voltage VSS. In the present embodiment, the potential of the low voltage VSS is, for example, a ground potential. Therefore, in order to make the description concise, the low voltage VSS is assumed to be grounded as follows.
在本實施例中,反向器302可以包括NMOS電晶體N1和PMOS電晶體P3。其中,NMOS電晶體N1的源極端接地,而汲極端和閘極端則分別耦接PMOS電晶體P3的汲極端和閘極端,並且NMOS電晶體N1的閘極端還耦接至反及閘308的輸入端A1。另外,PMOS電晶體P3的源極端則可以耦接至訊號焊墊204,而其汲極端則可以與NMOS電晶體N1的汲極端透過反向器302的輸出端共同耦接至靜電放電防護開關304。In the present embodiment, the inverter 302 may include an NMOS transistor N1 and a PMOS transistor P3. Wherein, the source terminal of the NMOS transistor N1 is grounded, and the 汲 terminal and the gate terminal are respectively coupled to the 汲 terminal and the gate terminal of the PMOS transistor P3, and the gate terminal of the NMOS transistor N1 is also coupled to the input of the NAND gate 308. End A1. In addition, the source terminal of the PMOS transistor P3 can be coupled to the signal pad 204, and the drain terminal can be coupled to the ESD protection switch 304 through the output terminal of the NMOS transistor N1 through the output of the inverter 302. .
靜電放電防護開關304也可以利用NMOS電晶體N2來實現。其中,NMOS電晶體N2的源極端可以接地,汲極端可以耦接訊號焊墊204,而閘極端則可以耦接反向器302的輸出端。The ESD protection switch 304 can also be implemented using an NMOS transistor N2. The source terminal of the NMOS transistor N2 can be grounded, the drain terminal can be coupled to the signal pad 204, and the gate terminal can be coupled to the output of the inverter 302.
圖3B則繪示為依照本發明第一實施例的一種閘極控制電路234的電路圖。請參照圖3B,閘極控制電路234的電路結構與閘極控制電路214的電路結構雷同,也包括反向器322、靜電放電防護開關324、電容326和反及閘328。同樣地,反向器322的輸入端A2可以透過電阻330和高電壓選擇電路耦接至高電位,並且可以耦接至反及閘328的第一輸入端。其中,反及閘328的第二輸入端則可以接收反及閘訊號NA2,而其輸出端則可以耦接PMOS電晶體P2的閘極端。另外,反及閘328也具有一高電壓端, 而其電位可以是井控制電壓HVPP的電位。然而,在本實施例中,其電位卻不需要那麼高,原因在之後會有詳細的說明。FIG. 3B is a circuit diagram of a gate control circuit 234 in accordance with a first embodiment of the present invention. Referring to FIG. 3B, the circuit structure of the gate control circuit 234 is identical to that of the gate control circuit 214, and includes an inverter 322, an electrostatic discharge protection switch 324, a capacitor 326, and an inverse gate 328. Similarly, the input terminal A2 of the inverter 322 can be coupled to the high potential through the resistor 330 and the high voltage selection circuit, and can be coupled to the first input terminal of the NAND gate 328. The second input end of the anti-gate 328 can receive the anti-gate signal NA2, and the output end can be coupled to the gate end of the PMOS transistor P2. In addition, the anti-gate 328 also has a high voltage end. The potential can be the potential of the well control voltage HVPP. However, in the present embodiment, the potential is not required to be so high, and the reason will be described in detail later.
同樣地,反向器322也可以包括PMOS電晶體P4和NMOS電晶體N3。NMOS電晶體N3的源極端也可以接地,而汲極端和閘極端則可以分別耦接PMOS電晶體P4的汲極端和閘極端。另外,PMOS電晶體P4的閘極端和汲極端可以分別耦接反向器322的輸入端A2和輸出端,而PMOS電晶體P4的源極端則可以耦接訊號焊墊206。Similarly, the inverter 322 may also include a PMOS transistor P4 and an NMOS transistor N3. The source terminal of the NMOS transistor N3 can also be grounded, and the 汲 terminal and the gate terminal can be coupled to the 汲 terminal and the gate terminal of the PMOS transistor P4, respectively. In addition, the gate terminal and the drain terminal of the PMOS transistor P4 can be respectively coupled to the input terminal A2 and the output terminal of the inverter 322, and the source terminal of the PMOS transistor P4 can be coupled to the signal pad 206.
另外,靜電放電防護開關324也可以利用NMOS電晶體N4來實現。同樣地,NMOS電晶體N4的源極端可以接地,閘極端可以耦接反向器322的輸出端,而汲極端則可以耦接訊號焊墊206。In addition, the ESD protection switch 324 can also be implemented using the NMOS transistor N4. Similarly, the source terminal of the NMOS transistor N4 can be grounded, the gate terminal can be coupled to the output of the inverter 322, and the drain terminal can be coupled to the signal pad 206.
特別的是,在閘極控制電路234中還包括高電壓選擇電路333,其可以透過電阻330而耦接至反向器322的輸入端A2,並且可以耦接至反及閘328的高電壓端。In particular, the gate control circuit 234 further includes a high voltage selection circuit 333 that can be coupled to the input terminal A2 of the inverter 322 through the resistor 330 and can be coupled to the high voltage terminal of the inverse gate 328. .
圖4繪示為依照本發明之一較佳實施例的一種高電壓選擇電路的電路圖。請參照圖4,高電壓選擇電路333包括PMOS電晶體P5和P6。PMOS電晶體P5和P6的的源極端可以分別耦接電壓源V3和訊號焊墊206。而每一PMOS電晶體的汲極端除了與本身的N型井耦接之外,亦再與另一PMOS電晶體的汲極端共接,以構成依內部電源輸出端Vx。另外,每一PMOS電晶體的閘極端則交叉地耦接至彼此的源極端。利用PMOS電晶體P5和P6的切換,就可以在電壓源V3和訊號焊墊206中,選出一較高電壓者作為內部電源輸出端Vx的輸出電壓。而在本實施例中,輸入端訊號Vx也可以被送至反及閘328的高電壓端。4 is a circuit diagram of a high voltage selection circuit in accordance with a preferred embodiment of the present invention. Referring to FIG. 4, the high voltage selection circuit 333 includes PMOS transistors P5 and P6. The source terminals of the PMOS transistors P5 and P6 can be coupled to the voltage source V3 and the signal pad 206, respectively. The 汲 terminal of each PMOS transistor is coupled to the NMOS terminal of the other PMOS transistor in addition to being coupled to its own N-type well to form an internal power supply output terminal Vx. Additionally, the gate terminals of each PMOS transistor are cross-coupled to the source terminals of each other. By switching between the PMOS transistors P5 and P6, a higher voltage can be selected as the output voltage of the internal power supply output terminal Vx in the voltage source V3 and the signal pad 206. In this embodiment, the input signal Vx can also be sent to the high voltage end of the NAND gate 328.
圖5繪示為依照本發明第一實施例的一種閘極控制電路內部之訊號的狀況表。請合併參照圖2、3A、3B和5,當需要積體電路200進行寫入的動作時,可以分別使反及閘訊號NA1和NA2為低電位(L)和高電位(H)。此時,反及閘308會因為其中一輸入端的電位為L的緣故,而輸出狀態為H的開關訊號SW1給PMOS電晶體P1,導致PMOS電晶體P1關閉。FIG. 5 is a table showing the status of signals inside a gate control circuit according to the first embodiment of the present invention. Referring to FIGS. 2, 3A, 3B and 5 in combination, when the integrated circuit 200 is required to perform the writing operation, the inverse gate signals NA1 and NA2 can be made low (L) and high (H), respectively. At this time, the reverse gate 308 will output the switching signal SW1 of the state H to the PMOS transistor P1 because the potential of one of the input terminals is L, causing the PMOS transistor P1 to be turned off.
請合併參照圖4,另一方面,在閘極控制電路234中,由於訊號焊墊206被施加電壓源V2,而電壓源V2的電位又可以大於電壓源V3的電位,導致PMOS電晶體P5關閉,而PMOS電晶體P6則被導通。此時,輸入端訊號Vx的電位就是電壓源V2的電位。換句話說,反向器322的輸入端A2的電位就是H。因此,反及閘328在輸入端都為H的狀態下,會輸出狀態為L的開關訊號SW2給PMOS電晶體P2,而使其導通。此外,由於反向器322的輸入端A2的電位為V2,因此就會輸出狀態為L的反向訊號INV2給NMOS電晶體N4,而使得NMOS電晶體N4關閉。藉此,就可以將電壓源V2的電位經由PMOS電晶體P2送至功能訊號端VPP,而使積體電路進行程式化的動作。Referring to FIG. 4 in combination, on the other hand, in the gate control circuit 234, since the signal pad 206 is applied with the voltage source V2, the potential of the voltage source V2 can be greater than the potential of the voltage source V3, causing the PMOS transistor P5 to be turned off. And the PMOS transistor P6 is turned on. At this time, the potential of the input terminal signal Vx is the potential of the voltage source V2. In other words, the potential of the input terminal A2 of the inverter 322 is H. Therefore, in the state where the input terminal is H, the reverse gate 328 outputs the switching signal SW2 of the state L to the PMOS transistor P2 to be turned on. Further, since the potential of the input terminal A2 of the inverter 322 is V2, the reverse signal INV2 of the state L is output to the NMOS transistor N4, and the NMOS transistor N4 is turned off. Thereby, the potential of the voltage source V2 can be sent to the function signal terminal VPP via the PMOS transistor P2, and the integrated circuit can be programmed.
相對地,若是積體電路200進入讀取週期時,則可以分別使反及閘訊號NA1和NA2為H和L。此時,閘極控制電路234中的反及閘328會因為其中一輸入端的狀態為L,而輸出狀態為H的開關訊號SW2給PMOS電晶體P2,而使其關閉。相對地,在閘極控制電路214中的反及閘308,會由於其第一輸入端為電壓源V1的電位,而第二輸入端的電位也為H,而輸出狀態為L的開關訊號SW1給PMOS電晶體P1。另外,由於反向器302的輸入端A1為V1,因此就可以輸出狀態為L的反向訊號INV1給NMOS電晶體N2,而使得NMOS電晶體N2關閉。藉此,就可以將電壓源V1的電位經由PMOS電晶體P1送至功能訊號端VPP,以使積體電路200進行讀取操作。In contrast, if the integrated circuit 200 enters the read cycle, the inverse gate signals NA1 and NA2 can be made H and L, respectively. At this time, the reverse gate 328 in the gate control circuit 234 will turn off the switching signal SW2 of the state H to the PMOS transistor P2 because the state of one of the input terminals is L. In contrast, the gate 308 in the gate control circuit 214 may have a potential of the voltage source V1 at its first input terminal, and a potential of the second input terminal is also H, and the switching signal SW1 of the output state is L. PMOS transistor P1. In addition, since the input terminal A1 of the inverter 302 is V1, the reverse signal INV1 of the state L can be output to the NMOS transistor N2, and the NMOS transistor N2 can be turned off. Thereby, the potential of the voltage source V1 can be sent to the function signal terminal VPP via the PMOS transistor P1 to cause the integrated circuit 200 to perform a read operation.
另一方面,若是訊號焊墊204有靜電放電的情況發生時,反向器302的輸入端A1會因為電容306無法瞬間改變狀態的特性,而將輸入端A1耦接至低電壓VSS。此時,反及閘308也會因為其中一輸入端A1的電位為L,因此輸出狀態為H的開關訊號SW1給PMOS電晶體P1,而使其關閉。另外,由於反向器302的輸入端A1的電位為VSS,因此就可以輸出狀態為H的反向訊號INV1給NMOS電晶體N2,並使其導通。藉此,靜電放電的電流不會送到內部電路202,而是可以循NMOS電晶體N2所導通的路徑進行放電。On the other hand, if the electrostatic discharge of the signal pad 204 occurs, the input terminal A1 of the inverter 302 couples the input terminal A1 to the low voltage VSS because the capacitor 306 cannot instantaneously change the state of the state. At this time, the gate 308 is also turned on because the potential of one of the input terminals A1 is L, so that the switching signal SW1 of the output state H is supplied to the PMOS transistor P1. Further, since the potential of the input terminal A1 of the inverter 302 is VSS, the reverse signal INV1 of the state H can be output to the NMOS transistor N2 and turned on. Thereby, the current of the electrostatic discharge is not sent to the internal circuit 202, but can be discharged in accordance with the path through which the NMOS transistor N2 is turned on.
類似地,若是訊號焊墊206發生靜電放電的情形時,高電壓選擇電路333所輸出的輸入端訊號Vx電位會在短時間內被強制拉升到非常高的電位。此時,由於電容326兩端的電位無法在短時間改變,因此電容326會將低電壓VSS耦合至反向器322的輸入端A2。此時,反及閘328會因為其中一輸入端的電位為L,因此會輸出狀態為H的開關訊號SW2,以將PMOS電晶體P2關閉。另外,反向器322會輸出狀態為H的反向訊號INV2給NMOS電晶體N4,以將其導通。藉此,靜電放電的電流就會被功率開關232阻隔,並且循NMOS電晶體N4所導通的路徑進行放電,而避免流入內部電路202而造成積體電路200的損壞。Similarly, if the signal pad 206 is electrostatically discharged, the input signal Vx output from the high voltage selection circuit 333 is forcibly pulled up to a very high potential in a short time. At this time, since the potential across the capacitor 326 cannot be changed in a short time, the capacitor 326 couples the low voltage VSS to the input terminal A2 of the inverter 322. At this time, the NAND gate 328 will output a switching signal SW2 of the state H to turn off the PMOS transistor P2 because the potential of one of the input terminals is L. In addition, the inverter 322 outputs a reverse signal INV2 of state H to the NMOS transistor N4 to turn it on. Thereby, the current of the electrostatic discharge is blocked by the power switch 232, and is discharged according to the path in which the NMOS transistor N4 is turned on, thereby avoiding the inflow of the internal circuit 202 and causing damage to the integrated circuit 200.
圖6A繪示為依照本發明第二實施例的閘極控制電路214的電路圖。請參照圖6A,在本實施例中,閘極控制電路214更包括一反向器602,其輸入端接收一操作訊號ZENVDD,並依據此操作訊號ZENVDD而產生反及閘訊號NA1給反及閘308。此外,反向器602還具有一高電壓端,其耦接訊號焊墊204,以便接收電壓訊號V1。FIG. 6A is a circuit diagram of a gate control circuit 214 in accordance with a second embodiment of the present invention. Referring to FIG. 6A, in the embodiment, the gate control circuit 214 further includes an inverter 602. The input terminal receives an operation signal ZENVDD, and generates an anti-gate signal NA1 according to the operation signal ZENVDD. 308. In addition, the inverter 602 has a high voltage terminal coupled to the signal pad 204 for receiving the voltage signal V1.
圖6B繪示為依照本發明第二實施例的閘極控制電路234的電路圖。請參照圖6B,同樣地,在閘極控制電路234中,也可以配置有反向器612,其輸入端耦接一操作訊號ZENVPP,以輸出反及閘訊號NA2給反及閘328。反向器612也具有一高電壓端,其可以耦接高電壓選擇電路333所輸出的輸入端訊號Vx。FIG. 6B is a circuit diagram of a gate control circuit 234 in accordance with a second embodiment of the present invention. Referring to FIG. 6B, similarly, in the gate control circuit 234, an inverter 612 may be disposed, and an input terminal is coupled to an operation signal ZENVPP to output a reverse gate signal NA2 to the inverse gate 328. The inverter 612 also has a high voltage terminal, which can be coupled to the input signal Vx output by the high voltage selection circuit 333.
在一些選擇實施例中,閘極控制電路234還可以包括緩衝器614,其輸入端耦接反及閘328的輸出,而緩衝器614的輸出端則可以耦接PMOS電晶體P2的閘極端。藉此,反及閘328所產生的開關訊號SW2就可以通過緩衝器614而被傳送至PMOS電晶體P2。同樣地,緩衝器614也具有一高電壓端,其同樣可以耦接高電壓選擇電路333所輸出的輸入端訊號Vx。In some alternative embodiments, the gate control circuit 234 may further include a buffer 614 having an input coupled to the output of the NAND gate 328, and the output of the buffer 614 may be coupled to the gate terminal of the PMOS transistor P2. Thereby, the switching signal SW2 generated by the gate 328 can be transmitted to the PMOS transistor P2 through the buffer 614. Similarly, the buffer 614 also has a high voltage terminal, which can also be coupled to the input signal Vx output by the high voltage selection circuit 333.
圖7A繪示為依照本發明第三實施例的閘極控制電路214的電路圖。請參照圖7A,在本實施例中,閘極控制電路214還可以包括反及閘702和NMOS電晶體N5。其中,反及閘702的第一輸入端可以耦接操作訊號ZENVDD,第二輸入端可以耦接反向器302的輸入端A1,而輸出端則可以耦接NMOS電晶體N5的閘極端。另外,NMOS電晶體N5的源極端和汲極端則可以分別耦接PMOS電晶體P1的源極端和汲極端。FIG. 7A is a circuit diagram of a gate control circuit 214 in accordance with a third embodiment of the present invention. Referring to FIG. 7A, in the embodiment, the gate control circuit 214 may further include an anti-gate 702 and an NMOS transistor N5. The first input end of the anti-gate 702 can be coupled to the operation signal ZENVDD, the second input end can be coupled to the input end A1 of the inverter 302, and the output end can be coupled to the gate end of the NMOS transistor N5. In addition, the source terminal and the NMOS terminal of the NMOS transistor N5 may be coupled to the source terminal and the NMOS terminal of the PMOS transistor P1, respectively.
圖8繪示為依照本發明第二和第三實施例的一種閘極控制電路內部之訊號的狀況表。請合併參照圖7A和圖8,在寫入週期期間,操作訊號ZENVDD可以為H,因此反及閘訊號NA1就可以為L。另外,由於在寫入週期期間,反向器302的輸入端A1電位也為H,因此反及閘702的輸出就是L,導致NMOS電晶體N5關閉。8 is a table showing the status of signals inside a gate control circuit in accordance with the second and third embodiments of the present invention. Referring to FIG. 7A and FIG. 8 together, during the writing period, the operation signal ZENVDD may be H, so the gate signal NA1 may be L. In addition, since the potential of the input terminal A1 of the inverter 302 is also H during the writing period, the output of the inverse gate 702 is L, causing the NMOS transistor N5 to be turned off.
相對地,在讀取週期期間,控制訊號ZENVDD為L,就使得反閘極訊號NA1為H。此外,反及閘702會因為其中一輸入端為L,而將狀態為H送至NMOS電晶體N5的閘極端,使得NMOS電晶體N5導通。In contrast, during the read cycle, the control signal ZENVDD is L, so that the reverse gate signal NA1 is H. In addition, the NAND gate 702 will send a state H to the gate terminal of the NMOS transistor N5 because one of the input terminals is L, so that the NMOS transistor N5 is turned on.
圖7B繪示為依照本發明第三實施例的閘極控制電路234的電路圖。請參照圖7B,在本實施例中,閘極控制電路234同樣可以具有反及閘712和NMOS電晶體N6,而二者的耦接關係和動作原理,本領域具有通常知識者可以自行參照上述反及閘702和NMOS電晶體N5的敘述,在此不再多作贅述。FIG. 7B is a circuit diagram of a gate control circuit 234 in accordance with a third embodiment of the present invention. Referring to FIG. 7B, in the embodiment, the gate control circuit 234 can also have a reverse gate 712 and an NMOS transistor N6, and the coupling relationship and operation principle of the two can be referred to by those skilled in the art. The description of the gate 702 and the NMOS transistor N5 will not be repeated here.
請回頭參照圖2、圖4和圖5,閘極控制電路234在讀取週期時,會輸出狀態為H的開關訊號SW2,以關閉PMOS電晶體P2。此時,訊號焊墊206上並不一定要施加V2電壓。在一些實施例中,在讀取週期期間,訊號焊墊206的電位可以是V1、VSS或甚至浮接。然而,若是發生訊號焊墊206上的電位V2與電壓源V3電位同步上升至等電位時,高電壓選擇電路333的輸出端Vx的電位會等於電壓源V2的電位再減去二極體的電壓降。Referring back to FIG. 2, FIG. 4 and FIG. 5, the gate control circuit 234 outputs a switching signal SW2 of state H during the read cycle to turn off the PMOS transistor P2. At this time, it is not necessary to apply a V2 voltage on the signal pad 206. In some embodiments, the potential of the signal pad 206 may be V1, VSS, or even floating during the read cycle. However, if the potential V2 on the signal pad 206 rises to the equipotential in synchronization with the potential of the voltage source V3, the potential of the output terminal Vx of the high voltage selection circuit 333 is equal to the potential of the voltage source V2 minus the voltage of the diode. drop.
圖9A繪示為依照本發明第四實施例的閘極控制電路234的電路圖。請參照圖9A,為了因應上述的情形,在本實施例中,閘極控制電路234還可以配置一二極體902,其陽極端可以耦接訊號焊墊206,而陰極端則可以耦接PMOS電晶體P4的源極端。而藉由二極體902的壓降,就可以補償上述因為訊號焊墊206之電位V2與電壓源V3之同步上升至等電位時,而導致輸入端訊號Vx僅為電壓源V2的電位再減去二極體的電壓降的情形。FIG. 9A is a circuit diagram of a gate control circuit 234 in accordance with a fourth embodiment of the present invention. Referring to FIG. 9A, in order to meet the above situation, in the embodiment, the gate control circuit 234 can also be configured with a diode 902, the anode end of which can be coupled to the signal pad 206, and the cathode end can be coupled to the PMOS. The source terminal of the transistor P4. By the voltage drop of the diode 902, the potential V2 of the signal pad 206 and the voltage source V3 rise to the equipotential level, and the input signal Vx is only the potential of the voltage source V2. The case of the voltage drop of the diode.
圖9B和圖9C所揭示的閘極控制電路,用以也是與圖9A相同,不同的是利用PMOS電晶體P7和P8來取代二極體802。在圖9B中,PMOS電晶體P7的源極端可以耦接訊號焊墊206,而閘極端和汲極端則可以分別耦接PMOS電晶體P4的閘極端和源極端。另外,在圖9C中,PMOS電晶體P8的源極端同樣也可以耦接至訊號焊墊206,而閘極端和汲極端則可以共同耦接至PMOS電晶體P4的源極端。The gate control circuit disclosed in FIGS. 9B and 9C is also the same as FIG. 9A except that the PMOS transistors P7 and P8 are used in place of the diode 802. In FIG. 9B, the source terminal of the PMOS transistor P7 can be coupled to the signal pad 206, and the gate terminal and the drain terminal can be coupled to the gate terminal and the source terminal of the PMOS transistor P4, respectively. In addition, in FIG. 9C, the source terminal of the PMOS transistor P8 can also be coupled to the signal pad 206, and the gate terminal and the drain terminal can be coupled to the source terminal of the PMOS transistor P4.
圖10A繪示為依照本發明之一較佳實施例的一種井控制電路216的電路圖。請參照圖10A,井控制電路216包括PMOS電晶體P9和P10。其中,PMOS電晶體P9和P10的源極端分別耦接至訊號焊墊204的電壓V1與電壓端點VDDIN,而二者的及極端除與本身的N型井共接外,亦與另一PMOS電晶體的汲極端共接,以形成井控制電壓HVDD給PMOS電晶體P1的井端,以避免PMOS電晶體因本體效應所造成驅動能力的下降。FIG. 10A is a circuit diagram of a well control circuit 216 in accordance with a preferred embodiment of the present invention. Referring to FIG. 10A, the well control circuit 216 includes PMOS transistors P9 and P10. The source terminals of the PMOS transistors P9 and P10 are respectively coupled to the voltage V1 of the signal pad 204 and the voltage terminal VDDIN, and the sum of the two is connected with the N-well of the circuit, and the other PMOS. The germanium terminals of the transistor are connected in common to form a well control voltage HVDD to the well end of the PMOS transistor P1 to avoid a decrease in driving capability of the PMOS transistor due to the bulk effect.
在本實施例中,井控制電壓HVDD更可以閘極控制電路214中之反及閘308的高電壓端,使PMOS電晶體P1可以正常運作。In the present embodiment, the well control voltage HVDD can be further turned to the high voltage terminal of the gate 308 in the gate control circuit 214 to enable the PMOS transistor P1 to operate normally.
圖10B繪示為依照本發明之一較佳實施例的一種井控制電路236的電路圖。請參照圖10B,與井控制電路216相同,井控制電路236也包括PMOS電晶體P11和P12。PMOS電晶體P11和P12的源極端分別耦接至訊號焊墊206的電壓V2,以及電壓端點VPPIN2,而二者的汲極端除了與本身的N型井端共接外,亦與另一PMOS電晶體的汲極端共接,以輸出井控制電壓HVPP給PMOS電晶體P2,以避免PMOS電晶體因為本體效應所造成驅動能力的下降。FIG. 10B is a circuit diagram of a well control circuit 236 in accordance with a preferred embodiment of the present invention. Referring to FIG. 10B, like well control circuit 216, well control circuit 236 also includes PMOS transistors P11 and P12. The source terminals of the PMOS transistors P11 and P12 are respectively coupled to the voltage V2 of the signal pad 206 and the voltage terminal VPPIN2, and the 汲 terminals of the PMOS transistors are connected to the N-type well terminal and the other PMOS battery. The germanium terminal of the crystal is connected in common to output the well control voltage HVPP to the PMOS transistor P2 to avoid the driving capability of the PMOS transistor due to the bulk effect.
在一些實施例中,此井控制電壓HVPP也可以送至閘極控制電路234中之反及閘328和反向器612的高電壓端。然而,由於閘極控制電路234僅在寫入週期期間,才會使PMOS電晶體P2導通。因此,在一些選擇實施例中,反及閘328和反向器612的高電壓端不需耦接井控制電壓HVPP,而可以耦接輸入端訊號Vx。In some embodiments, the well control voltage HVPP can also be sent to the high voltage terminals of the gate control circuit 234 and the gate 328 and the inverter 612. However, since the gate control circuit 234 is only turned on during the write period, the PMOS transistor P2 is turned on. Therefore, in some alternative embodiments, the high voltage terminals of the anti-gate 328 and the inverter 612 need not be coupled to the well control voltage HVPP, but may be coupled to the input signal Vx.
綜上所述,由於本發明之閘極控制電路可以內嵌在積體電路中,因此本發明所提供的積體電路會具有較小的體積。另外,由於本發明在靜電放電發生後,會使功率開關關閉,而使靜電放電防護開關導通,因此本發明也可以充分地保護積體電路之內部電路不受靜電放電的損傷。In summary, since the gate control circuit of the present invention can be embedded in the integrated circuit, the integrated circuit provided by the present invention can have a small volume. Further, since the present invention turns off the power switch after the occurrence of the electrostatic discharge, and the electrostatic discharge protection switch is turned on, the present invention can sufficiently protect the internal circuit of the integrated circuit from the electrostatic discharge.
雖然本發明已以較佳實施例揭露如上,然其並非用以限定本發明,任何熟習此技藝者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.
100...選擇電路100. . . Selection circuit
110...高電壓追蹤模組110. . . High voltage tracking module
112...高壓選擇模組112. . . High voltage selection module
114、116...井偏壓模組114, 116. . . Well bias module
120...位準偏移模組120. . . Level offset module
122、124...位準偏移器122, 124. . . Level shifter
130...開關模組130. . . Switch module
132、134、P1、P2、P3、P4、P5、P6、P7、P8、P9、P10、P11、P12...PMOS電晶體132, 134, P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12. . . PMOS transistor
200...積體電路200. . . Integrated circuit
202...內部電路202. . . Internal circuit
204、206...訊號焊墊204, 206. . . Signal pad
210、230...焊墊電路210, 230. . . Pad circuit
212、232...功率開關212, 232. . . Power switch
214、234...閘極控制電路214, 234. . . Gate control circuit
302、322、602、612...反向器302, 322, 602, 612. . . Inverter
304、324...靜電放電防護開關304, 324. . . Electrostatic discharge protection switch
306、326...電容306, 326. . . capacitance
308、328、702、712...反及閘308, 328, 702, 712. . . Reverse gate
310、330...電阻310, 330. . . resistance
333...高電壓選擇電路333. . . High voltage selection circuit
614...緩衝器614. . . buffer
902...二極體902. . . Dipole
A1、A2...反向器的輸入端A1, A2. . . Inverter input
INV1、INV2...反向訊號INV1, INV2. . . Reverse signal
N1、N2、N3、N4、N5、N6...NMOS電晶體N1, N2, N3, N4, N5, N6. . . NMOS transistor
NA1、NA2...反及閘訊號NA1, NA2. . . Anti-gate signal
SW1、SW2...開關訊號SW1, SW2. . . Switch signal
V1、V2、V3、VD1、VP1...電壓源V1, V2, V3, VD1, VP1. . . power source
VDD...電源端VDD. . . Power terminal
VPP...功能訊號端VPP. . . Functional signal end
VPPI、HVDD、HVPP、HVDD、VPPIN1、VPPIN2、VDDIN、ENVDD、ENVPP...控制電壓VPPI, HVDD, HVPP, HVDD, VPPIN1, VPPIN2, VDDIN, ENVDD, ENVPP. . . Control voltage
VSS...低電壓VSS. . . low voltage
Vx...輸入端訊號Vx. . . Input signal
ZENVDD、ZENVPP...操作訊號ZENVDD, ZENVPP. . . Operation signal
圖1繪示為習知之電源供應器之選擇電路的電路圖。1 is a circuit diagram of a selection circuit of a conventional power supply.
圖2繪示為依照本發明之一較佳實施例的一種積體電路的電路方塊圖。2 is a circuit block diagram of an integrated circuit in accordance with a preferred embodiment of the present invention.
圖3A和3B分別繪示為依照本發明第一實施例的閘極控制電路的電路圖。3A and 3B are circuit diagrams respectively showing a gate control circuit in accordance with a first embodiment of the present invention.
圖4繪示為依照本發明之一較佳實施例的一種高電壓選擇電路的電路圖。4 is a circuit diagram of a high voltage selection circuit in accordance with a preferred embodiment of the present invention.
圖5繪示為依照本發明第一實施例的一種閘極控制電路內部之訊號的狀況表。FIG. 5 is a table showing the status of signals inside a gate control circuit according to the first embodiment of the present invention.
圖6A和6B分別繪示為依照本發明第二實施例的閘極控制電路的電路圖。6A and 6B are circuit diagrams respectively showing a gate control circuit in accordance with a second embodiment of the present invention.
圖7A和7B分別繪示為依照本發明第三實施例的閘極控制電路的電路圖。。7A and 7B are circuit diagrams respectively showing a gate control circuit in accordance with a third embodiment of the present invention. .
圖8繪示為依照本發明第二和第三實施例的一種閘極控制電路內部之訊號的狀況表。8 is a table showing the status of signals inside a gate control circuit in accordance with the second and third embodiments of the present invention.
圖9A、9B和9C分別繪示為依照本發明第四實施例的閘極控制電路的電路圖。9A, 9B and 9C are circuit diagrams respectively showing a gate control circuit in accordance with a fourth embodiment of the present invention.
圖10A和圖10B繪示為依照本發明之一較佳實施例的一種井控制電路的電路圖。10A and 10B are circuit diagrams of a well control circuit in accordance with a preferred embodiment of the present invention.
200...積體電路200. . . Integrated circuit
202...內部電路202. . . Internal circuit
204、206...訊號焊墊204, 206. . . Signal pad
210、230...焊墊電路210, 230. . . Pad circuit
212、232...功率開關212, 232. . . Power switch
214、234...閘極控制電路214, 234. . . Gate control circuit
HVDD、HVPP...井控制電壓HVDD, HVPP. . . Well control voltage
P1、P2...PMOS電晶體P1, P2. . . PMOS transistor
SW1、SW2...開關訊號SW1, SW2. . . Switch signal
V1、V2...電壓源V1, V2. . . power source
VDD...電源端VDD. . . Power terminal
VPP...功能訊號端VPP. . . Functional signal end
VPPIN2、VDDIN...控制電壓VPPIN2, VDDIN. . . Control voltage
Claims (13)
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US20070291569A1 (en) * | 2006-06-16 | 2007-12-20 | Hsiang-An Hsieh | Non-volatile storage apparatus and a control method thereof |
US20080055991A1 (en) * | 2006-08-29 | 2008-03-06 | Jin-Kook Kim | Voltage generator circuit capable of generating different voltages based on operating mode of non-volatile semiconductor memory device |
US20080144420A1 (en) * | 2006-12-15 | 2008-06-19 | Sung Soo Xi | Voltage control circuit, a voltage control method and a semiconductor memory device having the voltage control circuit |
US20080159017A1 (en) * | 2006-12-28 | 2008-07-03 | Samsung Electronics Co., Ltd. | Bias voltage generator and method generating bias voltage for semiconductor memory device |
US20090059690A1 (en) * | 2007-08-30 | 2009-03-05 | John Reginald Rilev | Methods and apparatuses for operating memory |
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US20070291569A1 (en) * | 2006-06-16 | 2007-12-20 | Hsiang-An Hsieh | Non-volatile storage apparatus and a control method thereof |
US20080055991A1 (en) * | 2006-08-29 | 2008-03-06 | Jin-Kook Kim | Voltage generator circuit capable of generating different voltages based on operating mode of non-volatile semiconductor memory device |
US20080144420A1 (en) * | 2006-12-15 | 2008-06-19 | Sung Soo Xi | Voltage control circuit, a voltage control method and a semiconductor memory device having the voltage control circuit |
US20080159017A1 (en) * | 2006-12-28 | 2008-07-03 | Samsung Electronics Co., Ltd. | Bias voltage generator and method generating bias voltage for semiconductor memory device |
US20090059690A1 (en) * | 2007-08-30 | 2009-03-05 | John Reginald Rilev | Methods and apparatuses for operating memory |
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