TWI384485B - Circuit for checking memeory status in advance - Google Patents

Circuit for checking memeory status in advance Download PDF

Info

Publication number
TWI384485B
TWI384485B TW97134892A TW97134892A TWI384485B TW I384485 B TWI384485 B TW I384485B TW 97134892 A TW97134892 A TW 97134892A TW 97134892 A TW97134892 A TW 97134892A TW I384485 B TWI384485 B TW I384485B
Authority
TW
Taiwan
Prior art keywords
memory
pin
configuration
logic circuit
electrically connected
Prior art date
Application number
TW97134892A
Other languages
Chinese (zh)
Other versions
TW201011766A (en
Inventor
Chihcheng Wei
Hsianghsin Kung
Original Assignee
Inventec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Inventec Corp filed Critical Inventec Corp
Priority to TW97134892A priority Critical patent/TWI384485B/en
Publication of TW201011766A publication Critical patent/TW201011766A/en
Application granted granted Critical
Publication of TWI384485B publication Critical patent/TWI384485B/en

Links

Description

記憶體組態提前檢查電路Memory configuration check circuit in advance

本發明是有關於一種記憶體組態檢查電路,且特別是有關於一種在開機之前檢查記憶體組態的記憶體組態提前檢查電路。The present invention relates to a memory configuration check circuit, and more particularly to a memory configuration advance check circuit for checking a memory configuration prior to power on.

於電腦系統中,當使用者啟動電源按紐時,電腦系統首先會進行初始化,執行開機自我測試(power on self test;POST)過程。開機自我測試過程乃執行基本輸入/輸出系統中之一連串指令,以對於電腦系統中之各種硬體裝置進行初始化,並偵測個別硬體之狀態與設定,例如記憶體、硬碟、顯示卡、或周邊裝置如鍵盤、滑鼠等硬體。In the computer system, when the user activates the power button, the computer system first initializes and performs a power on self test (POST) process. The boot self-test process performs a series of commands in the basic input/output system to initialize various hardware devices in the computer system and detect the status and settings of individual hardware, such as memory, hard disk, display card, Or peripheral devices such as keyboards, mice and other hardware.

當電腦系統完成開機自我測試過程後,便執行中斷處理函數,以將作業系統載入至記憶體,並將控制權交予作業系統,使用者便可於此作業系統上執行一般經常使用之應用程式。電腦系統執行此一開機自我測試程序一般需耗時7至9秒鐘之時間。After the computer system completes the boot self-test process, the interrupt processing function is executed to load the operating system into the memory, and the control is given to the operating system, and the user can execute the commonly used application on the operating system. Program. It takes 7 to 9 seconds for the computer system to perform this boot self-test procedure.

由於一般電腦的記憶體組態檢查,多是在系統開機之後的開機自我測試階段中進行,如檢查出記憶體組態有誤,則再發出警告聲提醒使用者系統發現記憶體組態有誤。使用者需將系統關機,重新安排記憶體的組態位置,並再次開機進行檢測,持完成檢測後,才可正常地 使用電腦。Because the memory configuration check of the general computer is mostly carried out during the boot self-test phase after the system is turned on. If the memory configuration is checked incorrectly, a warning sound is issued to remind the user that the memory configuration is incorrect. . The user needs to shut down the system, re-arrange the configuration position of the memory, and turn it on again for detection. After the test is completed, it can be normally use computer.

因此本發明的目的就是在提供一種記憶體組態提前檢查電路,用以系統開機前檢查當前的記憶體組態是否與建議的記憶體組態相符。It is therefore an object of the present invention to provide a memory configuration advance check circuit for checking whether the current memory configuration matches the proposed memory configuration before the system is powered on.

本發明之另一目的在於提供一種記憶體組態提前檢查電路,用以顯示建議的記憶體組態,令使用者可依照燈號所顯示的建議記憶體組態,將記憶體安裝在對應的記憶體插槽中。Another object of the present invention is to provide a memory configuration advance check circuit for displaying a suggested memory configuration, so that the user can install the memory in accordance with the recommended memory configuration displayed by the light number. In the memory slot.

本發明提供一種記憶體組態提前檢查電路,包含複數個記憶體插槽、與記憶體插槽電性連接之一邏輯電路,及與邏輯電路電性連接之一發光元件。邏輯電路設定有一建議記憶體組態。安裝有記憶體之記憶體插槽可提供一低電位至邏輯電路,未安裝有記憶體之記憶體插槽則提供一高電位至邏輯電路,藉以判斷記憶體之記憶體組態是否與建議記憶體組態相同。當記憶體組態與該建議記憶體組態不同時,邏輯電路發出一警示訊號至發光元件,使發光元件作動。The invention provides a memory configuration advance check circuit, which comprises a plurality of memory slots, a logic circuit electrically connected to the memory socket, and a light-emitting element electrically connected to the logic circuit. The logic circuit settings have a suggested memory configuration. The memory slot with the memory installed provides a low-potential to logic circuit. The memory slot without the memory is provided to provide a high-potential to logic circuit to determine whether the memory configuration of the memory is related to the suggested memory. The body configuration is the same. When the memory configuration is different from the recommended memory configuration, the logic circuit sends a warning signal to the light-emitting element to activate the light-emitting element.

其中每一記憶體具有一第一接地腳與一第二接地腳,第一接地腳與第二接地腳為相互導通。每一記憶體插槽具有對應於第一接地腳之一第一腳位與對應於第二接地腳之一第二腳位,第一腳位係連接向一電源電壓端,第二腳位係連接向一接地端。其中插入記憶體之記 憶體插槽之第一腳位,可經由記憶體而與第二腳位導通,以提供低電位給邏輯電路。記憶體組態提前檢查電路中更包含一基板管理控制器(baseboard management controller;BMC),與邏輯電路電性連接,當邏輯電路判斷記憶體組態正確後,邏輯電路發出一開機許可訊號至基板管理控制器。Each of the memories has a first grounding leg and a second grounding leg, and the first grounding leg and the second grounding leg are electrically connected to each other. Each memory slot has a first pin corresponding to one of the first ground pins and a second pin corresponding to one of the second ground pins, the first pin is connected to a power voltage terminal, and the second pin system is Connect to a ground. Inserting memory The first pin of the memory slot can be electrically connected to the second pin via the memory to provide a low potential to the logic circuit. The memory configuration early check circuit further includes a baseboard management controller (BMC) electrically connected to the logic circuit. When the logic circuit determines that the memory configuration is correct, the logic circuit sends a power-on permission signal to the substrate. Manage the controller.

本發明之另一態樣為一種記憶體組態提前檢查電路,包含複數個記憶體插槽、與記憶體插槽電性連接之一微控制器,及與微控制器電性連接之複數個發光元件。微控制器設定有一建議記憶體組態。安裝有記憶體之記憶體插槽提供一低電位至微控制器,未安裝有記憶體之記憶體插槽則提供一高電位至微控制器,籍以判斷記憶體之記憶體組態是否與建議記憶體組態相同。發光元件為一對一地對應記憶體插槽,當記憶體組態與建議記憶體組態不符時,發光元件會顯示建議記憶體組態。Another aspect of the present invention is a memory configuration advance check circuit, comprising a plurality of memory slots, a microcontroller electrically connected to the memory socket, and a plurality of micro-controllers electrically connected to the microcontroller Light-emitting element. The microcontroller is configured with a recommended memory configuration. The memory slot in which the memory is mounted provides a low potential to the microcontroller, and the memory slot without the memory is provided to provide a high potential to the microcontroller to determine whether the memory configuration of the memory is It is recommended that the memory configuration be the same. The light-emitting elements correspond to the memory slots one-to-one. When the memory configuration does not match the recommended memory configuration, the light-emitting elements display the recommended memory configuration.

微控制器可包含一複雜型可程式邏輯裝置(Complex Programmable Logic Device;CPLD)。記憶體組態提前檢查電路中更包含有一基板管理控制器(baseboard management controller;BMC),與微控制器電性連接。當微控制器判斷記憶體組態正確後,微控制器發出一開機許可訊號至基板管理控制器。The microcontroller can include a Complex Programmable Logic Device (CPLD). The memory configuration early check circuit further includes a baseboard management controller (BMC) electrically connected to the microcontroller. When the microcontroller determines that the memory configuration is correct, the microcontroller issues a power-on permission signal to the baseboard management controller.

其中每一記憶體具有一第一接地腳與一第二接地腳,第一接地腳與第二接地腳為相互導通。其中每一記憶體插槽具有對應於第一接地腳之一第一腳位與對應於 第二接地腳之一第二腳位,第一腳位係連接向一電源電壓端,第二腳位係連接向一接地端。插入記憶體之記憶體插槽之第一腳位經由記憶體與第二腳位導通,以提供低電位給微控制器。Each of the memories has a first grounding leg and a second grounding leg, and the first grounding leg and the second grounding leg are electrically connected to each other. Each of the memory slots has a first pin corresponding to one of the first ground pins and corresponds to The second pin of the second grounding leg is connected to a power voltage terminal, and the second pin is connected to a ground terminal. The first pin of the memory slot inserted into the memory is electrically connected to the second pin via the memory to provide a low potential to the microcontroller.

本發明之記憶體組態提前檢查電路可在系統開機前即告知使用者記憶體組態有誤,並可透過發光元件提示使用者建議的記憶體組態,令使用者可重新調整記憶體的擺放位置到所建議的記憶體組態。The memory configuration early check circuit of the invention can inform the user that the memory configuration is wrong before the system is turned on, and can prompt the user to suggest the memory configuration through the light emitting component, so that the user can readjust the memory. Position the location to the recommended memory configuration.

以下將以圖式及詳細說明清楚說明本發明之精神,任何所屬技術領域中具有通常知識者在瞭解本發明之較佳實施例後,當可由本發明所教示之技術,加以改變及修飾,其並不脫離本發明之精神與範圍。The spirit and scope of the present invention will be apparent from the following description of the preferred embodiments of the invention. The spirit and scope of the invention are not departed.

本發明提出一種記憶體組態提前檢查電路,使使用者在開機之前即可得知記憶體組態是否與出場時所設定的建議記憶體組態相同,並可根據燈號所提示的建議記憶體組態重新安排記憶體的位置。The invention provides a memory configuration early check circuit, so that the user can know whether the memory configuration is the same as the recommended memory configuration set when exiting, and can be suggested according to the suggested prompt of the light number. The body configuration rearranges the location of the memory.

參照第1圖,其係繪示一種記憶體的示意圖。記憶體100之腳位中包含有多個接地腳110a、110b、110c,而記憶體100內部具有連接線112,以連接此些接地腳110a、110b、110c,使接地腳110a、110b、110c相互導通。只要其中有一個與接地端接地,所有相連的接地腳110a、110b、110c均可接地。Referring to Figure 1, there is shown a schematic diagram of a memory. The memory 100 includes a plurality of grounding legs 110a, 110b, and 110c, and the memory 100 has a connecting wire 112 therein to connect the grounding pins 110a, 110b, and 110c so that the grounding pins 110a, 110b, and 110c are mutually connected. Turn on. As long as one of them is grounded to the ground, all connected grounding legs 110a, 110b, 110c can be grounded.

參照第2A圖與第2B圖,其係分別繪示本發明之記憶體組態提前檢查電路一較佳實施例不同狀態的示意圖。記憶體組態提前檢查電路包含有設置於主機板210上之一記憶體插槽220及一邏輯電路230。記憶體插槽220中具有對應於記憶體100之接地腳110a、110b、110c的第一腳位222、第二腳位224、第三腳位226。其中第一腳位222為與邏輯電路230電性連接,第一腳位222更連接向一電源電壓端(Vcc)。第二腳位224與第三腳位226為透過連接線228相導通,並與接地端接地。Referring to Figures 2A and 2B, there are shown schematic views of different states of a preferred embodiment of the memory configuration advance check circuit of the present invention. The memory configuration advance check circuit includes a memory slot 220 and a logic circuit 230 disposed on the motherboard 210. The memory slot 220 has a first pin 222, a second pin 224, and a third pin 226 corresponding to the ground pins 110a, 110b, 110c of the memory 100. The first pin 222 is electrically connected to the logic circuit 230, and the first pin 222 is further connected to a power voltage terminal (Vcc). The second pin 224 and the third pin 226 are electrically connected through the connecting line 228 and grounded to the ground.

第2A圖中,記憶體未插入主機板210上之記憶體插槽220,此時,邏輯電路230所接收到之由記憶體插槽220之第一腳位222所傳來的電位為電源電壓(Vcc)的電位。In FIG. 2A, the memory is not inserted into the memory slot 220 on the motherboard 210. At this time, the potential received by the logic circuit 230 from the first pin 222 of the memory slot 220 is the power supply voltage. The potential of (Vcc).

第2B圖中,記憶體100已插入記憶體插槽220,此時,記憶體100之第一接地腳110a、第二接地腳110b、第三接地腳110c分別與記憶體插槽220上的第一腳位222、第二腳位224、第三腳位226接觸。記憶體插槽220中的第二腳位224與第三腳位226為與接地端連接,與之相接觸的記憶體100之第二接地腳110b、第三接地腳110c因此而接地,連帶著與第二接地腳110b、第三接地腳110c相導通的第一接地腳110a亦因此而接地,使得與第一接地腳110a接觸之記憶體插槽220的第一腳位222,可透過記憶體100而與主機板210的接地端接地。因此,當記憶體100插入記憶體插槽220之後,邏輯電 路230所接收到來自於記憶體插槽220之第一腳位222的電位為接地。In FIG. 2B, the memory 100 has been inserted into the memory slot 220. At this time, the first grounding leg 110a, the second grounding pin 110b, and the third grounding leg 110c of the memory 100 are respectively associated with the memory slot 220. One pin 222, second pin 224, and third pin 226 are in contact. The second pin 224 and the third pin 226 in the memory slot 220 are connected to the ground, and the second ground pin 110b and the third ground pin 110c of the memory 100 in contact with it are grounded accordingly. The first grounding leg 110a, which is electrically connected to the second grounding leg 110b and the third grounding leg 110c, is also grounded so that the first pin 222 of the memory slot 220 in contact with the first grounding leg 110a is permeable to the memory. 100 is grounded to the ground of the motherboard 210. Therefore, when the memory 100 is inserted into the memory slot 220, the logic is The potential received by the path 230 from the first pin 222 of the memory slot 220 is grounded.

由於記憶體100未插入記憶體插槽220時,記憶體插槽220之第一腳位222所傳給邏輯電路230的電位為電源電壓(Vcc)(高電位)。而當記憶體100插入記憶體插槽220後,記憶體插槽220之第一腳位222所傳給邏輯電路230的電位為接地(低電位)。邏輯電路230可根據記憶體插槽220之第一腳位222提供高電位或是低電位,得知此記憶體插槽220是否安裝有記憶體100。Since the memory 100 is not inserted into the memory slot 220, the potential transmitted to the logic circuit 230 by the first pin 222 of the memory slot 220 is the power supply voltage (Vcc) (high potential). When the memory 100 is inserted into the memory slot 220, the potential transmitted to the logic circuit 230 by the first pin 222 of the memory slot 220 is grounded (low potential). The logic circuit 230 can provide a high potential or a low potential according to the first pin 222 of the memory slot 220, and whether the memory slot 220 is mounted with the memory 100.

參照第3圖,其係繪示本發明之記憶體組態提前檢查電路另一較佳實施例之電路圖。本實施例包含有多個記憶體插槽310a、310b、310c,一邏輯電路320,與一發光元件330。其中記憶體插槽310a、310b、3110c分別與邏輯電路320電性連接,發光元件330則與邏輯電路320電性連接。記憶體插槽310a、310b、310c之第一腳位312a、312b、312c分別與電源電壓端(Vcc)相連,記憶體插槽310a、310b、310c之第二腳位314a、314b、314c則分別與主機板上之接地端進行接地。Referring to Figure 3, there is shown a circuit diagram of another preferred embodiment of the memory configuration advance check circuit of the present invention. This embodiment includes a plurality of memory slots 310a, 310b, 310c, a logic circuit 320, and a light emitting element 330. The memory slots 310a, 310b, and 3110c are electrically connected to the logic circuit 320, and the light-emitting elements 330 are electrically connected to the logic circuit 320. The first pins 312a, 312b, and 312c of the memory slots 310a, 310b, and 310c are respectively connected to the power supply voltage terminal (Vcc), and the second pins 314a, 314b, and 314c of the memory sockets 310a, 310b, and 310c are respectively Ground the ground terminal on the motherboard.

本實施例中,第一記憶體插槽310a、第二記憶體插槽310b未安裝有記憶體,第三記憶體插槽310c安裝有一記憶體350。如前所述,未安裝有記憶體350之第一記憶體插槽310a、第二記憶體插槽310b提供高電位給邏輯電路320,而安裝有記憶體350之第三記憶體插槽310c則會提供低電位給邏輯電路320。邏輯電路320可藉此得 知目前的記憶體組態。In this embodiment, the first memory slot 310a and the second memory slot 310b are not mounted with a memory, and the third memory slot 310c is mounted with a memory 350. As described above, the first memory slot 310a and the second memory slot 310b, to which the memory 350 is not mounted, provide a high potential to the logic circuit 320, and the third memory slot 310c to which the memory 350 is mounted. A low potential is provided to the logic circuit 320. Logic circuit 320 can be derived therefrom Know the current memory configuration.

邏輯電路320設定有出場時的建議記憶體組態,並透過高低電位判斷插入的記憶體組態是否與內建的建議記憶體組態相同。若是目前的記憶體組態與邏輯電路320內建的記憶體組態不同,則邏輯電路320發出一警示訊號至發光元件330,使發光元件330作動而提醒使用者。使用者可重新擺放記憶體350,當發光元件330不再發光時,即代表當前的記憶體組態符合出場時建議的記憶體組態。The logic circuit 320 sets the recommended memory configuration at the time of appearance, and judges whether the inserted memory configuration is the same as the built-in recommended memory configuration through the high and low potentials. If the current memory configuration is different from the built-in memory configuration of the logic circuit 320, the logic circuit 320 sends a warning signal to the light-emitting element 330 to cause the light-emitting element 330 to act to alert the user. The user can reposition the memory 350. When the light-emitting element 330 is no longer illuminated, it means that the current memory configuration conforms to the recommended memory configuration at the time of appearance.

記憶體提前檢查電路中更包含有一基板管理控制器340(baseboard management controller;BMC),基板管理控制器340係與邏輯電路320電性連接。當邏輯電路320判斷目前的記憶體組態與內建的建議記憶體組態相同時,邏輯電路320會傳送一開機許可訊號至基板管理控制器340,使電腦開機。The memory pre-check circuit further includes a baseboard management controller 340 (BMC), and the baseboard management controller 340 is electrically connected to the logic circuit 320. When the logic circuit 320 determines that the current memory configuration is the same as the built-in recommended memory configuration, the logic circuit 320 transmits a power-on permission signal to the baseboard management controller 340 to turn the computer on.

參照第4圖,其係繪示本發明之記憶體組態提前檢查電路又一較佳實施例之電路圖。本實施例之記憶體插槽410係連接至微控制器420,本實施例中包含有多個發光元件430與微控制器420電性連接,其中,發光元件430為一對一地對應於記憶體插槽410。微控制器420可為一複雜型可程式邏輯裝置(Complex Programmable Logic Device;CPLD)。Referring to Figure 4, there is shown a circuit diagram of still another preferred embodiment of the memory configuration advance check circuit of the present invention. The memory slot 410 of the embodiment is connected to the microcontroller 420. In this embodiment, the plurality of light-emitting elements 430 are electrically connected to the microcontroller 420. The light-emitting elements 430 correspond to the memory one-to-one. Body slot 410. The microcontroller 420 can be a Complex Programmable Logic Device (CPLD).

如前所述,當記憶體插槽410安裝有記憶體(圖中未繪示)時,該記憶體插槽410可提供低電位給微控制器 420,而未安裝有記憶體之記憶體插槽410則會提供高電位給微控制器420。微控制器420可籍此得知目前的記憶體組態。記憶體組態提前檢查電路可透過微控制器420進一步地強化其功能。As described above, when the memory slot 410 is mounted with a memory (not shown), the memory slot 410 can provide a low potential to the microcontroller. 420, and the memory slot 410 without the memory installed provides a high potential to the microcontroller 420. The microcontroller 420 can then learn the current memory configuration. The memory configuration advance check circuit can further enhance its functionality through the microcontroller 420.

若是當前的記憶體組態與微控制器420中所設定的建議記憶體組態相符,則微控制器420可發出一開機許可訊號至基板管理控制器440,使電腦開機。若是當前的記憶體組態與微控制器420中所設定的建議記憶體組態不相符,則微控制器420可控制發光元件430顯示建議記憶組態,即控制對應於建議記憶體組態的發光元件430發光,令使用者可依照燈號指示的建議記憶體組態將記憶體放置在建議的記憶體插槽之中。If the current memory configuration matches the recommended memory configuration set in the microcontroller 420, the microcontroller 420 can issue a power-on permission signal to the baseboard management controller 440 to power up the computer. If the current memory configuration does not match the recommended memory configuration set in the microcontroller 420, the microcontroller 420 can control the light-emitting component 430 to display the suggested memory configuration, ie, the control corresponds to the suggested memory configuration. The illuminating element 430 illuminates, allowing the user to place the memory in the suggested memory slot in accordance with the suggested memory configuration indicated by the illuminator.

由上述本發明較佳實施例可知,應用本發明具有下列優點。本發明之記憶體組態提前檢查電路可在系統開機前即告知使用者記憶體組態有誤,並可透過發光元件提示使用者建議的記憶體組態,令使用者可重新調整記憶體的擺放位置到所建議的記憶體組態。It will be apparent from the above-described preferred embodiments of the present invention that the application of the present invention has the following advantages. The memory configuration early check circuit of the invention can inform the user that the memory configuration is wrong before the system is turned on, and can prompt the user to suggest the memory configuration through the light emitting component, so that the user can readjust the memory. Position the location to the recommended memory configuration.

雖然本發明已以一較佳實施例揭露如上,然其並非用以限定本發明,任何熟習此技藝者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been described above in terms of a preferred embodiment, it is not intended to limit the invention, and it is obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧記憶體100‧‧‧ memory

110a‧‧‧第一接地腳110a‧‧‧First grounding foot

110b‧‧‧第二接地腳110b‧‧‧Second grounding foot

110c‧‧‧第三接地腳110c‧‧‧ third grounding foot

112‧‧‧連接線112‧‧‧Connecting line

210‧‧‧主機板210‧‧‧ motherboard

220‧‧‧記憶體插槽220‧‧‧ memory slot

222‧‧‧第一腳位222‧‧‧First position

224‧‧‧第二腳位224‧‧‧second foot

226‧‧‧第三腳位226‧‧‧ third position

228‧‧‧連接線228‧‧‧Connecting line

230‧‧‧邏輯電路230‧‧‧Logical Circuit

310a‧‧‧第一記憶體插槽310a‧‧‧First memory slot

310b‧‧‧第二記憶體插槽310b‧‧‧Second memory slot

310c‧‧‧第三記憶體插槽310c‧‧‧ third memory slot

312a‧‧‧第一腳位312a‧‧‧First position

312b‧‧‧第一腳位312b‧‧‧First position

312c‧‧‧第一腳位312c‧‧‧First position

314a‧‧‧第二腳位314a‧‧‧second foot

314b‧‧‧第二腳位314b‧‧‧second foot

314c‧‧‧第二腳位314c‧‧‧second foot

320‧‧‧邏輯電路320‧‧‧Logical Circuit

330‧‧‧發光元件330‧‧‧Lighting elements

340‧‧‧基板管理控制器340‧‧‧Baseboard Management Controller

350‧‧‧記憶體350‧‧‧ memory

410‧‧‧記憶體插槽410‧‧‧ memory slot

420‧‧‧微控制器420‧‧‧Microcontroller

430‧‧‧發光元件430‧‧‧Lighting elements

440‧‧‧基板管理控制器440‧‧‧Base management controller

為讓本發明之上述和其他目的、特徵、優點與實施 例能更明顯易懂,所附圖式之詳細說明如下:第1圖係繪示一種記憶體的示意圖。The above and other objects, features, advantages and embodiments of the present invention are made. The examples can be more clearly understood, and the detailed description of the drawings is as follows: FIG. 1 is a schematic diagram showing a memory.

第2A圖與第2B圖係分別繪示本發明之記憶體組態提前檢查電路一較佳實施例不同狀態的示意圖。2A and 2B are schematic views respectively showing different states of a preferred embodiment of the memory configuration advance check circuit of the present invention.

第3圖係繪示本發明之記憶體組態提前檢查電路另一較佳實施例之電路圖。Figure 3 is a circuit diagram showing another preferred embodiment of the memory configuration advance check circuit of the present invention.

第4圖係繪示本發明之記憶體組態提前檢查電路又一較佳實施例之電路圖。Figure 4 is a circuit diagram showing still another preferred embodiment of the memory configuration advance check circuit of the present invention.

100‧‧‧記憶體100‧‧‧ memory

110a‧‧‧第一接地腳110a‧‧‧First grounding foot

110b‧‧‧第二接地腳110b‧‧‧Second grounding foot

110c‧‧‧第三接地腳110c‧‧‧ third grounding foot

112‧‧‧連接線112‧‧‧Connecting line

210‧‧‧主機板210‧‧‧ motherboard

220‧‧‧記憶體插槽220‧‧‧ memory slot

222‧‧‧第一腳位222‧‧‧First position

224‧‧‧第二腳位224‧‧‧second foot

226‧‧‧第三腳位226‧‧‧ third position

230‧‧‧邏輯電路230‧‧‧Logical Circuit

Claims (9)

一種記憶體組態提前檢查電路,包含:複數個記憶體插槽,用以安裝至少一記憶體;一邏輯電路,與該些記憶體插槽電性連接,該邏輯電路設定有一建議記憶體組態,安裝有該至少一記憶體之記憶體插槽分別提供一低電位至該邏輯電路,未安裝有該至少一記憶體之記憶體插槽則分別提供一高電位至該邏輯電路,藉以判斷該至少一記憶體之一記憶體組態是否與該建議記憶體組態相同;一發光元件,與該邏輯電路電性連接,當該記憶體組態與該建議記憶體組態不同時,該邏輯電路發出一警示訊號至該發光元件,使該發光元件作動;以及一基板管理控制器(baseboard management controller;BMC),與該邏輯電路電性連接,當該邏輯電路判斷該記憶體組態正確後,該邏輯電路發出一開機許可訊號至該基板管理控制器。 A memory configuration early check circuit includes: a plurality of memory slots for mounting at least one memory; a logic circuit electrically connected to the memory sockets, the logic circuit is provided with a suggested memory group a memory slot in which the at least one memory is mounted respectively provides a low potential to the logic circuit, and a memory slot in which the at least one memory is not provided respectively provides a high potential to the logic circuit, thereby determining Whether the memory configuration of the at least one memory is the same as the recommended memory configuration; a light-emitting element electrically connected to the logic circuit, when the memory configuration is different from the recommended memory configuration, The logic circuit sends a warning signal to the light emitting component to activate the light emitting component; and a baseboard management controller (BMC) is electrically connected to the logic circuit, and when the logic circuit determines that the memory is configured correctly After that, the logic circuit sends a power-on permission signal to the baseboard management controller. 如申請專利範圍第1項所述之記憶體組態提前檢查電路,其中每一記憶體具有一第一接地腳與一第二接地腳,該第一接地腳與該第二接地腳相導通。 The memory configuration advance check circuit of claim 1, wherein each memory has a first grounding leg and a second grounding pin, and the first grounding pin is electrically connected to the second grounding leg. 如申請專利範圍第2項所述之記憶體組態提前檢查電路,其中每一記憶體插槽具有對應於該第一接地腳 之一第一腳位與對應於該第二接地腳之一第二腳位,該第一腳位係藉串連一電阻連接向一電源電壓端,該第二腳位係連接向一接地端。 The memory configuration early check circuit of claim 2, wherein each memory slot has a corresponding first ground pin One of the first pin corresponds to the second pin of the second ground pin, and the first pin is connected to a power voltage terminal by a series connection, and the second pin is connected to a ground. . 如申請專利範圍第3項所述之記憶體組態提前檢查電路,其中插有記憶體之該至少一記憶體插槽之該第一腳位經由該記憶體與該第二腳位導通,以提供該低電位給該邏輯電路。 The memory configuration advance check circuit according to claim 3, wherein the first pin of the at least one memory slot in which the memory is inserted is electrically connected to the second pin via the memory, This low potential is provided to the logic circuit. 一種記憶體組態提前檢查電路,包含:複數個記憶體插槽,用以安裝至少一記憶體;一微控制器,與該些記憶體插槽電性連接,該微控制器設定有一建議記憶體組態,安裝有該至少一記憶體之記憶體插槽提供一低電位至該微控制器,未安裝有該至少一記憶體之記憶體插槽則分別提供一高電位至該微控制器,藉以判斷該至少一記憶體之一記憶體組態是否與該建議記憶體組態相同;複數個發光元件,與該微控制器電性連接,該些發光元件為一對一地對應該些記憶體插槽,其中當該記憶體組態與該建議記憶體組態不符時,該些發光元件會顯示該建議記憶體組態;以及一基板管理控制器(baseboard management controller;BMC),與該邏輯電路電性連接,當該邏輯電路判斷該記憶體組態正確後,該邏輯電路發出一開機許 可訊號至該基板管理控制器。 A memory configuration early check circuit includes: a plurality of memory slots for mounting at least one memory; a microcontroller electrically connected to the memory slots, the microcontroller setting a suggested memory a body configuration, the memory slot in which the at least one memory is mounted provides a low potential to the microcontroller, and the memory slot in which the at least one memory is not mounted respectively provides a high potential to the microcontroller And determining whether the memory configuration of the at least one memory is the same as the recommended memory configuration; the plurality of light-emitting elements are electrically connected to the micro-controller, and the light-emitting elements are corresponding to one-to-one a memory slot, wherein when the memory configuration does not match the recommended memory configuration, the light-emitting elements display the suggested memory configuration; and a baseboard management controller (BMC), and The logic circuit is electrically connected, and when the logic circuit determines that the memory is configured correctly, the logic circuit issues a power-on Signals can be sent to the baseboard management controller. 如申請專利範圍第5項所述之記憶體組態提前檢查電路,其中該微控制器包含一複雜型可程式邏輯裝置(Complex Programmable Logic Device;CPLD)。 The memory configuration early check circuit according to claim 5, wherein the microcontroller comprises a Complex Programmable Logic Device (CPLD). 如申請專利範圍第5項所述之記憶體組態提前檢查電路,其中每一記憶體具有一第一接地腳與一第二接地腳,該第一接地腳與該第二接地腳相導通。 The memory configuration advance check circuit of claim 5, wherein each memory has a first grounding leg and a second grounding pin, and the first grounding pin is electrically connected to the second grounding leg. 如申請專利範圍第7項所述之記憶體組態提前檢查電路,其中每一記憶體插槽具有對應於該第一接地腳之一第一腳位與對應於該第二接地腳之一第二腳位,該第一腳位係藉串連一電阻連接向一電源電壓端,該第二腳位係連接向一接地端。 The memory configuration early check circuit of claim 7, wherein each memory slot has a first pin corresponding to one of the first ground pins and one corresponding to the second ground pin In the two-pin position, the first pin is connected to a power voltage terminal by a series-connected resistor, and the second pin is connected to a ground terminal. 如申請專利範圍第8項所述之記憶體組態提前檢查電路,其中插有記憶體之該至少一記憶體插槽之該第一腳位經由該記憶體與該第二腳位導通,以提供該低電位給該微控制器。 The memory configuration advance check circuit of claim 8, wherein the first pin of the at least one memory slot in which the memory is inserted is electrically connected to the second pin via the memory, This low potential is provided to the microcontroller.
TW97134892A 2008-09-11 2008-09-11 Circuit for checking memeory status in advance TWI384485B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW97134892A TWI384485B (en) 2008-09-11 2008-09-11 Circuit for checking memeory status in advance

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW97134892A TWI384485B (en) 2008-09-11 2008-09-11 Circuit for checking memeory status in advance

Publications (2)

Publication Number Publication Date
TW201011766A TW201011766A (en) 2010-03-16
TWI384485B true TWI384485B (en) 2013-02-01

Family

ID=44828744

Family Applications (1)

Application Number Title Priority Date Filing Date
TW97134892A TWI384485B (en) 2008-09-11 2008-09-11 Circuit for checking memeory status in advance

Country Status (1)

Country Link
TW (1) TWI384485B (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6000048A (en) * 1996-08-14 1999-12-07 Cirrus Logic, Inc. Combined logic and memory circuit with built-in memory test
US20020027556A1 (en) * 1996-03-21 2002-03-07 Kazushige Yamagishi Data processor with built-in dram
TW200410072A (en) * 2002-12-13 2004-06-16 Samsung Electronics Co Ltd Computer system and control method thereof
TWI254853B (en) * 2004-07-09 2006-05-11 Via Tech Inc Method and device for initialization drams
TW200713292A (en) * 2005-09-20 2007-04-01 Transcend Information Inc Method, apparatus, and system for memory test
US20070168147A1 (en) * 2006-01-19 2007-07-19 International Business Machines Corporation Acquiring test data from an electronic circuit

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020027556A1 (en) * 1996-03-21 2002-03-07 Kazushige Yamagishi Data processor with built-in dram
US6000048A (en) * 1996-08-14 1999-12-07 Cirrus Logic, Inc. Combined logic and memory circuit with built-in memory test
TW200410072A (en) * 2002-12-13 2004-06-16 Samsung Electronics Co Ltd Computer system and control method thereof
TWI254853B (en) * 2004-07-09 2006-05-11 Via Tech Inc Method and device for initialization drams
TW200713292A (en) * 2005-09-20 2007-04-01 Transcend Information Inc Method, apparatus, and system for memory test
US20070168147A1 (en) * 2006-01-19 2007-07-19 International Business Machines Corporation Acquiring test data from an electronic circuit

Also Published As

Publication number Publication date
TW201011766A (en) 2010-03-16

Similar Documents

Publication Publication Date Title
US9552315B2 (en) Determining addresses of electrical components arranged in a daisy chain
US20080036468A1 (en) Apparatus to facilitate functional shock and vibration testing of device connections and related method
TWI533122B (en) Boot detecting circuit, computer system and boot detecting method thereof
JP2009134705A (en) Detection system for peripheral device
US9075135B2 (en) Reporting connection failure
US20150324321A1 (en) Detecting device installation and removal on a port
US8443234B2 (en) Bios refresh device and method using the same
US20100185880A1 (en) Test apparatus
TW201346542A (en) Power on indication circuit
TW201337545A (en) Display device capable of displaying power on self test (POST) information
TWI492045B (en) Method and fixture of measure for computer device
TWI384485B (en) Circuit for checking memeory status in advance
US7216241B2 (en) Self-testing power supply which indicates when an output voltage is within tolerance while not coupled to an external load
US20160342800A1 (en) Electronic device and hard disk device of electronic device
US20060152379A1 (en) Self contained monitoring circuit and an electrical appliance incorporating such circuit
US9189931B2 (en) Circuitry with warning function
US10025683B2 (en) Information processing device and computer-readable recording medium
US10838478B1 (en) Power system
TWI448880B (en) Power-on selecting circuit
US9686881B2 (en) Server
US11828799B2 (en) Electrical property testing device of evaluation board
JP6856884B1 (en) Information processing systems, information processing equipment and programs
CN114238001A (en) Server mainboard power-on circuit and power-on method
CN105696251B (en) Washing machine and method for setting payment mode of coin-operated washing machine
KR101721680B1 (en) Display apparatus having a power booting portion and method for re-booting power using the same

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees