TWI384342B - Current control method and apparatus - Google Patents

Description

Current control method and device

The present invention relates to a power supply, and more particularly to a maximum current control circuit and method for use in a power supply.

In the switching power supply, PWM technology has been widely used to control or adjust the output power. In order to prevent permanent damage to the power supply, many power supply circuits have built-in protection circuits, such as over voltage and over current circuits. Among them, the limitation of output power is generally used to protect against overload or output short circuit.

Please refer to FIG. 1 , which is a conventional PWM power supply 100 . The controller 106 can generate a PWM signal that controls whether the power switch 102 is turned "ON" or "OFF". When the power switch 102 is turned on, the power supply voltage V _IN charges the primary coil of the transformer 104 such that the current flowing through the main winding gradually increases. When the power switch 102 is turned off, the energy stored in the transformer 104 is discharged by charging the output capacitor through the secondary coil. The resistor R _{CS is} connected in series with the power switch 102, so its voltage across the V _CS is the current flowing through the power switch 102 and/or the main winding. When the voltage across the V _{CS is} greater than or equal to a certain value, such as the value represented by the current limit signal V _LIMIT , it means that the current flowing through the power switch 102 and/or the main winding is excessively risky, and the controller 106 The power switch 102 is turned off to stop the current of the main winding from continuing to increase. In other words, the current limit signal V _LIMIT can limit the maximum output power of the PWM power supply 100.

However, if the current limit signal V _LIMIT is a constant constant, the maximum output power may vary with the magnitude of the supply voltage v _IN due to the signal transfer delay (signa1 propagation delay). When the voltage across the V _{CS is} greater than or equal to the current limit signal V _LIMIT , a certain signal delay time t _DELAY must be required when the controller 106 actually turns off the power switch 102. During this period of signal delay time t _DELAY , the current of the main winding will still increase, and the increase will be proportional to the value of the current power supply voltage V _IN . Therefore, the true maximum output power increases as the power supply voltage V _IN becomes larger.

U.S. Patent No. 6,674,656 (hereinafter referred to as '656 patent) provides a solution (PWM controller having a saw-limiter for output power limit without sensing input voltage). Figure 2 illustrates a method concept in the '656 patent. In the '656 patent, the current limit signal V _LIMIT is not a constant. The waveform converter 202 receives the saw-tooth signal output from the oscillator 204, and then sequentially adjusts the slope, the clamp process, and the level shift to generate the current limit signal V as shown in FIG. _LIMIT . In each cycle, the current limit signal V _LIMIT changes over time, starting with a rise from a minimum voltage and finally clamping to a maximum voltage. Figure 3 shows the waveform with the current limit signal V _{LIMIT and} the waveform of the two voltages V _CS , where the voltage across the V _CS (V _INHIGH ) represents the voltage across the V _CS when the supply voltage V _{IN is} high. The cross voltage V _CS (V _INLOW ) represents the voltage across the V _CS when the power supply voltage V _{IN is} low. It can be seen from Fig. 3 that when the power supply voltage V _{IN is} high, the voltage across the V _CS (V _INHIGH ) also rises faster, and a lower current limit signal V _LIMIT is encountered, thereby improving the signal delay time. The problem of possible maximum output power instability.

One embodiment of the present invention provides a method. A switch is first turned on, which is connected in series with an energy transfer element of a power supply. A current limit signal and an ideal current limit value are provided. Detects current through one of the switches. When the current exceeds the current limit signal, the switch is turned off. The maximum value of this current is detected. The current limit signal is updated based on the maximum value and the ideal current limit value.

An embodiment of the present invention provides an apparatus including a current limiter and a limit signal generator. The current limiter is coupled to a switch. The switch is in series with one of the power delivery elements of a power supply. The current limiter detects a current through the switch and turns off the switch when the current exceeds a current limit signal. The limit signal generator is configured to provide the current limit signal, detect a maximum value of the current, and update the current limit signal according to the maximum value and an ideal current limit value.

One embodiment of the present invention provides a method. Turn on a switch in one cycle. The switch is in series with one of the power delivery elements of a power supply. Detects the current through one of the switches when the switch is turned on. A current limit signal is provided. When the current exceeds the current limit signal, the switch is turned off. The current limit signal is a certain value when the switch is turned on during the period. The current limiting signal updates the current limiting signal as a current limiting signal for use in a subsequent cycle based on a current detection result in the cycle.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

Figure 4 is a circuit diagram of a power supply circuit in accordance with an embodiment of the present invention. The power supply 400 is a flyback power converter including a power switch 402, a transformer 404, a limit signal generator 500, a comparator 410, a controller 412, a resistor R _CS , a diode 414, and a rectified load. Capacitor C _O . Controller 412 controls power switch 402 to be turned "off" or "on" to control charging of transformer 404 or discharging transformer 404. The resistor R _CS detects the current flowing through the main winding of the transformer 404 and is also used to control the output power of the power supply 400. The limit signal generator 500 outputs a current limit signal V _LIMIT . The limit signal generator 500 will be explained in detail later. The comparator 410 compares the current limit signal V _LIMIT with the voltage across the voltage V _CS generated by the resistor R _CS , and the controller 412 controls the power switch 402 in accordance with the output of the comparator 410.

The limit signal generator 500 detects the maximum value of the power switch 402 flowing through the current cycle, that is, the maximum value of the voltage across the V _CS , and then updates/changes the current limit signal V _LIMIT to generate the current of the next cycle. Limit signal V _LIMIT . In other words, the limit signal generator 500 will cycle-by-cycle the update current limit signal V _LIMIT . Moreover, the current limit signal V _LIMIT is a constant value during the time that the power switch 402 is turned on.

Figure 5 is a signal diagram showing an embodiment of the present invention in which the current limit signal V _LIMIT and the voltage across the V _CS in the nth and n+1th cycles are shown. V _CS-MAX (n) represents the peak value of the current flowing through the power switch 402 during the nth cycle; V _LIMIT (n) represents the reference value actually used to limit the current flowing through the power switch 402 during the nth cycle; V _{CS- IDEAL} represents the ideal current limit value flowing through power switch 402; dV _CS (n) represents the actual difference between V _{CS- MAX} (n) and V _CS-IDEAL (=V _CS-MAX (n)-V _CS-IDEAL ) ;dV _LIMIT (n) represents the updated difference between V _LIMIT (n) and V _LIMIT (n+1) (=V _LIMIT (n)-V _LIMIT (n+1)).

As can be seen from Fig. 5, in the nth cycle, although the crossover voltage V _CS has reached the reference value V _LIMIT (n), the crossover voltage V _CS does not fall immediately but arrives because of the signal transmission delay. When the current peak value V _CS-MAX (n), it begins to drop. Moreover, the current peak value V _CS-MAX (n) is higher than the ideal current limit value V _CS-IDEAL . This means that the reference value V _LIMIT (n) of this cycle is too high to produce a current peak V _CS-MAX (n) above the ideal current limit value V _CS-IDEAL . If the reference value V _LIMIT (n+1) can be lowered, the expected current peak value V _CS-MAX (n+1) will drop together and be closer to the ideal current limit value V _CS-IDEAL . If the actual difference (=V _CS-MAX (n)-V _CS-IDEAL ) is directly used as the update difference dV _LIMIT (n) to generate the reference value V _LIMIT (n+1), then it can be expected that the current The peak VC _S-MAX (n+1) is almost exactly equal to the ideal current limit value V _CS-IDEAL , as shown in the n+1th cycle of Figure 5.

Therefore, an embodiment of the present invention is to periodically update the reference value V _LIMIT . Moreover, the update difference dV _LIMIT (n) used for each update is proportional to the actual difference dV _CS (n) between the maximum current through the power transistor detected by the current cycle and a desired expected value. When expressed by a formula, as in the following formula (1) V _LIMIT (n+1)=V _LIMIT (n)-k×(V _CS-MAX (n)-V _CS-IDE A _L )...(1)

It can be expected that the difference between the current peak value V _CS-MAX (n+1) and the reference value V _LIMIT (n+1) caused by the signal transmission delay in the n+1th cycle should be the current peak value V _CS-MAX ( n) The difference between the reference value V _LIMIT (n) is the same. So V _CS-MAX (n+1)=V _LIMIT (n+1)+(V _CS-MAX (n)-V _LIMIT (n)).........(2)

Substituting V _LIMIT (n+1) in equation (2) with equation (1) yields V _CS-MAX (n+1)=V _CS-MAX (n)-k×(V _CS-MAX (n) )-V _CS-IDEAL )=(1-k)×V _CS-MAX (n)+k×V _CS-IDEAL .........(3)

The following conclusion can be derived from equation (3): V _CS-MAX (1)=(1-k)V _CS-MAX (0)+kV _CS-IDEAL V _CS-MAX (2)=(1-k)V _CS-MAX (1)+kV _CS-IDEAL =(1-k) ² V _CS-MAX (0)+((1-k)k+k)×V _CS-IDEAL .....V _CS-MAX (n)=(1-k) ⁿ V _CS-MAX (0)+[1-(1-k) ⁿ ]×V _CS-IDEAL

When |1-k|<1, as the value of n increases, the current peak value V _CS-MAX (n) approaches the ideal current limit value V _CS-IDEAL , and this value will follow V _LIMIT (0) or V. _CS-MAX (0) These start values are irrelevant. This means that as long as the circuit can achieve the result of equation (1), the value of k can be blurred between 0 and 2, and does not have to care about the V _LIMIT (0) preset at the beginning, the current peak V _{CS -MAX} (n) will eventually be locked to the ideal current limit value V _CS-IDEAL . For the speed of convergence, k is preferably between 0.5 and 1.5. It is best to be equal to 1, because as long as it is the next cycle, V _CS-MAX (1) becomes V _CS-IDEAL directly.

Fig. 6 is an embodiment of the limit signal generator in Fig. 4, and the result of the formula (1) can be realized. The limit signal generator 500 includes a correction signal generator 502 and a limit signal updater 504. The correction signal generator 502 detects the voltage across the V _CS and the current limit signal V _LIMIT , according to the current limit signal V _LIMIT before the update, the peak value of the detected voltage across the V _CS , and the ideal current limit value V _CS-IDEAL To generate the correction signal V _LIMIT-next . The limit signal updater 504 updates the current limit signal V _LIMIT with the correction signal V _LIMIT-next .

In the correction signal generator 502, the current I ₁ is as large as I ₂ ; the current I ₃ is as large as I ₄ ; the current mirror formed by the MOS M ₃₀ and M ₂₀ causes the flow through the MOS M ₂₀ and M ₃₀ the current ratio, should the current I ₂ I ₃ ratio is equal with the current; current mirror (current mirror) formed by MOS M ₄₀ and M _10, causing a current proportional to the flow through the MOS M ₄₀ M _10, the current should be with I ₄ is equal to the current ratio of I ₁ .

Assume that the timing signal generator 500 is operating in the nth cycle, assuming timing. The correction signal generator 502 has a peak sampler P _sample . When the signal V _G turns off the power switch 402, the voltage value stored by the capacitor in the peak sampler P _sample is the current peak value V _CS-MAX (n).

MOS M ₁ forms part of a source follower. Therefore, when the current peak value V _CS-MAX (n) is stored in the capacitor, the voltage at the left end of the resistor R ₁ is maintained at V _CS-MAX (n) + V _th-M1 , where V _th-M1 is MOS M ₁ Threshold voltage.

By the same token, the voltage at the right end of resistor R ₁ is maintained at V _CS-IDEAL +V _th-M2 , where V _th-M2 is the threshold voltage of MOS M ₂ and will be similar to V _th-M1 . At this time, the current flowing through the resistor R ₁ is I ₁ = (V _{CS - MAX} (n) - V _{CS - IDEAL} ) / R ₁₀ , and R ₁₀ is the resistance value of the resistor R ₁ .

The current I _{1 is} also the difference current flowing through the MOS M ₁ and M ₂ , so it is also the difference current flowing through the MOS M ₁₀ and M ₂₀ . After the current mirror is converted, the current I ₂ flowing through the resistor R ₂ is proportional to the current I ₁ , that is, the current I ₂ =m × the current I ₁ .

The voltage at the right end of resistor R ₂ is maintained at V _LIMIT (n) + V _th-M4 . Assuming that the resistance value of the resistor R ₂ is R ₂₀ , the correction signal V _LIMIT-next can be derived as follows.

V _LIMIT-next =V _LIMIT (n)+V _th-M4 -I ₂ ×R ₂₀ -V _th-M3 ~V _LIMIT (n)-R ₂₀ /R ₁₀ ×m×(V _CS-MAX (n)- V _CS-IDEAL ).........(4)

Fig. 7 is an embodiment of the limit signal updater in Fig. 6. The signal V _S is a signal generated after the signal V _G is delayed by the delay 602 for a certain time dt. Shortly after the signal V _G turns on the power switch 402, the signal V _S turns on MOS M _S1 and turns off MOS M _S2 . When the signal V _G turns off the power switch 402, the signal V _S still turns on the MOS M _S1 and turns off the MOS M _S2 , so one end of the capacitor C ₁ memorizes the value of the correction signal V _LIMIT-next , and one end of the capacitor C ₂ , the reference value V _LIMIT (n) of the current limit signal V _LIMIT for this period is memorized. The time dt must be long enough for the current peak value V _CS-MAX (n) to faithfully affect the correction signal V _LIMIT-next , that is, the value of the correction signal V _LIMIT-next conforms to the result of equation (4). Therefore, when the signal V _G turns off the power switch 402 for a time dt, the signal V _S turns off the MOS M _S1 , turns on the MOS M _S2 , and updates the current limit signal V _LIMIT with the correction signal V _LIMIT-next , resulting in the next cycle. The reference value V _LIMIT (n+1) is used and is stored at one end of the capacitor C ₂ . Assuming that the capacitance values of the capacitances C ₁ and C ₂ are C ₁₀ and C ₂₀ , respectively, V _LIMIT (n+1) can be derived from the charge sharing and the formula (4), which are derived from the following formula.

V _LIMIT (n+1)=V _LIMIT (n)-R ₂₀ /R ₁₀ ×m×C ₁₀ /(C ₁₀ +C ₂₀ )×(V _CS-MAX (n)-V _CS-IDEAL )......... (5)

Comparing the formula (5) with the formula (1), as long as the value of R ₂₀ /R ₁₀ ×m×C ₁₀ /(C ₁₀ +C ₂₀ ) is preferably 1 or between 0 and 2, then In this embodiment, after several switching cycles, the peak value of the voltage across the V _cs can be converged to the ideal current limit value V _CS-IDEAL to limit the current through the power switch. Moreover, the value of the resistor and capacitor here does not need to be very accurate, but the ratio value needs to fall within a very large range, so it is very easy to achieve for the actual circuit layout.

The limit signal updater 504 in FIG. 7 also has two ideal diodes for clamping the value of the current limit signal V _{LIMIT to} the ideal current limit value V _CS-IDEAL and a preset minimum value V _{CS-MIN .} between. In this way, it is possible to avoid the problem that the peak value of the cross voltage V _CS is too large or too small before the current limit signal V _LIMIT has not converge.

It can be seen from the embodiment of the present invention that after updating the current limit signal V _{LIMIT for} one cycle and one cycle, the peak value of the voltage across the V _cs can be very accurately limited to the ideal current limit value V _CS-IDEAL . Moreover, embodiments of the present invention do not require precise resistance and capacitance and are very easy to implement.

The embodiment of Fig. 6 is to perform a current limit signal V _LIMIT update operation each time the power switch has an on and off operation. However, the power switch is turned on and off, not necessarily because the current through the power switch is too high. Therefore, in another embodiment of the present invention, the current limit signal V _LIMIT update operation is performed only once when the power switch has an on and off operation once and the current through the power switch is too high. In one embodiment, the signals V _{G in} FIGS. 6 and 7 may all be replaced with a signal V _G′ , and the signal V _G′ is the signal V _{G in} FIG. 4 and the output signal of the comparator 410. The result of the AND of the V _P .

When the ideal current limit value V _CS-IDEAL is a constant constant value, an embodiment of the present invention can accurately define the maximum current flowing through the power switch to a corresponding constant value, completely solving the signal transmission delay. Possible problems.

However, taking Figure 4 as an example, even if the maximum current of the power switch 402 is limited to a corresponding fixed value, it does not mean that the output current I _{o of the} external load is rectified when the rectified load capacitance C _{O is} maintained at a constant value. It varies with the value of the power supply voltage V _IN . For example, when the power supply 400 operates in a continuous conduction mode (CCM) and V _o is a preset value, the average output current I _o may change as the value of the power supply voltage V _IN changes. .

In other embodiments of the invention, the ideal current limit value V _CS-IDEAL may not be a constant constant value, but may change over time or may change over time.

Figure 8 is a diagram of an apparatus for generating an ideal current limit value V _CS-IDEAL in one embodiment of the invention. Wherein, the waveform converter 802 receives the saw-tooth signal or the triangular wave signal output from the oscillator 804, and then generates an ideal current limit value V _CS-IDEAL as shown in FIG. 8 , and then _sends it to The gate of MOS M ₄ in Figure 6. Waveform converter 802 can be implemented, but not limited to, using the techniques disclosed in the '656 patent. Figure 9 shows a schematic diagram of the signal of the embodiment of Figure 8. It can be seen from Fig. 9 that the ideal current limit value V _CS-IDEAL increases with time at least for a period of time when the power switch in the nth cycle or the n+1th cycle is turned on.

Figure 10 is a diagram of an apparatus for generating an ideal current limit value V _CS-IDEAL in another embodiment of the present invention. The duty cycle detector 1002 receives the signal V _G that controls the control terminal of the power switch 402 in FIG. 4 to find a duty cycle D _{turn-on of the} current cycle. The converter 1004 converts the duty cycle D _turn-on into an ideal current limit value V _CS-IDEAL , which becomes the ideal current limit value V _CS-IDEAL to be used in the next cycle. For example, when the duty cycle D _{turn-on is} greater than 0.4, the converter 1004 sets the ideal current limit value V _CS-IDEAL to 0.85 volts, and when the duty cycle D _{turn-on is} less than 0.2, the ideal current limit value V _{CS- IDEAL is} set to 0.75 volts, and when the duty cycle D _{turn-on is} between 0.2 and 0.4, the ideal current limit value V _CS-IDEAL is linearly between 0.75 and 0.85. It can also be seen from Fig. 10 that the ideal current limit value V _CS-IDEAL is substantially a constant constant when the power switch is turned on, but its value will be updated and changed as the cycle changes.

The invention is not limited to application to a flyback power converter. The invention can Applied to any circuit that provides a current limit signal to accurately limit the current to an ideal desired value.

Although the present invention has been disclosed in the above preferred embodiments, the present invention is not intended to limit the invention, and any of the ordinary skill in the art to which the present invention pertains may be made without departing from the spirit and scope of the invention. And the scope of the present invention is defined by the scope of the appended claims.

100‧‧‧Power supply

102‧‧‧Power switch

104‧‧‧Transformers

106‧‧‧ Controller

R _CS ‧‧‧resistance

V _CS ‧‧‧cross pressure

V _LIMIT ‧‧‧ current limit signal

V _IN ‧‧‧Power supply voltage

202‧‧‧ Waveform Converter

204‧‧‧ oscillator

V _CS (V _INHIGH ) _{‧ ‧} cross pressure

V _CS (V _INLOW ) _{‧‧‧cross} pressure

400‧‧‧Power supply

402‧‧‧Power switch

404‧‧‧Transformer

410‧‧‧ comparator

412‧‧‧ Controller

414‧‧‧ diode

500‧‧‧Restriction signal generator

C _O ‧‧‧Rectified load capacitance

V _CS-MAX (n)‧‧‧ current peak

V _LIMIT (n)‧‧‧ reference value

V _CS-IDEAL ‧‧‧Ideal current limit value

dV _CS (n)‧‧‧ actual difference

dV _LIMIT (n)‧‧‧ update difference

Output signal V _P ‧‧‧

502‧‧‧Correction signal generator

504‧‧‧Restricted Signal Updater

V _LIMIT-next ‧‧‧correction signal

I ₁ I ₂ I ₃ I ₄ ‧‧‧ Current

M ₁₀ M ₂₀ M ₃₀ M ₄₀ ‧‧‧MOS

P _sample ‧‧‧peak sampler

V _G ‧‧‧ signal

M ₁ M ₂ M ₃ M ₄ ‧‧‧MOS

V _S ‧‧‧ signal

R ₁ R ₂ ‧‧‧resistance

M _S1 M _S2 ‧‧‧MOS

C ₁ C ₂ ‧‧‧ capacitor

V _CS-MIN ‧‧‧ lowest value

802‧‧‧ Waveform Converter

804‧‧‧ oscillator

1002‧‧‧Work cycle detector

D _turn-on ‧‧‧ work cycle

1004‧‧‧ converter

Figure 1 shows a conventional PWM power supply.

Figure 2 shows a conventional method of adjusting the current limit signal V _LIMIT .

Figure 3 shows the waveform with the current limit signal V _{LIMIT and} the waveforms of the two V _CS .

Figure 4 is a circuit diagram of a power supply circuit in accordance with an embodiment of the present invention.

Figure 5 is a schematic diagram of signals according to an embodiment of the present invention.

Figure 6 is an embodiment of the limit signal generator of Figure 4.

Fig. 7 is an embodiment of the limit signal updater in Fig. 6.

Figure 8 is a circuit diagram for generating an ideal current limit value V _CS-IDEAL .

Figure 9 is a signal diagram showing an embodiment of the circuit of Figure 8.

Figure 10 is a schematic diagram of another circuit used to generate the ideal current limit value V _CS-IDEAL .

Limit signal generator ‧‧500

Resistance ‧‧‧R ₁ R ₂

Correction signal generator ‧‧‧502

Limit signal updater ‧‧‧504

Correction signal ‧‧V _LIMIT-next

Current ‧‧‧I ₁ I ₂ I ₃ I ₄

MOS‧‧‧M _1o M ₂₀ M ₃₀ M ₄₀

Peak sampler ‧‧‧P _sample

Signal ‧‧‧V _G

MOS‧‧‧M ₁ M ₂ M ₃ M ₄

Current limit signal ‧‧V _LIMIT

Ideal current limit value ‧‧V _CS-IDEAL

Cross pressure ‧‧V _CS

Claims (14)

A current control method includes: turning on a switch in series with an energy transfer component of a power supply; providing a current limit signal and an ideal current limit value; and transmitting a second memory through a second capacitor Memorizing the current limit signal; detecting a current passing through the switch; when the current exceeds the current limit signal, turning off the switch; detecting the maximum value of the current; according to the current limit signal before the update, the maximum And the ideal current limit value, generating a correction signal; storing the correction signal through a first memory end of the first capacitor; and controlling the connection between the first memory end and the second memory end to utilize the correction signal Update the current limit signal. The current control method according to claim 1, wherein the corrected difference between the current limit signal and the correction signal before the update, and the actual difference between the maximum value and the ideal current limit value are A fixed proportional relationship. The current control method according to claim 1, wherein the current limiting signal before updating and the updated current limiting signal are The update difference between the two, and the actual difference between the maximum value and the ideal current limit value, is a fixed ratio k, and k is between 0 and 2. The current control method of claim 1, wherein the step of updating the current limit signal comprises: converting a difference between the maximum value and the ideal current limit value as a first difference signal; Multiplying the first difference signal by a certain value to generate a second difference signal; subtracting the second difference signal from the current limit signal before updating to generate the correction signal; and updating the current limit with the correction signal signal. The current control method of claim 1, further comprising: clamping the current limiting signal between the ideal current limit value and a lower limit value. A current control device includes: a current limiter coupled to a switch, the switch is coupled in series with an energy transfer component of a power supply, the current limiter detecting a current through the switch, and when When the current exceeds a current limit signal, the switch is turned off; and a limit signal generator is configured to provide the current limit signal, detect the maximum value of the current, and update the current value according to the maximum value and an ideal current limit value. a current limit signal, the limit signal generator comprising: a correction signal generator, according to the current limit before updating a signal, the maximum value and the ideal current limit value to generate a correction signal; and a limit signal updater to update the current limit signal with the correction signal, the limit signal updater comprising: a first capacitor having one a first memory end for storing the correction signal; and a second capacitor having a second memory end for memorizing the current limit signal; wherein the limit signal updater controls the first memory end and the second The memory is connected to update the current limit signal. The current control device of claim 6, wherein the limit signal generator updates the current limit signal according to an actual difference between the maximum value and the ideal current limit value. The current control device of claim 6, wherein an update difference between the current limit signal before updating and the updated current limit signal is between the maximum value and the ideal current limit value. The actual difference is a fixed ratio k, and k is between 0 and 2. The current control device of claim 6, wherein the correction signal generator comprises: a peak sampler for detecting a maximum value of the current. A current control method includes: providing an ideal current limit value; turning on a switch in a cycle, the switch and a power supply An energy transfer element is connected in series; detecting when the switch is turned on, passing a current of the switch; detecting a maximum value of the current during the period; providing a current limit signal; and according to the current limit signal before updating The maximum value and the ideal current limit value generate a correction signal; the first memory terminal of the first capacitor memorizes the correction signal; and the second memory terminal of the second capacitor memorizes the current limit signal When the current exceeds the current limit signal, turning off the switch; and controlling the connection between the first memory end and the second memory end to update the current limit signal by using the correction signal as a subsequent cycle The current limiting signal is used; wherein the current limiting signal is a certain value when the switch is turned on during the period. The current control method according to claim 10, wherein the ideal current limit value is a certain value when the switch is turned on during the period. The current control method of claim 10, wherein the ideal current limit value increases over time during at least a period of time when the switch is turned on during the period. The current control method described in claim 10, further comprising There is: providing a triangular wave signal; and generating the ideal current limit value according to the triangular wave signal. The current control method of claim 10, wherein the duty cycle of the switch in the cycle is used to determine the ideal current limit value for the subsequent switching cycle.