TWI382385B - A current-type pixel circuit and a display device including the current-type pixel circuit - Google Patents

Description

Current mode pixel circuit and display device including the same

The present invention relates to a pixel circuit and a display device including the same, and more particularly to a current pixel circuit and a display device including the current pixel circuit.

Referring to FIG. 1, a display device includes a driving circuit 8 and N × M pixel circuits 7 arranged in an N × M matrix.

For the pixel circuit 7 of the nth column, the driving circuit 8 outputs a scan signal V _SEL (n) through a scan line, and outputs a control signal V _CTL (n) through a control line, and the control signal V _CTL ( n) is essentially an inverted signal of the scan signal V _SEL (n). For the pixel circuit 7 of the mth row, the driving circuit 8 outputs a driving current I _DATA (m) through a data line. Where n =1... N and m =1... M . The driving circuit 8 supplies an operating voltage VDD and a ground voltage GND to the pixel circuits 7.

Referring to FIG. 2, each pixel circuit 7 includes an Organic Light-Emitting Diode (OLED) D, a capacitor C, and four P-type transistors M1, M2, M3, and M4.

The N scan signals V _SEL (1) to V _SEL (N), the N control signals V _CTL (1) to V _CTL (N) and the M drive current I _DATA (1) to I _DATA outputted by the drive circuit 8 (M), the OLED D of each pixel circuit 7 can be driven to exhibit an essential color of different luminances of illumination. The display device can combine the colors appearing by the OLED D of all the pixel circuits 7 as the image content.

For the pixel circuit 7 in the mth row of the nth column, a first end of the transistor M1 and a first end of the capacitor C receive the operating voltage VDD, and the cathode of the OLED D receives the ground voltage GND. A second end of the transistor M3 receives the drive current I _DATA (m). A control terminal of the transistor M4 receives the control signal V _CTL (n), and a control terminal of the transistor M2 and a control terminal of the transistor M3 respectively receive the scan signal V _SEL (n). Since the control signal V _CTL (n) is substantially an inverted signal of the scan signal V _SEL (n), a second end of the transistor M1 can be electrically connected to a control terminal of the transistor M1. Switching between an anode connected to the OLED D.

Referring to FIG. 2 and FIG. 3, during the writing period P1, the control signal V _CTL (n) is in a high potential state, and the scan signal V _SEL (n) is in a low potential state to make the second phase of the transistor M1. The terminal is electrically connected to the control terminal of the transistor M1. At this time, the transistor M2 is turned on and the transistor M3 is turned on, and the transistor M4 is not turned on, and the capacitor C is charged through the transistors M1 and M2 by the current I _D1 -I _DATA (m), where I _D1 is Current flowing through the second end of the transistor M1.

Until a steady state of charge, the second terminal of the capacitor C voltage V _C of the relation to the driving current I _DATA (m) may be represented by Equation (1).

Wherein V _{th 1} is a threshold voltage of the transistor M1, and , μ _p is the carrier field-effect mobility, W is the channel width, L is the channel length, and C _OX is the unit capacitance of the gate oxide layer.

During the illumination period P2, the control signal V _CTL (n) is in a low potential state, and the scan signal V _SEL (n) is in a high potential state, so that the second end of the transistor M1 is electrically connected to the anode of the OLED D . At this time, the transistor M2 and the transistor M3 are not turned on, and the transistor M4 is turned on.

The capacitance C of the second terminal voltage V _C so that the transistor M1 is turned on, and through such transistors M1, M4, the OLED D may receive a current equal to the driving current I _DATA (m) to display current I _OLED To reveal the essential color of the luminance of the light corresponding to the driving current I _DATA (m). Therefore, by adjusting the driving currents I _DATA (1) to I _DATA (M), the driving circuit 8 can control the luminance of the OLED D of each of the pixel circuits 7.

Therefore, if the OLED D of the pixel circuit 7 located in the mth row ( n = 1... N and m = 1... M ) of the nth column is adjusted to a lower order luminance, the driving circuit 8 A drive current I _DATA (m) having a relatively small current value needs to be sent. In the application of a larger-sized display device, as the number of scanning lines increases, the driving current of a smaller current value will lengthen the charging time of the parasitic capacitance C of the data line, and the problem is more serious.

Accordingly, it is an object of the present invention to provide a current type pixel circuit capable of shortening pixel charging time and a display device including the current type pixel circuit.

Therefore, the current mode pixel circuit of the present invention is adapted to receive a first voltage, a scan signal, a control signal, a driving current, and a time varying signal, the current pixel circuit comprising a light emitting diode, a capacitor, and a the first A transistor and a switching unit.

The light emitting diode includes a first pole and a second pole. The capacitor includes a first end and a second end that receive the control signal. The first transistor includes a first end, a second end, and a control end. The first end of the first transistor receives the first voltage, and the control end of the first transistor is electrically connected to the second end of the capacitor.

The switching unit is controlled by the scan signal to switch the second end of the first transistor between a writing position and a lighting position.

In the write position, the control signal is in a write potential state, and the switching unit electrically connects the second end of the first transistor to the control end of the first transistor, and the capacitor passes through the first transistor to flow The current through the second end of the first transistor is charged to the difference in the drive current.

In the light emitting position, the control signal is in a light emitting potential state, and the switching unit electrically connects the second end of the first transistor to the first pole of the light emitting diode, and the voltage of the second end of the capacitor makes the first The transistor is turned on to cause the light emitting diode to emit light.

The switching unit includes a second transistor and a third transistor, a first end of the second transistor is electrically connected to the second end of the capacitor, and a second end of the first transistor is electrically connected to the second a second end of the transistor, a first end of the third transistor and a first pole of the LED, and a second pole of the LED receives the time-varying signal, and the third A second end of the crystal receives the drive current.

The display device of the present invention comprises a driving circuit and a plurality of the above-mentioned current-type pixel circuits, wherein the current-type pixel circuits are arranged in a matrix, for each a current mode pixel circuit of the column, the driving circuit outputs the scan signal and the control signal, the driving circuit outputs the driving current for each line of the current type pixel circuit, and the driving circuit outputs the time varying signal to each The second pole of the light-emitting diode of the current mode pixel circuit.

The above and other technical contents, features and advantages of the present invention will be apparent from the following detailed description of the preferred embodiments.

Before the present invention is described in detail, it is noted that in the following description, similar elements are denoted by the same reference numerals.

First preferred embodiment

Referring to Figure 4, a first preferred embodiment of the display device of the present invention comprises a driver circuit 2 and N x M current mode pixel circuits 1 arranged in an N x M matrix.

The driving circuit 2 includes a scan driver 21, a data driver 22 and a voltage driver 23.

For the current-type pixel circuit 1 of the nth column, the scan driver 21 outputs a scan signal V _SCAN 1(n) through a scan line. For the current mode pixel circuit 1 of the mth row, the data driver 22 outputs a drive current I _DATA (m) through a data line. Where n =1... N and m =1... M . The voltage driver 23 outputs a first voltage, a second voltage, a third voltage, and a modulation voltage VEE to each of the current mode pixel circuits 1. In the preferred embodiment, the first voltage is an operating voltage VDD, the second voltage is a ground voltage GND, and the third voltage is a low potential voltage V _CATH .

Referring to FIG. 5, each current pixel circuit 1 includes an OLED D and a The capacitor C, a first transistor T1 and a switching unit 11. The OLED D has a first pole and a second pole, and in the preferred embodiment, the first pole is an anode and the second pole is a cathode. The switching unit 11 has a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6. The first, fourth, and sixth transistors T1, T4, and T6 are P-type transistors, and the second, third, and fifth transistors T2, T3, and T5 are N-type transistors.

A first end of the capacitor C is electrically connected to a second end of the fifth transistor T5 and a second end of the sixth transistor T6, and a second end of the capacitor C is electrically connected to the second transistor. A first end of T2 and a control end of the first transistor T1. A second end of the first transistor T1 is electrically connected to a second end of the second transistor T2, a first end of the third transistor T3, and a first end of the fourth transistor T4. A second end of the fourth transistor T4 is electrically connected to the anode of the OLED D.

A first end of the first transistor T1 receives the operating voltage VDD, and a first end of the sixth transistor T6 receives the modulated voltage VEE. A first end of the fifth transistor T5 receives the ground voltage GND, and a cathode of the OLED D receives the low potential voltage V _CATH .

For the current mode pixel circuit 1 located in the mth row of the nth column, a second end of the third transistor T3 receives the drive current I _DATA (m). And the switching unit 11 receives the scan signal V _SCAN 1(n) such that the first end of the capacitor C and the second end of the first transistor T1 are in a writing position (as shown in FIG. 7 ) and a lighting position (eg, Switch between Figure 8). The switching unit 11 receives the scan signal V _SCAN 1(n) via a control terminal of the second, third, fourth, fifth, and sixth transistors T2, T3, T4, T5, and T6, respectively.

Referring to FIG. 5 and FIG. 6, during the writing period P1, the scan signal V _SCAN 1(n) is in a high potential state, so that the first end of the capacitor C and the second end of the first transistor T1 are written. The in-position, that is, the first end of the capacitor C receives the ground voltage GND and the second end of the first transistor T1 is electrically connected to the control end of the first transistor T1 (as shown in FIG. 7). At this time, the second, third, and fifth transistors T2, T3, and T5 are turned on, and the fourth and sixth transistors T4 and T6 are not turned on.

Via the first and second transistors T1, T2, the capacitor C is charged with a current I _{D1 -} I _DATA (m), where I _D1 is the current flowing through the second end of the first transistor T1. Until a steady state of charge, the second terminal of the capacitor C voltage V _C of the relation to the driving current I _DATA (m) may Equation (2), and the voltage across the capacitor C is equal to the capacitance of C The voltage V _{C at the} second end.

Wherein V _{th 1} is a threshold voltage value of the first transistor T1, and , μ _p is the carrier field mobility, W is the channel width, L is the channel length, and C _OX is the unit capacitance of the gate oxide layer.

During the illumination period P2, the scan signal V _SCAN 1(n) is in a low potential state, so that the first end of the capacitor C and the second end of the first transistor T1 are in a light-emitting position, that is, the capacitance C The first end receives the modulation voltage VEE and the second end of the first transistor T1 is electrically connected to the anode of the OLED D (as shown in FIG. 8). At this time, the second, third, and fifth transistors T2, T3, and T5 are not turned on, and the fourth and sixth transistors T4 and T6 and the OLED D are turned on. Since the voltage across the capacitor C is V _C , the voltage at the control terminal of the first transistor T1 is V _C + VEE.

The voltage of the control terminal of the first transistor T1 turns on the first transistor T1, so that the OLED D can receive a current value as shown in the equation (3) through the first and fourth transistors T1 and T4. The current I _OLED is displayed to reveal the corresponding luminance of the light.

It can be seen from equation (3) that when the voltage value of VEE is greater than zero, the display current I _{OLED is} smaller than the drive current I _DATA (m). Therefore, even if the relevant OLED D located in the mth row of the nth column needs to exhibit a lower order luminance during the illumination period P2, the data driver 22 is allowed to send the driving current I _DATA (m) having a larger current value. And adjusting the modulation voltage VEE to achieve the desired brightness.

At the time of writing the period P1, also because the data driver 22 can transfer a large driving current I _DATA (m), the charging speed of the associated capacitor C is accelerated.

Therefore, when the luminance of the OLED D is weakened, the capacitor C is not made. The charging time is elongated, and the reaction time of the display device is not slowed down.

Referring to FIG. 9, the operation principle of the display device includes the following steps:

Step 31: A high-potential scan signal V _SCAN 1(n) is sent from the scan driver 21 to perform a scanning operation on the n-th column of the current-type pixel circuit 1 while the remaining scan signals are low.

Step 32: The scanned current pixel circuits 1 of the nth column are in the writing period P1, and respectively receive the driving currents I _DATA (1)...I _DATA (M) sent by the data driver 22, To charge the relevant capacitor C.

At the same time, the remaining unscanned current mode pixel circuits 1 are in the light emission period P2 because they receive the low potential scanning signal. However, since the relevant capacitor C is not recharged, the corresponding OLED D exhibits the brightness of the previous picture state.

Step 33: If the current mode pixel circuit 1 of the next column is to be scanned, the process jumps back to step 31, and if not, the process ends.

Second preferred embodiment

Referring to Figure 10, a second preferred embodiment of the display device of the present invention comprises a driver circuit 2 and N x M current mode pixel circuits 1 arranged in an N x M matrix.

The driving circuit 2 includes a scan driver 21, a data driver 22 and a voltage driver 23.

For the current-type pixel circuit 1 of the nth column, the scan driver 21 outputs a scan signal V _SCAN 1(n) through a scan line, and outputs a control signal V _CMD (n) through a control line. For the current mode pixel circuit 1 of the mth row, the data driver 22 outputs a drive current I _DATA (m) through a data line. Where n =1... N and m =1... M . The voltage driver 23 outputs a first voltage and a third voltage to each of the current mode pixel circuits 1. In the preferred embodiment, the first voltage is an operating voltage VDD and the third voltage is a low potential voltage V _CATH .

Referring to FIG. 11, each current pixel circuit 1 includes an OLED D, a capacitor C, a first transistor T1, and a switching unit 11. The OLED D has a first pole and a second pole, and in the preferred embodiment, the first pole is an anode and the second pole is a cathode. The switching unit 11 has a second transistor T2, a third transistor T3 and a fourth transistor T4. The first and fourth transistors T1 and T4 are P-type transistors, and the second and third transistors T2 and T3 are N-type transistors.

The electrical connection relationship between the first, second, third, and fourth transistors T1, T2, T3, and T4 and the OLED D is similar to that of the first preferred embodiment, and details are not described herein. A first end of the second transistor T2 is electrically connected to a second end of the capacitor C, and a cathode of the OLED D receives the low potential voltage V _CATH .

For the current mode pixel circuit 1 located in the mth row of the nth column, a first end of the capacitor C receives a control signal V _CMD (n), and a second end of the third transistor T3 receives a drive. Current I _DATA (m). And the switching unit 11 receives the scan signal V _SCAN 1(n) to switch the second end of the first transistor T1 between the writing position and the lighting position. The switching unit 11 receives the scan signal V _SCAN 1(n) by a control terminal of the second, third, and fourth transistors T2, T3, and T4, respectively.

Referring to FIG. 11 and FIG. 12, during the writing period P1, the scan signal V _SCAN 1(n) is in a high potential state, and the control signal V _CMD (n) is in a write potential state (in the preferred embodiment, The write potential state is a low potential state), so that the second end of the first transistor T1 is in a writing position, that is, the second end of the first transistor T1 is electrically connected to the control of the first transistor T1. end. At this time, the second and third transistors T2, T3 are turned on and the fourth transistor T4 is not turned on.

Via the first and second transistors T1, T2, the capacitor C is charged with a current I _{D1 -} I _DATA (m), where I _D1 is the current flowing through the second end of the first transistor T1. Charging up until a steady state, the second terminal of the capacitor C voltage V _C of the relation to the driving current I _DATA (m) as shown in equation (2), and the voltage across the capacitor C is equal to the capacitance C The voltage V _{C at} the second end is different from the voltage of the low potential control signal V _CMD (n).

During the illumination period P2, the scan signal V _SCAN 1(n) is in a low potential state, and the control signal V _CMD (n) is in a light-emitting potential state (in the preferred embodiment, the light-emitting potential state is a high-potential state) So that the second end of the first transistor T1 is in the light emitting position, that is, the second end of the first transistor T1 is electrically connected to the anode of the OLED D. At this time, the second and third transistors T2 and T3 are not turned on, and the fourth transistor T4 is turned on. The voltage of the control terminal of the first transistor T1 is _{V C + △ V CMD (n} ), wherein △ V _CMD (n) for the control signal V _CMD (n) of the difference between the high and low potential.

The voltage of the control terminal of the first transistor T1 turns on the first transistor T1, so that the OLED D can receive a current value as shown in equation (4) through the first and fourth transistors T1 and T4. The current I _OLED is displayed to reveal the corresponding luminance of the light.

(4) can be seen from the equation, when the voltage value △ V _CMD (n) is greater than zero, the current I _OLED display is less than the driving current I _DATA (m). Thus, when the light emission period P2, also having the premise of the driving current higher current value I _DATA (m), and adjusting the control signal V _CMD (n) of high and low potential difference △ V _CMD (n), so that the relevant OLED D exhibits lower order brightness. At the time of writing the period P1, also because the data driver 22 can transfer a large driving current I _DATA (m), the charging speed of the associated capacitor C is accelerated.

Third preferred embodiment

Referring to FIG. 13 and FIG. 14, a third preferred embodiment of the display device of the present invention is different from the second preferred embodiment in that the second and third transistors T2 and T3 of each switching unit 11 are P-type. Crystal. In addition, the current formula for the n-th column pixel circuit 1, the scanning driver 21 through an output scan line in addition to a scan signal V _SCAN 1 (n), also outputs a scan signal V _SCAN 2 (n). The scan signal V _SCAN 2(n) is a signal that is non-overlapped on the scan signal V _SCAN 1(n). In the preferred embodiment, the scan signal V _SCAN 2(n) is substantially an inverted signal of the scan signal V _SCAN 1(n), and is not limited thereto.

The scan signal V _SCAN 1(n) and the scan signal V _SCAN 2(n) exhibit a non-overlapping relationship with each other, that is, the two are not in a high potential state at the same time.

For the current mode pixel circuit 1 located in the mth row ( n = 1... N and m = 1... M ) on the nth column, the control terminal of the fourth transistor T4 receives the scan signal V _SCAN 1(n), and the control terminal of the second transistor T2 and the control terminal of the third transistor T3 receive the scan signal V _SCAN 2(n), respectively.

The operation of the writing period P1 and the lighting period P2 of the third preferred embodiment is similar to that of the second preferred embodiment, and details are not described herein.

Fourth preferred embodiment

Referring to FIG. 15, a current mode pixel circuit 1 of a fourth preferred embodiment of the display device of the present invention is different from the second preferred embodiment in that the switching unit 11 of each current pixel circuit 1 omits the fourth The transistor T4, and the cathode of the OLED D receives a time varying signal from the voltage driver 23. In the preferred embodiment, the time varying signal is a control signal V _CATH '.

For the current mode pixel circuit 1 located at the mth row ( n = 1... N and m = 1... M ) on the nth column, the switching unit 11 receives the scan signal V _SCAN 1(n) The control signal V _CATH ' is matched to switch the second end of the first transistor T1 between the writing position and the lighting position.

Referring to FIG. 15 and FIG. 16, during the writing period P1, the scan signal V _SCAN 1(n) and the control signal V _CATH ' are in a high potential state, and the control signal V _CMD (n) is in a write potential state ( In the preferred embodiment, the write potential state is a low potential state), so that the second end of the first transistor T1 is in a writing position, that is, the second end of the first transistor T1 is electrically connected to the second transistor The control terminal of the first transistor T1. At this time, the second and third transistors T2 and T3 are turned on, and the OLED D is not turned on.

Via the first and second transistors T1, T2, the capacitor C is charged with a current I _{D1 -} I _DATA (m), where I _D1 is the current flowing through the second end of the first transistor T1. Charging up until a steady state, the second terminal of the capacitor C voltage V _C of the relation to the driving current I _DATA (m) as shown in equation (2), and the voltage across the capacitor C is equal to the capacitance C The voltage V _{C at} the second end is different from the voltage of the low potential control signal V _CMD (n).

During the illumination period P2, the scan signal V _SCAN 1(n) and the control signal V _CATH ' are in a low potential state, and the control signal V _CMD (n) is a light-emitting potential state (in the preferred embodiment, the illumination The potential state is a high potential state), so that the second end of the first transistor T1 is in a light emitting position, that is, the second end of the first transistor T1 is electrically connected to the anode of the OLED D. At this time, the second and third transistors T2, T3 are not turned on, and the OLED D is turned on. The voltage of the control terminal of the first transistor T1 is _{V C + △ V CMD (n} ), wherein △ V _CMD (n) for the control signal V _CMD (n) of the difference between the high and low potential.

The voltage of the control terminal of the first transistor T1 turns on the first transistor T1, so that the OLED D can receive a display current I _OLED having a current value as shown in the equation (4) through the first transistor T1. .

Fifth preferred embodiment

Referring to FIG. 17, a current mode pixel circuit 1 of a fifth preferred embodiment of the display device of the present invention is different from the third preferred embodiment in that the switching unit 11 of each current pixel circuit 1 omits the fourth The transistor T4, and the cathode of the OLED D receives a time varying signal from the voltage driver 23. In the preferred embodiment, the time varying signal is a control signal V _CATH '. Further, for the current-based pixel circuit 1 of the nth column, the scan driver 21 outputs only one scan signal V _SCAN 2(n) through a scan line.

For the current mode pixel circuit 1 located at the mth row ( n = 1... N and m = 1... M ) on the nth column, the control terminal of the second transistor T2 and the third transistor The control terminal of the crystal T3 receives the scan signal V _SCAN 2(n), respectively.

The operation of the fifth preferred embodiment in the writing period P1 and the lighting period P2 is similar to that of the fourth preferred embodiment, and details are not described herein.

Sixth preferred embodiment

Referring to Figure 18, a sixth preferred embodiment of the display device of the present invention comprises a driver circuit 2 and N x M current mode pixel circuits 1 arranged in an N x M matrix.

The driving circuit 2 includes a scan driver 21, a data driver 22 and a voltage driver 23.

Type pixel circuit for current n-th column 1, the scan driver 21 through an output scan line in addition to a scan signal V _SCAN 1 (n), also outputs a scan signal V _SCAN 2 (n). The scan signal V _SCAN 2(n) is a signal that does not overlap the scan signal V _SCAN 1(n). In the preferred embodiment, the scan signal V _SCAN 2(n) is substantially an inverted signal of the scan signal V _SCAN 1(n), and is not limited thereto. The data driver 22 and the voltage driver 23 are similar to the first preferred embodiment in the case of the current-based pixel circuit 1, and therefore will not be described herein.

Referring to FIG. 19, each current pixel circuit 1 includes an OLED D, a capacitor C, a first transistor T1, and a switching unit 11. The OLED D has a first pole and a second pole, and in the preferred embodiment, the first pole is an anode and the second pole is a cathode. The switching unit 11 has a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. The transistors T1, T2, T3, T4, T5, T6, and T7 are all P-type transistors.

A first end of the capacitor C is electrically connected to a second end of the fifth transistor T5 The terminal is electrically connected to a second end of the sixth transistor T6, and a second end of the capacitor C is electrically connected to a first end of the seventh transistor T7 and a control end of the first transistor T1. A second end of the first transistor T1 is electrically connected to a second end of the second transistor T2, a first end of the third transistor T3, and a first end of the fourth transistor T4. A second end of the seventh transistor T7 is electrically connected to a first end of the second transistor T2, and a second end of the fourth transistor T4 is electrically connected to the anode of the OLED D.

A first end of the first transistor T1 receives the operating voltage VDD, and a first end of the sixth transistor T6 receives the modulated voltage VEE. A first end of the fifth transistor T5 receives the ground voltage GND, and a cathode of the OLED D receives the low potential voltage V _CATH .

For the current mode pixel circuit 1 located in the mth row of the nth column, a second end of the third transistor T3 receives the driving current I _DATA (m), and the fourth and sixth transistors T4, A control terminal of T6 receives the scan signal V _SCAN 2(n), respectively. The switching unit 11 receives the scan signal V _SCAN 1(n) such that the first end of the capacitor C and the second end of the first transistor T1 are switched between a writing position and a lighting position. The switching unit 11 receives the scan signal V _SCAN 1(n) via a control terminal of the second, third, fifth, and seventh transistors T2, T3, T5, and T7, respectively.

Referring to FIG. 19 and FIG. 20, during the writing period P1, the scan signal V _SCAN 1(n) is in a low potential state and the scan signal V _SCAN 2(n) is in a high potential state, so that the capacitor C is first. The second end of the first transistor T1 is in the writing position, that is, the first end of the capacitor C receives the ground voltage GND and the second end of the first transistor T1 is electrically connected to the first transistor T1. The console. At this time, the second, third, fifth, and seventh transistors T2, T3, T5, and T7 are turned on, and the fourth and sixth transistors T4 and T6 are not turned on.

The capacitor C is charged by the current I _D1 -I _DATA (m) via the first, second and seventh transistors T1, T2, T7, wherein I _D1 is the current flowing through the second end of the first transistor T1 . Charging up until a steady state, the second terminal of the capacitor C voltage V _C of the relation to the driving current I _DATA (m) as in equation (2), and the voltage across the capacitor C is equal to the capacitance C The voltage V _{C at} the second end.

During the illumination period P2, the scan signal V _SCAN 1(n) is in a high potential state and the scan signal V _SCAN 2(n) is in a low potential state, so that the first end of the capacitor C and the first transistor T1 The second end of the capacitor C receives the modulation voltage VEE and the second end of the first transistor T1 is electrically connected to the anode of the OLED D. At this time, the second, third, fifth, and seventh transistors T2, T3, T5, and T7 are not turned on, and the fourth and sixth transistors T4 and T6 and the OLED D are turned on. Since the voltage across the capacitor C is V _C , the voltage at the control terminal of the first transistor T1 is V _C + VEE.

The voltage of the control terminal of the first transistor T1 turns on the first transistor T1, so that the OLED D can receive a current value as shown in the equation (3) through the first and fourth transistors T1 and T4. The current I _OLED is displayed to reveal the corresponding luminance of the light.

When the voltage value of VEE is greater than zero, the display current I _{OLED is} smaller than the drive current I _DATA (m). Therefore, the data driver 22 is allowed to send the driving current I _DATA (m) having a larger current value during the lighting period P2, and the modulation voltage VEE is adjusted to achieve the desired brightness of the OLED D.

At the time of writing the period P1, also because the data driver 22 can transfer a large driving current I _DATA (m), the charging speed of the associated capacitor C is accelerated.

Seventh preferred embodiment

Referring to FIG. 21, a current mode pixel circuit 1 of a seventh preferred embodiment of the display device of the present invention is different from the sixth preferred embodiment in the second, third, fourth, and fourth portions of each switching unit 11. 5. The sixth and seventh transistors T2, T3, T4, T5, T6, and T7 are N-type transistors. Further, for the current-based pixel circuit 1 of the nth column, the scan signal V _SCAN 1(n) and the scan signal V _SCAN 2(n) are substantially the scan signal V _SCAN 1 of the sixth preferred embodiment, respectively. (n) and an inverted signal of the scan signal V _SCAN 2(n).

The operation of the writing period P1 and the lighting period P2 in the seventh preferred embodiment is similar to that of the sixth preferred embodiment, and details are not described herein.

It is to be noted that in the sixth and seventh preferred embodiments, the second and seventh transistors T2, T7 are connected in series in order to reduce leakage current. Since the second and seventh transistors T2 and T7 have the same conduction state, they can theoretically be combined into one transistor.

Eighth preferred embodiment

Referring to FIG. 22, a current mode pixel circuit 1 of an eighth preferred embodiment of the display device of the present invention is different from the first preferred embodiment in the first, fourth and sixth transistors T1, T4 and T6. It is an N-type transistor, and the second, third, and fifth transistors T2, T3, and T5 are P-type transistors. The OLED D has a first pole and a second pole, and in the preferred embodiment, the first pole is A cathode and the second pole is an anode.

In addition, the voltage driver 23 outputs a first voltage, a second voltage, a third voltage, an operating voltage VDD, and a modulation voltage VEE to each current pixel circuit 1. In the preferred embodiment, the first voltage is a ground voltage GND, the second voltage is a ground voltage GND, and the third voltage is a high potential voltage V _ANODE . A first end of the first transistor T1 receives the ground voltage GND, a first end of the fifth transistor T5 receives the ground voltage GND, and a second end of the fourth transistor T1 receives the OLED D a cathode, and the anode of the OLED D receives the high potential voltage V _ANODE . A second terminal of the third transistor T3 receives the driving current I _DATA (m) and receives the operating voltage VDD. For the current-type pixel circuit 1 of the nth column, the scan driver 21 outputs only one scan signal V _SCAN 2(n) through a scan line.

For the current mode pixel circuit 1 located on the mth row ( n =1... N and m =1... M ) on the nth column, the second, third, fourth, fifth, and The control terminals of the six transistors T2, T3, T4, T5, and T6 receive the scan signal V _SCAN 2(n), respectively.

The operation of the eighth preferred embodiment in the writing period P1 and the lighting period P2 is similar to that of the first preferred embodiment, and details are not described herein.

Ninth preferred embodiment

Referring to FIG. 23, a galvanic pixel circuit 1 of a ninth preferred embodiment of the display device of the present invention is different from the eighth preferred embodiment in that the fourth and sixth transistors T4 and T6 are P-type transistors. . In addition, the current formula for the n-th column pixel circuit 1, the scanning driver 21 through an output scan line in addition to a scan signal V _SCAN 2 (n), also outputs a scan signal V _SCAN 1 (n). The scan signal V _SCAN 2(n) is a signal that does not overlap the scan signal V _SCAN 1(n). In the preferred embodiment, the scan signal V _SCAN 2(n) is substantially an inverted signal of the scan signal V _SCAN 1(n), and is not limited thereto.

For the current mode pixel circuit 1 located at the mth row ( n = 1... N and m = 1... M ) on the nth column, the second, third and fifth transistors T2, T3 The control terminal of T5 receives the scan signal V _SCAN 2(n), respectively, and the control terminals of the fourth and sixth transistors T4, T6 receive the scan signal V _SCAN 1(n), respectively.

The operation of the writing period P1 and the lighting period P2 in the ninth preferred embodiment is similar to that of the eighth preferred embodiment, and details are not described herein.

It is also worth noting that the second, third, fourth, fifth and sixth transistors T2, T3, T4, T5, T6 may all be N-type transistors. And for the current mode pixel circuit 1 located in the mth row ( n = 1... N and m = 1... M ) on the nth column, the second, third, and fifth transistors T2 The control terminals of T3 and T5 respectively receive the scan signal V _SCAN 1(n), and the control terminals of the fourth and sixth transistors T4 and T6 respectively receive the scan signal V _SCAN 2(n), as shown in FIG.

Tenth preferred embodiment

Referring to FIG. 25, a current mode pixel circuit 1 of a tenth preferred embodiment of the display device of the present invention is different from the second preferred embodiment in that the first and fourth transistors T1 and T4 are N-type transistors. The second and third transistors T2, T3 are P-type transistors. The OLED D has a first pole and a second pole, and in the preferred embodiment, the first pole is a cathode and the second pole is an anode.

In addition, the voltage driver 23 outputs a first voltage, a second voltage, and a third voltage to each of the current mode pixel circuits 1. In the preferred embodiment, the first voltage is a ground voltage GND, the second voltage is an operating voltage VDD, and the third voltage is a high potential voltage V _ANODE . A first end of the first transistor T1 receives the ground voltage GND, a second end of the fourth transistor T1 receives the cathode of the OLED D, and an anode of the OLED D receives the high potential voltage V _ANODE . A second end of the third transistor T3 receives the driving current I _DATA (m) and receives the operating voltage VDD. For the current-based pixel circuit 1 of the nth column, the scan driver 21 outputs only one scan signal V _SCAN 2(n) through a scan line.

For the current mode pixel circuit 1 located on the mth row ( n = 1... N and m = 1... M ) on the nth column, the second, third and fourth transistors T2, T3 The control terminal of T4 receives the scan signal V _SCAN 2(n), respectively.

The operation of the writing period P1 and the lighting period P2 in the tenth preferred embodiment is similar to that of the second preferred embodiment, and details are not described herein.

Eleventh preferred embodiment

Referring to FIG. 26, a current-based pixel circuit 1 of an eleventh preferred embodiment of the display device of the present invention is different from the tenth preferred embodiment in that the second and third transistors T2 and T3 are N-type. Crystal. In addition, the current formula for the n-th column pixel circuit 1, the scanning driver 21 through an output scan line in addition to a scan signal V _SCAN 2 (n), also outputs a scan signal V _SCAN 1 (n). The scan signal V _SCAN 2(n) is a signal that does not overlap the scan signal V _SCAN 1(n). In the preferred embodiment, the scan signal V _SCAN 2(n) is substantially an inverted signal of the scan signal V _SCAN 1(n), and is not limited thereto.

For the current mode pixel circuit 1 located in the mth row ( n = 1... N and m = 1... M ) on the nth column, the control terminal of the fourth transistor T4 receives the scan signal V _SCAN 2(n), and the control terminals of the second and third transistors T2, T3 respectively receive the scan signal V _SCAN 1(n).

The operation of the writing period P1 and the lighting period P2 in the eleventh preferred embodiment is similar to that of the tenth preferred embodiment, and details are not described herein.

It should be noted that the second, third, and fourth transistors T2, T3, and T4 may all be P-type transistors. And for the current mode pixel circuit 1 located in the mth row ( n =1... N and m =1... M ) on the nth column, the control terminal of the fourth transistor T4 receives the scan signal V _SCAN 1 (n), and the control terminals of the second and third transistors T2, T3 respectively receive the scan signal V _SCAN 2 (n), as shown in FIG.

Twelfth preferred embodiment

Referring to FIG. 28, a galvanic pixel circuit 1 of a twelfth preferred embodiment of the display device of the present invention is different from the fifth preferred embodiment in the first, second and third transistors T1 and T2. T3 is an N-type transistor. The OLED D has a first pole and a second pole, and in the preferred embodiment, the first pole is a cathode and the second pole is an anode.

In addition, the voltage driver 23 outputs a first voltage, a second voltage, and a time-varying signal to each of the current mode pixel circuits 1. In the preferred embodiment, the first voltage is a ground voltage GND, the second voltage is an operating voltage GND, and the time varying signal is a control signal V _ANODE '. A first end of the first transistor T1 receives the ground voltage GND, a second end of the first transistor T1 receives the cathode of the OLED D, and an anode of the OLED D receives the control signal V _ANODE '. A second end of the third transistor T3 receives the driving current I _DATA (m) and receives the operating voltage VDD. Further, for the current-based pixel circuit 1 of the nth column, the scan driver 21 outputs only one scan signal V _SCAN 1(n) through a scan line.

For the current mode pixel circuit 1 located on the mth row ( n = 1... N and m = 1... M ) on the nth column, the control terminals of the second and third transistors T2, T3 The scan signal V _SCAN 1(n) is received separately.

The operation of the writing period P1 and the lighting period P2 in the twelfth preferred embodiment is similar to that of the fifth preferred embodiment, and details are not described herein.

It is also worth noting that the second and third transistors T2 and T3 may both be P-type transistors. And for the current-type pixel circuit 1 of the nth column, the scan driver 21 outputs only one scan signal V _SCAN 2(n) through a scan line. For the current mode pixel circuit 1 located on the mth row ( n = 1... N and m = 1... M ) on the nth column, the control terminals of the second and third transistors T2, T3 The scan signal V _SCAN 2(n) is received separately, as shown in FIG.

It is also worth noting that the current mode pixel circuit 1 in the above embodiment can be independent of the display device.

In summary, the current mode pixel circuit of the present invention and the display device including the current type pixel circuit use the larger driving current I _DATA (m) to charge the relevant capacitor C during the writing period P1, so that the effective shortening can be effectively shortened. The charging time, which in turn accelerates the reaction time of the display device. And can directly adjust the modulation voltage VEE or the control signal V _CMD (n) of high and low potential difference △ V _CMD (n), so that the relevant OLED D present an appropriate emission luminance upon light emission period P2, it can really achieve the present invention purpose.

However, the above is only the preferred embodiment of the present invention, when not The scope of the invention is to be construed as being limited by the scope of the invention and the scope of the invention.

1‧‧‧Current pixel circuit

11‧‧‧Switch unit

2‧‧‧Drive circuit

21‧‧‧ scan driver

22‧‧‧Data Drive

23‧‧‧Voltage Driver

C‧‧‧ capacitor

D‧‧‧Organic Luminescent Diodes

T1‧‧‧first transistor

T2‧‧‧second transistor

T3‧‧‧ third transistor

T4‧‧‧ fourth transistor

T5‧‧‧ fifth transistor

T6‧‧‧ sixth transistor

T7‧‧‧ seventh transistor

P1‧‧‧ write cycle

P2‧‧‧Lighting cycle

VDD‧‧‧ operating voltage

VEE‧‧‧ modulated voltage

GND‧‧‧ Grounding voltage

I _OLED ‧‧‧ display current

I _DATA (m)‧‧‧ drive current

V _CMD (n)‧‧‧ control signal

V _SCAN 1(n)‧‧‧ scan signal

V _SCAN 2(n)‧‧‧ scan signal

V _CATH ‧‧‧low potential voltage

V _CATH '‧‧‧ control signal

V _ANODE ‧‧‧High potential voltage

V _ANODE '‧‧‧ control signal

1 is a circuit block diagram of a conventional display device; FIG. 2 is a circuit diagram of a conventional pixel circuit; FIG. 3 is a timing chart illustrating an output signal of a conventional driving circuit; and FIG. 4 is a display device of the present invention. FIG. 5 is a circuit diagram of a current-based pixel circuit of the first preferred embodiment; FIG. 6 is a timing diagram illustrating an output signal of the driving circuit of the first preferred embodiment; Figure 7 is a partial circuit diagram showing the current-type pixel circuit of the first preferred embodiment in a writing position; Figure 8 is a partial circuit diagram showing the current-type pixel circuit of the first preferred embodiment in a light-emitting position; 9 is a flow chart illustrating the operation principle of the display device of the first preferred embodiment; FIG. 10 is a circuit block diagram of a second preferred embodiment of the display device of the present invention; and FIG. 11 is a second preferred embodiment. FIG. 12 is a timing diagram illustrating an output signal of a driving circuit of a second preferred embodiment; FIG. 13 is a circuit diagram of a third preferred embodiment of the display device of the present invention. Figure 14 is a circuit diagram of a current-based pixel circuit of a third preferred embodiment; Figure 15 is a circuit diagram of a current-based pixel circuit of the fourth preferred embodiment; Figure 16 is a timing chart illustrating a fourth comparison Figure 17 is a circuit diagram of a current-based pixel circuit of a fifth preferred embodiment; Figure 18 is a circuit block diagram of a sixth preferred embodiment of the display device of the present invention; Figure 20 is a timing diagram showing the output signal of the driving circuit of the sixth preferred embodiment; Figure 21 is a current drawing of the seventh preferred embodiment; FIG. 22 is a circuit diagram of a current type pixel circuit of the eighth preferred embodiment; FIG. 23 is a circuit diagram of a current type pixel circuit of the ninth preferred embodiment; and FIG. 24 is a ninth preferred embodiment. FIG. 25 is a circuit diagram of a current-based pixel circuit of a tenth preferred embodiment; FIG. 26 is a circuit diagram of a current-based pixel circuit of the eleventh preferred embodiment; Is another current type pixel of the eleventh preferred embodiment Figure 28 is a circuit diagram of a current mode pixel circuit of a twelfth preferred embodiment; and Figure 29 is a circuit diagram of another current mode pixel circuit of the twelfth preferred embodiment Road map.

1‧‧‧Current pixel circuit

11‧‧‧Switch unit

C‧‧‧ capacitor

D‧‧‧Organic Luminescent Diodes

T1‧‧‧first transistor

T2‧‧‧second transistor

T3‧‧‧ third transistor

T4‧‧‧ fourth transistor

T5‧‧‧ fifth transistor

T6‧‧‧ sixth transistor

VDD‧‧‧ operating voltage

VEE‧‧‧ modulated voltage

GND‧‧‧ Grounding voltage

I _DATA (m)‧‧‧ drive current

V _SCAN 1(n)‧‧‧ scan signal

V _CATH ‧‧‧low potential voltage

Claims (7)

A current-based pixel circuit, configured to receive a first voltage, a scan signal, a control signal, a drive current, and a time-varying signal, comprising: a light-emitting diode, including a first pole and a second pole; a capacitor includes a first end and a second end receiving the control signal; a first transistor comprising a first end, a second end, and a control end, the first end of the first transistor receiving The first voltage, and the control end of the first transistor is electrically connected to the second end of the capacitor; and a switching unit is controlled by the scan signal to make the second end of the first transistor in the write position Switching between the light-emitting positions; in the writing position, the control signal is in a write potential state, and the switching unit electrically connects the second end of the first transistor to the control end of the first transistor, the capacitor transmits the The first transistor is charged with a difference between a current flowing through the second end of the first transistor and the driving current; in the light emitting position, the control signal is in a light emitting potential state, and the switching unit makes the first transistor The second end electrically connects the light emitting two The first pole of the body, the voltage of the second end of the capacitor turns on the first transistor to cause the light emitting diode to emit light; wherein the switching unit comprises a second transistor and a third transistor, the second a first end of the transistor is electrically connected to the second end of the capacitor, and a second end of the first transistor is electrically connected to a second end of the second transistor, a first end of the third transistor, and the The first pole of the light-emitting diode, and The second pole of the light emitting diode receives the time varying signal, and a second end of the third transistor receives the driving current. The galvanic pixel circuit of claim 1, wherein, in the writing position, the second and third transistors are turned on, and the time-varying signal causes the light-emitting diode to be non-conductive, emitting light In the position, the second and third transistors are not turned on, and the time-varying signal turns on the light-emitting diode. The galvanic pixel circuit of claim 1, wherein the first transistor is a P-type transistor, and the second and third transistors are N-type transistors, and the LED is The first extreme anode, the second extreme cathode, and the first voltage is a high potential voltage. The current-based pixel circuit of claim 1, wherein the first, second, and third transistors are P-type transistors, and the first anode and the second pole of the light-emitting diode are a cathode, and the first voltage is a high potential voltage. The current-based pixel circuit of claim 1, wherein the first, second, and third transistors are N-type transistors, and the first electrode of the light-emitting diode is substantially cathode The anode and the first voltage is a low potential voltage. The galvanic pixel circuit of claim 1, wherein the first transistor is an N-type transistor, the second and third transistors are P-type transistors, and the LED is The first pole is the cathode, the second pole is the anode, and the first voltage is a low potential voltage. A display device comprising a driving circuit and a plurality of patent applications The current-based pixel circuit according to any one of the items 1 to 6, wherein the current-type pixel circuits are arranged in a matrix, and for each column of the current-based pixel circuit, the driving circuit outputs the scan signal and the The control signal is for each row of the current-based pixel circuit, the driving circuit outputs the driving current, and the driving circuit outputs the time-varying signal to the second pole of the light-emitting diode of each current-based pixel circuit.