TWI381444B - Method for fabricating an opening - Google Patents

Description

Method of forming an opening

This invention relates to a method of forming an opening, and more particularly to a method of forming an opening in a mosaic structure.

With the advancement of the semiconductor industry, in order to meet the development and design of these high-density integrated circuits, the size of various components has dropped below sub-micron. The performance of these integrated circuits, in addition to the reliability of their internal components, is also subject to the metal interconnects used to transmit the electronic signals between the components. Therefore, with the current trend of continuously reducing the size of the integrated circuit, the integrated circuit process has progressed toward the direction of multiple metal interconnects. In order to solve the difficulty of fabricating metal interconnects in a multi-layer, the damascene process has been extensively studied and developed; in addition, copper (Cu) has a higher specific gravity than aluminum (Al) and most metals. Lower resistivity and excellent electron migration resistance, and low dielectric constant (low-k) materials help reduce the resistance-capacitance (RC delay effect) between metal wires. Therefore, copper wires and low dielectric constant (low-k) insulating layers have been used in a large number for making single damascene structures and dual damascene structures. Moreover, the copper process is also considered to be a new technology to solve the problem of metal wiring in deep sub-half micron integrated circuits in the future.

It should be noted that it is conventional to deposit a barrier layer directly after the hard mask is used to form the opening of the damascene structure, even if the hard mask is overlaid on the dielectric layer. Therefore, the formed barrier layer covers not only the bottom of the opening but also the sidewall surface of the dielectric layer, and also covers a portion of the hard mask surface. However, as the line width is reduced, the barrier of the hard mask greatly reduces the incident angle of the barrier layer during sputtering, so that the barrier layer cannot form a continuous profile on the sidewall surface of the dielectric layer. Since the discontinuous barrier layer causes voids in the subsequently electroplated copper metal layer and creates a poor mosaic structure, how to improve the conventional damascene process is an important issue today.

Therefore, the present invention mainly discloses a method for forming a damascene structure opening to solve the problem that a copper metal layer is easily formed in a conventional process.

In accordance with a preferred embodiment of the present invention, the method of forming an opening of the present invention primarily comprises the following steps. A semiconductor substrate is first provided, and the semiconductor substrate includes at least one metal interconnect layer. A stacked film is then formed on the semiconductor substrate, and the stacked film includes at least one dielectric layer and a hard mask. A hard mask is then used to form an opening in the stacked film without exposing the metal interconnect layer. The hard mask is then removed and a barrier layer is formed over the semiconductor substrate and covers portions of the dielectric layer and portions of the metal interconnect layer surface.

Another embodiment of the present invention discloses a method of forming an opening comprising the following steps. A semiconductor substrate is first provided, and the semiconductor substrate includes at least one metal interconnect layer. A stacked film is then formed on the semiconductor substrate, and the stacked film includes at least one dielectric layer and a hard mask. A hard mask is then used to form an opening in the dielectric layer without exposing the metal interconnect layer. The hard mask is then removed and a barrier layer is deposited over the semiconductor substrate and covers portions of the dielectric layer and portions of the metal interconnect layer surface. Then, a metal layer is filled in the opening, and a chemical mechanical polishing process is performed to remove part of the metal layer and the barrier layer and make the surface of the metal layer flush with the surface of the dielectric layer.

Referring to FIGS. 1 to 5, FIGS. 1 to 5 are schematic views showing a single damascene structure according to a first embodiment of the present invention. As shown in FIG. 1, a semiconductor substrate 12 is first provided, such as a germanium substrate or a silicon-on-insulator (SOI) substrate. The semiconductor substrate 12 includes at least one metal interconnect layer 14, and the metal interconnect layer 14 is selected from the group consisting of metals such as copper, aluminum, titanium, titanium nitride, tantalum, tantalum nitride, and tungsten.

A stacked film 16 is then formed on the semiconductor substrate 12. The stacked film 16 includes a plurality of dielectric layers 18, 20, 22 and a hard mask 24 made of metal. The dielectric layers 18, 20, 22 may each be a low-k dielectric layer, an ultra-low dielectric constant dielectric layer or a common dielectric layer, such as a porous low-k dielectric material, a carbon-doped oxide. (carbon-doped Oxide; CDO), organic bismuth glass (OSGs), fluorinated cerium oxide (FSGs), ultra low dielectric constant (Ultra low-k; k < 2.5), cerium oxynitride (SiON), tantalum nitride or TEOS ( A material layer such as tetraethyloxoxane, and a method of forming the dielectric layers 18, 20, 22 includes a chemical vapor deposition process (CVD), a spin-coating process, and a plasma enhanced chemical vapor deposition process. (plasma-enhanced chemical vapor deposition; PECVD) and high density plasma chemical vapor deposition (HDPCVD) process methods.

In the present embodiment, the dielectric layer 18 is made of NBLOK composed of tantalum carbonitride (SiCN) or composed of tantalum nitride, and the dielectric layer 20 is made of porous low-k dielectric (porous low-k dielectric) Or consisting of SiLK provided by Dow Chemical, the dielectric layer 22 is composed of yttrium oxynitride, and the hard mask 24 is selected from titanium, titanium nitride, tantalum, tantalum nitride, aluminum or copper. A group of aluminum alloys. It should be noted that although the hard mask 24 made of metal is used in this embodiment, it is not limited to this configuration. The present invention can select other non-metal materials as the hard mask 24 according to the process requirements, such as spinning. Materials such as spin-on glass (SOG), oxides, amorphous carbon, polysilicon, or amorphous silicon are within the scope of the present invention.

Next, an insulating layer 26 made of silicon oxynitride (SiON) is applied over the surface of the hard mask 24, and the insulating layer 26 and the hard mask are covered. 24, a pattern transfer process is performed, for example, a patterned photoresist layer 42 is formed on the insulating layer 26, and then an etching process is performed to form an opening 28 in the insulating layer 26 and the hard mask 24. The yttrium oxynitride layer 26 has the function of a bottom anti-reflective layer (Bottom ARC) in this process.

As shown in FIG. 2, the patterned photoresist layer 42 and the insulating layer 26 are then removed using an ashing and descum process, and another pattern transfer process is continued. For example, the dielectric layer 20, 22 is etched by the patterned hard mask 24, and the opening pattern portion of the patterned hard mask 24 is transferred to the dielectric layers 20, 22 for the dielectric layer 20. A corresponding partial opening 30 is formed in 22. It is worthwhile to note that this step will form a corresponding partial opening 30 in the stacked film 16, which may extend into the dielectric layer 18 due to over-etching, but will not expose the metal in the semiconductor substrate 12. Inner wiring layer 14. Further, depending on the etching gas used in this step, the sidewall of the opening 30 may form a polymer layer, so that the polymer layer may be selectively stripped by an oxygen plasma step.

As shown in FIG. 3, a selective etching process is performed, for example, using a chlorine gas (Cl ₂ ) to perform a plasma etching process to remove portions of the patterned hard mask 24. In this embodiment, the sidewalls of the etched patterned hard mask 24 are retracted by etching of the etching gas and form a slightly tapered pattern. A further etching process is then performed with the ChxFy-based etch chemistry to remove portions of the dielectric layer 18 to expose the metal interconnect layer 14, where x, y are integers. It should be noted that in the process of removing a portion of the dielectric layer 18, the sidewalls of the dielectric layer 22 are also partially removed to form a beveled sidewall such as the patterned mask layer 24.

As shown in FIG. 4, a barrier layer 32 and a seed layer 34 are deposited in a sputtering manner on the patterned mask layer 24, the dielectric layers 18, 20, 22, and the metal interconnect layer 14. Exposed surface. The barrier layer 32 may be composed of a single layer or a composite layer of titanium, titanium nitride, tantalum, tantalum nitride, etc., except that the subsequently filled copper metal is prevented from diffusing to the dielectric layers 18, 20, 22, and The adhesion between the metal layer covering the single damascene structure and the single damascene structure can be improved. In addition to providing a current-conducting path for the seed layer 34, another important purpose is to provide a copper nucleation layer in advance to facilitate subsequent nucleation and growth of the electroplated copper. An electroplating process is then performed to form a metal layer 36 of copper on the surface of the seed layer 34 and to fill the opening 30 with the metal layer 36.

As shown in FIG. 5, one or more chemical mechanical polishing processes are performed to remove portions of the metal layer 36, the seed layer 34, the barrier layer 32, the patterned mask layer 24, and the dielectric layer 22 to remain in the opening 30. The metal layer 36 is substantially tangential to the surface of the dielectric layer 20. Thus, the single damascene structure 40 of the first embodiment of the present invention is completed.

Please refer to FIG. 6 to FIG. 10 , and FIG. 6 to FIG. 10 are the first embodiment of the present invention. The second embodiment makes a schematic diagram of a single damascene structure. As shown in FIG. 6, a semiconductor substrate 62 is first provided, such as a germanium substrate or a silicon-on-insulator (SOI) substrate. The semiconductor substrate 62 includes at least one metal interconnect layer 64, and the metal interconnect layer 64 is selected from the group consisting of metal conductors such as copper, titanium, titanium nitride, tantalum, tantalum nitride, and tungsten.

A stacked film 66 is then formed over the semiconductor substrate 62. The stacked film 66 includes a plurality of dielectric layers 68, 70, 72, a hard mask 74 made of metal, and a bismuth oxynitride (SiON) layer disposed between the dielectric layer 72 and the hard mask 74. (not shown), and the yttria layer can serve as an etch stop layer when the hard mask 74 is subsequently patterned. The dielectric layers 68, 70, 72 may each be a low-k dielectric layer, an ultra-low dielectric constant dielectric layer or a common dielectric layer, such as a porous low-k dielectric material, a carbon-doped oxide. (carbon-doped oxide; CDO), organic bismuth glass (OSGs), fluorinated cerium oxide (FSGs), ultra low dielectric constant (Ultra low-k; k < 2.5), tantalum nitride or TEOS (tetraethyl) A material layer such as oxoxane, and a method of forming dielectric layers 68, 70, 72 includes a chemical vapor deposition process (CVD), a spin-coating process, and a plasma enhanced chemical vapor deposition process (plasma- Enhanced chemical vapor deposition (PECVD) and high density plasma chemical vapor deposition (HDPCVD) process methods.

In this embodiment, the dielectric layer 68 is composed of tantalum carbonitride (SiCN). The NBLOK is composed of tantalum nitride, the dielectric layer 70 is composed of a porous low-k dielectric or SiLK provided by Dow Chemical, and the dielectric layer 72 is made of tetra-b. The structure consists of tetraethylorthosilicate (TEOS), and the hard mask 74 is selected from the group consisting of titanium, titanium nitride, tantalum, tantalum nitride, aluminum or copper aluminum alloy. It should be noted that although the hard mask 74 made of metal is used in this embodiment, it is not limited to this configuration. The present invention can select other non-metal materials as the hard mask 74 according to the process requirements, such as spinning. Materials such as spin-on glass (SOG), oxides, amorphous carbon, polysilicon, or amorphous silicon are within the scope of the present invention.

Then, an insulating layer 76 made of silicon oxynitride (SiON) is covered on the surface of the hard mask 74, and a pattern transfer process is performed on the insulating layer 76 and the hard mask 74, for example, a patterned light is formed first. The resist layer 92 is on the insulating layer 76, and then an etching process is performed to form an opening 78 in the insulating layer 76 and the hard mask 74. It should be noted that the yttria layer 76 has the effect of a bottom anti-reflective layer (Bottom ARC) in this process.

As shown in FIG. 7, the patterned photoresist layer 92 and the insulating layer 76 are then removed using an ashing and descum process, and another pattern transfer process is continued. For example, an etching process is performed on the dielectric layers 70 and 72 by using the patterned hard mask 74, and the opening pattern portion in the hard mask 74 is patterned. The portions are transferred to the dielectric layers 70, 72 to form corresponding partial openings 80 in the dielectric layers 70, 72. It is worthwhile to note that this step will form a corresponding partial opening 80 in the stacked film 66. The opening 80 may extend into the dielectric layer 68 due to over-etching, but will not expose the metal in the semiconductor substrate 62. The interconnect layer 64.

As shown in FIG. 8, an etching process is performed to remove the patterned hard mask 74, and then another etching process is performed to remove a portion of the dielectric layer 68 to expose the metal interconnect layer 64, or directly Removing the portion of the dielectric layer 68 while removing the patterned hard mask 74 and exposing the metal interconnect layer 64 are within the scope of the present invention. It should also be noted that the steps of forming a partial opening 80 in the dielectric layers 70, 72 and then removing the patterned hard mask 74 in this embodiment may be different in the same vacuum system. The room is completed.

Next, as shown in FIG. 9, a barrier layer 82 and a seed layer 84 are deposited on the exposed surfaces of the dielectric layers 68, 70, 72 and the metal interconnect layer 64 in a sputtering manner. The barrier layer 82 may be composed of a single layer or a composite layer of titanium, titanium nitride, tantalum, tantalum nitride, etc., except that the subsequently filled copper metal is prevented from diffusing to the dielectric layers 68, 70, 72, and The adhesion between the metal layer covering the single damascene structure and the single damascene structure can be improved. In addition to providing a current-conducting path, the seed layer 84 has another important purpose of providing a copper nucleation layer in advance so that the subsequent electroplating copper can be nucleated and formed thereon. long. An electroplating process is then performed to form a metal layer 86 of copper on the surface of the seed layer 84 and to fill the opening 80 with the metal layer 86.

As shown in FIG. 10, one or more chemical mechanical polishing processes are performed to remove portions of the metal layer 86, the seed layer 84, the barrier layer 82, and the dielectric layer 72 such that the metal layer 86 remaining in the opening 80 is substantially It is aligned with the surface of the dielectric layer 70. Thus, the single damascene structure 90 of the second embodiment of the present invention is completed.

Referring to FIG. 11 to FIG. 16 and FIG. 11 to FIG. 16 , a schematic diagram of a dual damascene structure according to a third embodiment of the present invention is shown. As shown in FIG. 11, a semiconductor substrate 102 is first provided, such as a germanium substrate or a silicon-on-insulator (SOI) substrate. The semiconductor substrate 102 includes at least one metal interconnect layer 104, and the metal interconnect layer 104 is selected from the group consisting of metal conductors such as copper, titanium, titanium nitride, tantalum, tantalum nitride, and tungsten.

A stacked film 106 is then formed over the semiconductor substrate 102. The stacked film 106 includes a plurality of dielectric layers 108, 110, 112 and a hard mask 114 made of metal. The dielectric layers 108, 110, 112 are similar in material to the dielectric layer 68 of the first embodiment. The material of 70, 72, and the material of the hard mask 114 is similar to the material of the hard mask 74 of the first embodiment. In the present embodiment, the dielectric layer 108 is NBLOK composed of tantalum carbonitride (SiCN), and the dielectric layer 110 is made of a porous low dielectric constant material (porous). Low-k dielectric) or SiLK provided by Dow Chemical Co., Ltd., dielectric layer 112 is composed of tetraethylorthosilicate (TEOS), and hard mask 114 contains titanium, titanium nitride, A group of tantalum, tantalum nitride, aluminum or copper-aluminum alloy. As in the first embodiment of the present invention, although the hard mask 114 made of metal is used in the embodiment, the present invention is not limited to this configuration. The present invention can select other non-metal materials as the hard mask 114 depending on the process requirements. Materials such as spin-on glass (SOG), oxides, polysilicon or amorphous carbon are within the scope of the present invention.

Then, an insulating layer 116 made of silicon oxynitride (SiON) is covered on the surface of the hard mask 114, and a pattern transfer process is performed on the insulating layer 116 and the hard mask 114, for example, a patterned photoresist is formed first. The layer 142 is on the insulating layer 116, and then an etching process is performed to form an opening 118 defining the trench in the insulating layer 116 and the hard mask 114. It should be noted that the yttria layer 116 has the effect of a bottom anti-reflective layer (Bottom ARC) in this process.

As shown in FIG. 12, after the patterned photoresist layer 142 is removed by an ashing and descum process, another patterned photoresist layer 120 is formed on the surface of the insulating layer 116 and the dielectric layer 112. An etching process is then performed using the patterned photoresist layer 120 to remove portions of the dielectric layers 110, 112 to form a partial via 122 in the dielectric layers 110, 112. As in the previous embodiment, the etching process forms a portion of the contact holes 122 in the dielectric layers 110, 112 relative to the patterned photoresist layer 120 but does not expose the metal interconnect layer 104 in the semiconductor substrate 102.

As shown in FIG. 13, the patterned photoresist layer 120 and the insulating layer 116 are removed by an ashing and descum process, and then another etching process is performed by using the patterned hard mask 114. A trench 124 corresponding to the opening of the patterned hard mask 114 is formed in the electrical layers 110, 112. It should be noted that the trench 124 may extend into the dielectric layer 108 due to over-etching, but does not expose the metal interconnect layer 104 in the semiconductor substrate 102.

Next, as shown in FIG. 14, an etching process is performed to remove the patterned hard mask 114, and then another etching process is performed to remove the residual dielectric layer 108 in the trench 124 to expose the metal interconnect layer 104. Alternatively, it is within the scope of the present invention to remove the residual dielectric layer 108 in the trench 124 and expose the metal interconnect layer 104 directly while removing the patterned hard mask 114. In addition, it should be noted that the steps from forming the patterned photoresist layer 120 to forming the trench 124 in this embodiment can be performed in different reaction chambers in the same vacuum system.

Then, as shown in FIG. 15, a barrier layer 126 and a seed layer 128 are sequentially formed on the surfaces of the dielectric layers 108, 110, 112 and the metal interconnect layer 104. As described in the previous embodiments, the barrier layer 126 is made of titanium, titanium nitride, A single material layer such as tantalum or tantalum nitride can be used to prevent the subsequent filling of the copper metal from diffusing to the dielectric layers 108, 110, 112, and to improve the subsequent metal layer and the single layer covering the single damascene structure. Adhesion between the mosaic structures. An electroplating process is then performed to form a metal layer 130 of copper on the surface of the seed layer 128, and the metal layer 130 fills the trench 124 and the contact hole 122.

As shown in FIG. 16, one or more chemical mechanical polishing processes are performed to remove a portion of the metal layer 130, the seed layer 128, the barrier layer 126, and the dielectric layer 112 on the surface of the dielectric layer 110 so as to remain in the trench 124. The metal layer 130 is substantially tangential to the surface of the dielectric layer 110. Thus, the dual damascene structure 140 of the third embodiment of the present invention is completed. It should also be noted that this embodiment combines the dual damascene process in a manner that completely removes the patterned hard mask in the second embodiment. However, the present invention is not limited to this practice, and the present invention can be combined with the method of only partially removing the patterned hard mask in the first embodiment to complete the dual damascene process, which is within the scope of the present invention.

Referring to FIGS. 17 to 19, FIGS. 17 to 19 are schematic views showing a dual damascene structure according to a fourth embodiment of the present invention. As shown in FIG. 17, the present invention can first perform the processes of FIGS. 12 to 13 and form the dielectric layer 112 with hafnium oxynitride, and then pattern the hard mask 114, the dielectric layers 110 and 112. Corresponding contact holes 122 and trenches 124 are formed.

A selective etching process is then performed, such as a plasma etching process using chlorine (Cl ₂ ) to remove portions of the patterned hard mask 114. In this embodiment, the sidewalls of the patterned patterned hard mask 114 are retracted by etching of the etching gas and form a slightly tapered pattern.

As shown in FIG. 18, another etching process is performed with a ChxFy-based etch chemistry to remove portions of the dielectric layer 108 to expose the metal interconnect layer 104, where x, y are integers. It should be noted that in the process of removing a portion of the dielectric layer 108, the sidewalls of the dielectric layer 112 are also partially removed to form a beveled sidewall such as the patterned mask layer 114.

As shown in FIG. 19, a barrier layer 126 and a seed layer 128 are sequentially formed on the surface of the patterned hard mask 114, the dielectric layers 108, 110, 112, and the metal interconnect layer 104. As with the previously described embodiments, the barrier layer 126 may be composed of a single material layer such as titanium, titanium nitride, tantalum, or tantalum nitride. An electroplating process is then performed to form a metal layer 130 of copper on the surface of the seed layer 128, and the metal layer 130 fills the trench 124 and the contact hole 122. Finally, one or more chemical mechanical polishing processes may be performed to remove portions of the metal layer 130, the seed layer 128, the barrier layer 126, and the dielectric layer 112 on the surface of the dielectric layer 110, so that the metal layer 130 remaining in the trench 124 is substantially The upper surface is tangent to the surface of the dielectric layer 110.

In summary, the present invention is mainly in the dielectric layer has not been completely etched The damascene pattern is required and the hard mask used to form the opening of the damascene structure is completely removed or partially removed before the deposition of the barrier layer, and then the subsequent sputtering and electroplating processes are performed. Since the step of removing the hard mask can greatly increase the incident angle when the barrier layer is sputtered, a barrier layer having a continuous contour can be formed on the sidewall surface of the dielectric layer when the barrier layer is sputtered, and the subsequent coverage is performed. The copper metal layer on the barrier layer does not become a gap due to the discontinuity of the barrier layer.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

12‧‧‧Semiconductor substrate

14‧‧‧Metal interconnect layer

16‧‧‧Stacked film

18‧‧‧ dielectric layer

20‧‧‧Dielectric layer

22‧‧‧Dielectric layer

24‧‧‧hard mask

26‧‧‧Insulation

28‧‧‧ openings

30‧‧‧ openings

32‧‧‧Barrier layer

34‧‧‧ seed layer

36‧‧‧metal layer

38‧‧‧Dielectric layer

40‧‧‧Single mosaic structure

42‧‧‧ patterned photoresist layer

62‧‧‧Semiconductor substrate

64‧‧‧Metal interconnect layer

66‧‧‧Stacked film

68‧‧‧Dielectric layer

70‧‧‧Dielectric layer

72‧‧‧ dielectric layer

74‧‧‧hard mask

76‧‧‧Insulation

78‧‧‧ openings

80‧‧‧ openings

82‧‧‧Barrier layer

84‧‧‧ seed layer

86‧‧‧metal layer

90‧‧‧Single mosaic structure

92‧‧‧ patterned photoresist layer

102‧‧‧Semiconductor substrate

104‧‧‧Metal interconnect layer

106‧‧‧Stacked film

108‧‧‧ dielectric layer

110‧‧‧ dielectric layer

112‧‧‧ dielectric layer

114‧‧‧hard mask

116‧‧‧Insulation

118‧‧‧ openings

120‧‧‧ patterned photoresist layer

122‧‧‧Contact hole

124‧‧‧ Ditch

126‧‧‧Barrier layer

128‧‧‧ seed layer

130‧‧‧metal layer

140‧‧‧Dual mosaic structure

142‧‧‧ patterned photoresist layer

1 to 5 are schematic views showing a single damascene structure produced by the first embodiment of the present invention.

6 to 10 are schematic views showing a single damascene structure according to a second embodiment of the present invention.

11 to 16 are schematic views showing a double damascene structure according to a third embodiment of the present invention.

17 to 19 are schematic views showing a double damascene structure according to a fourth embodiment of the present invention.

62‧‧‧Semiconductor substrate

64‧‧‧Metal interconnect layer

68‧‧‧Dielectric layer

70‧‧‧Dielectric layer

82‧‧‧Barrier layer

84‧‧‧ seed layer

86‧‧‧metal layer

90‧‧‧Single mosaic structure

Claims (24)

A method of forming an opening, comprising the steps of: providing a semiconductor substrate comprising at least one metal interconnect layer; forming a stacked film on the semiconductor substrate, the stacked film comprising at least one dielectric layer and a hard mask; forming an opening in the stacked film without exposing the metal interconnect layer; removing the hard mask; and forming a barrier layer on the semiconductor substrate and covering a portion of the a dielectric layer and a portion of the surface of the metal interconnect layer. The method of claim 1, wherein forming the opening in the stacked film comprises: patterning the hard mask; and etching the stacked film by using the patterned hard mask as an etch mask The opening is formed. The method of claim 1, wherein forming the opening in the stacked film comprises: patterning the hard mask; forming a patterned photoresist layer on the semiconductor substrate and covering the patterned hard Mask Using the patterned photoresist layer as an etch mask to form a via in the stacked film; removing the patterned photoresist layer; and using the patterned hard mask as an etch mask The stacked film is etched to form the opening. The method of claim 1, wherein the forming the stacked film further comprises: forming an insulating layer on the hard mask; and patterning the insulating layer and the hard mask with a patterned photoresist layer cover. The method of claim 1, wherein the dielectric layer is selected from the group consisting of tetraethylorthosilicate (TEOS), tantalum nitride, porous low-k dielectric, A group consisting of NBLOK composed of cerium oxynitride (SiON), lanthanum carbonitride (SiCN) or SiLK supplied by Dow Chemical Company. The method of claim 1, wherein the hard mask is a metal hard mask. The method of claim 6, wherein the metal hard mask is selected from the group consisting of amorphous germanium, polycrystalline germanium, titanium, titanium nitride, tantalum, tantalum nitride, aluminum or copper aluminum alloy. The method of claim 1, wherein the metal interconnect layer is selected from the group consisting of copper, titanium, titanium nitride, tantalum, tantalum nitride, and tungsten. The method of claim 1, further comprising exposing the metal interconnect layer when the hard mask is removed. The method of claim 1, wherein the step of forming the opening in the stacked film and removing the hard mask is achieved in the same vacuum system. The method of claim 1, further comprising forming an etch stop layer between the dielectric layer and the hard mask. A method of forming an opening, comprising the steps of: providing a semiconductor substrate comprising at least one metal interconnect layer; forming a stacked film on the semiconductor substrate, the stacked film comprising at least one dielectric layer and a hard mask; forming an opening in the stacked film by the hard mask without exposing the metal interconnect layer; partially removing the hard mask; Forming a barrier layer on the semiconductor substrate and covering a portion of the hard mask, the dielectric layer and a portion of the surface of the metal interconnect layer. In the method of claim 12, the step of partially removing the hard mask comprises partially removing the hard mask by a plasma etching process to retract the sidewall of the hard mask to form an oblique pattern. The method of claim 13, further comprising using chlorine gas to perform the plasma etching process. The method of claim 12, wherein forming the opening in the stacked film comprises: patterning the hard mask; and forming the opening by using the patterned hard mask as an etch mask. The method of claim 12, wherein forming the opening in the stacked film comprises: patterning the hard mask; forming a patterned photoresist layer on the semiconductor substrate and covering the patterned hard a mask; forming a contact in the stacked film by using the patterned photoresist layer; removing the patterned photoresist layer; The opening is formed using the patterned hard mask as an etch mask. The method of claim 12, wherein the forming the stacked film further comprises: forming an insulating layer on the hard mask; and patterning the insulating layer and the hard mask with a patterned photoresist layer cover. The method of claim 12, wherein the dielectric sequence is selected from the group consisting of tetraethylorthosilicate (TEOS), tantalum nitride, porous low-k dielectric, A group consisting of NBLOK composed of cerium oxynitride (SiON), lanthanum carbonitride (SiCN) or SiLK supplied by Dow Chemical Company. The method of claim 12, wherein the hard mask is a metal hard mask. The method of claim 19, wherein the metal hard mask is selected from the group consisting of amorphous germanium, polycrystalline germanium, titanium, titanium nitride, tantalum, tantalum nitride, aluminum or copper aluminum alloy. The method of claim 12, wherein the metal interconnect layer is selected from the group consisting of copper, titanium, titanium nitride, tantalum, tantalum nitride, and tungsten. The method of claim 12, further comprising exposing the metal interconnect layer after partially removing the hard mask. The method of claim 12, wherein the step of forming the opening in the stacked film and partially removing the hard mask is achieved in the same vacuum system. The method of claim 12, further comprising forming an etch stop layer between the dielectric layer and the hard mask.