TWI381354B - Timing controller and liquid crystal display using same - Google Patents

Description

Timing controller and liquid crystal display using the same

The present invention relates to a timing controller and a liquid crystal display using the same.

Due to its advantages of lightness, thinness, and low power consumption, the liquid crystal display panel is widely used in modern information equipment such as televisions, notebook computers, mobile phones, and personal digital assistants. As liquid crystal display technology becomes more and more mature, people have higher and higher requirements for the color display capability of liquid crystal display panels.

The color display capability of the liquid crystal display panel is described by the number of bits of the gray scale that the liquid crystal panel can display on each color channel. Each color channel can display 2 to the 6th power, that is, 64 grayscale liquid crystal display panels are called 6bit liquid crystal display panels. The liquid crystal display panel has three color channels of red, green and blue (RGB), which can display 262,144 colors (64×64×64=262144). By analogy, the 8-bit LCD panel displays 256 gray scales and can display 16777216 (16.7M) colors. From here we can see that the theoretical 6-bit panel can display less than 2% of the 8-bit panel.

The liquid crystal display panel displays the number of bits of the gray scale, which can be understood from the perspective of the maximum number of driving paths of the liquid crystal display driving integrated circuit. For example, the maximum number of driving channels of a 6-bit LCD panel can only be 64, which does not meet the hardware requirements of true color display. However, there are advantages to the number of driving paths. For example, the number of driving paths can reduce the design difficulty in terms of viewing angle and contrast. From the physical structure of the liquid crystal display panel, the 6-bit liquid crystal display panel, that is, the liquid crystal molecules, only 64 kinds of screens can be displayed between pure black and pure white. The state of control is easy to control, so most LCD monitors with a response time of 12 milliseconds and 8 milliseconds generally use a 6-bit liquid crystal display panel.

In actual use, the colors of the 6-bit and 8-bit LCD panels do not look much different. This is mainly the use of color enhancement technology, the purpose is to reduce the gap between the 6bit panel and the 8-bit panel, extending the application life of the 6bit panel. The so-called color enhancement technology usually includes pixel dithering (PD) algorithm and frame rate control (FRC) technology, which all utilize the principle of human visual inertia. For example, the frame rate control technique refreshes the pixels multiple times while displaying each screen image, so that the pixels cause a gray-scale transient during the switching of the frames, thereby increasing the number of gray levels that can be displayed. Since the frame rate control technique is relatively easy to implement and can be used without extensively reducing the resolution of the image. Enhanced by color enhancement technology, the 6-bit LCD panel is comparable to the color of the 8-bit LCD panel.

Please refer to FIG. 1 , which is a schematic diagram of a principle of a frame rate control algorithm. It is assumed that each pixel can only display two colors of black and white. Four frames in a row display one picture, and the gray level is 1 when all four consecutive frames of one pixel are displayed, and the gray level is 0 when all white is displayed. It can be seen from the figure that from top to bottom, five gray scales 0, 1/4, 1/2, 3/4, 1 can be generated, so that the frame rate control algorithm can realize only two colors of black and white. The purpose of displaying five different gray levels is to add three gray scale displays. In fact, if a picture is displayed in eight consecutive frames, the frame rate control algorithm can achieve the purpose of displaying nine different gray levels in only black and white, that is, adding seven gray scale displays.

The foregoing principle is only the principle of the frame rate control algorithm in the time domain. In fact, current frame rate control algorithms tend to go in both time and space domains. Row.

Please refer to FIG. 2, which is a schematic diagram of the principle of the frame rate control algorithm in the time domain and the spatial domain. It is assumed that each pixel can only display two colors of black and white. In the time domain, four frames are displayed in a continuous frame, and in the spatial domain, every four pixels constitute a pixel unit. It is defined that the gray level is 1 when all four consecutive frames of one pixel unit are displayed in black, and the gray level is 0 when all white is displayed. As can be seen from the figure, from top to bottom, five gray levels 0, 1/4, 1/2, 3/4, 1 can be generated. Compared with the frame rate control algorithm in a single time domain, the frame rate control algorithm performed simultaneously in the time domain and the spatial domain has the function of pixel jitter. For example, for a 1/2 gray scale, any eight gray scales of the sixteen gray scale displays of the four consecutive frames can be obtained, and the time and position of the pixels of the eight gray scales of 1 are not present. limit.

Liquid crystal displays typically use a frame rate control algorithm to enhance their display. The frame rate control algorithm is stored in a timing controller of the liquid crystal display.

Please refer to FIG. 3, which is a schematic diagram of a prior art liquid crystal display. The liquid crystal display 10 includes a liquid crystal display panel 11, a scan driver 12, a data driver 13, and a timing controller 14. The timing controller 14 includes a memory 142 and a data processor 141. The memory 142 stores a frame rate control algorithm, and the data processor 141 uses the frame rate control algorithm to process the received external initial data signal into a data signal to be displayed and provides the data signal to the data driver 13. The timing controller 14 provides timing control signals for the scan driver 12 and the data driver 13. The scan driver 12 and the data driver 13 are used to drive the liquid crystal display Panel 11.

Because different frame rate control algorithms have different display effects, the liquid crystal display 10 for different display requirements generally adopts different timing controllers 14, and the timing controller 14 adopts a specific frame rate control algorithm to conform to the liquid crystals. Display requirements for display 10. However, since the timing controller 14 includes only a specific frame rate control algorithm, the timing controller 14 is only applicable to a liquid crystal display, and the liquid crystal display 10 for different display needs needs to redesign the timing controller 14, thus making the product Low design freedom, long cycle and high cost. For the liquid crystal display 10 using the timing controller 14, it is not possible to adjust the display effect by adjusting the frame rate control algorithm.

In view of this, it is necessary to provide a timing controller with high design freedom, short cycle, and low cost.

In view of the above, a liquid crystal display capable of adjusting a display effect by adjusting a frame rate control algorithm is provided.

A timing controller includes a data processor, a memory and at least one pin for storing at least two frame rate control algorithms, wherein the at least one pin is used to select one of the frame rate control algorithms, the data The processor uses the frame rate control algorithm to process the initial data signal it receives.

A liquid crystal display includes a liquid crystal panel, a scan driver, a data driver and a timing controller. The scan driver and the data driver are used to drive the liquid crystal display panel. The timing controller is used for the scan The driver and the data driver provide a timing control signal and provide the data driver with a data signal to be displayed. The timing controller includes a data processor, a memory, and at least one pin. The memory is configured to store at least two frame rate control algorithms, the pin is configured to control the data processor to select a frame rate control algorithm, and the data processor uses the frame rate control algorithm to process the initial data signal received by the data processor to The information signal to be displayed is provided to the data drive.

Compared with the prior art, the timing controller of the present invention stores at least two frame rate control algorithms, so that the timing controller is applicable to at least two liquid crystal displays with different display requirements without redesigning according to different display requirements of the liquid crystal display. The timing controller thus shortens the design cycle of the liquid crystal display product and reduces the design cost. The liquid crystal display using the timing controller can adjust the display effect by adjusting the frame rate control algorithm.

Please refer to FIG. 4, which is a schematic diagram of a first embodiment of a liquid crystal display of the present invention. The liquid crystal display 20 includes a liquid crystal panel 21, a scan driver 22, a data driver 23, and a timing controller 24. The scan driver 22 and the data driver 23 are used to drive the liquid crystal panel 21.

Please refer to FIG. 5 , which is a schematic diagram of the circuit structure of the timing controller 24 . The timing controller 24 includes a data processor 241, a memory 242, a first pin 243, and a second pin 244. The memory 242 stores four frame rate control algorithms, and the data processor 241 reads a frame rate control algorithm from the memory 242 and uses the frame rate control algorithm to The received external initial data signal is processed as a data signal to be displayed and provided to the data driver 23. The timing controller 24 provides timing control signals for the scan driver 22 and the data driver 23. The timing controller 24 selects the frame rate control algorithm according to a logic state in which the first pin 243 and the second pin 244 are applied with a high potential or a low potential. The memory 242 is an electrically erasable programmable read-only memory (EEPROM).

The first pin 243 of the timing controller 24 is connected to a first power source VCC1 via a first resistor R1, and is grounded via a second resistor R2. The second pin 244 is connected to a second power source VCC2 via a third resistor R3 and is grounded via a fourth resistor R4. When the power source VCC1 is at a high potential, the potential of the first pin 243 is high, and when the potential of the power source VCC1 is 0, the potential of the first pin 243 is low. Similarly, when the power supply VCC2 is at a high potential, the potential of the second pin 244 is high, and when the potential of the power supply VCC2 is 0, the potential of the second pin 244 is low. The four resistors R1, R2, R3 and R4 have the same resistance value.

Please refer to FIG. 6 , which is a schematic diagram of the correspondence between the logic states of the two pins 243 and 244 and the four frame rate control algorithms. Here, 0 indicates that the potentials of the two pins 243 and 244 are low, and 1 indicates that the potentials of the two pins 243 and 244 are high. The potentials of the two pins 243 and 244 have four logical states of 00, 01, 10 and 11, respectively corresponding to four frame rate control algorithms. When the potential of the two pins 243, 244 is low, the logic potential of the two pins 243, 244 is 00, and the liquid crystal display 20 uses the frame rate control algorithm to process the data signal. When the first pin 243 is low When the second pin 244 is at a high potential, the logic potential of the two pins 243 and 244 is 01, and the liquid crystal display 20 uses the frame rate control algorithm 2 to process the data signal. When the first pin 243 is at a high potential and the second pin 244 is at a low potential, the logic potential of the two pins 243 and 244 is 10, and the liquid crystal display 20 processes the data signal by using the frame rate control algorithm 3. When the two pins 243 and 244 are at a high potential, the logic potentials of the two pins 243 and 244 are 11, and the liquid crystal display device 20 uses the frame rate control algorithm to process the data signals.

Please refer to FIG. 7 , which is a schematic diagram of a frame rate control algorithm in a time domain and a spatial domain. It is assumed that each pixel can only display two colors of black and white. In the time domain, four frames are displayed in a continuous frame, and in the spatial domain, every four pixels constitute a pixel unit. It is defined that each pixel of a pixel unit has a gray scale of 1 when all four frames are displayed in black, and the gray scale is 0 when all white is displayed. As can be seen from the figure, from top to bottom, five gray scales of 0, 1/4, 1/2, 3/4, 1 can be produced. Taking a liquid crystal display with a total of 64 colors of 4×4×4 as an example, each pixel only needs to display four gray scales, so any four of the above five gray scales are used, and there are five implementation methods: 0, 1/4, 1/2, 3/4; 0, 1/4, 1/2, 1; 0, 1/4, 3/4, 1; 0, 1/2, 3/4, 1; 4, 1/2, 3/4, 1, the five implementation methods define five frame rate control algorithms.

Similarly, if each pixel of the liquid crystal display can display 64 gray scales, more than 500 gray scales can be generated by using the frame rate control algorithm, and any 256 gray scales can realize full color display of 16.7M colors, thus having plural A frame rate control algorithm can achieve a full color display of 16.7M colors. The present invention employs four of the frame rate control algorithms.

Compared with the prior art, the timing controller 24 includes four alternative frame rate control algorithms, so that it can be used for four different display requirements of the liquid crystal display, without the need to re-design the design, the product design freedom is greatly improved. The cycle is shortened and the design cost is reduced. The liquid crystal display 20 employs the timing controller 24, which can adjust the display effect by adjusting the frame rate control algorithm.

Please refer to FIG. 8, which is a schematic diagram of a timing controller of a second embodiment of the liquid crystal display of the present invention. The liquid crystal display is substantially the same as the liquid crystal display 20 of the first embodiment, except that the timing controller 34 includes three pins 343, 344 and 345, and the three pins 343, 344 and 345 have a high potential and a low potential. The logic states are eighty, 000, 001, 010, 011, 100, 101, 110, and 111. The corresponding memory 342 stores eight frame rate control algorithms for use by the data processor 341.

The embodiment of the present invention is not limited to the above embodiment. For example, the number of pins of the timing controller 20 for selecting a frame rate control algorithm may also be four. Accordingly, the timing controller 20 stores sixteen frame rates. Control algorithm. For the present invention, the number of pins of the timing controller 20 for selecting a frame rate control algorithm is at least one. Accordingly, the timing controller 20 stores at least two frame rate control algorithms. The more pin counts and stored frame rate control algorithms, the higher the degree of product design freedom.

In summary, the present invention has indeed met the requirements of the invention patent, and has filed a patent application according to law. However, the above-mentioned embodiments are merely preferred embodiments of the present invention, and the scope of the present invention is not limited to the above-described embodiments, and those skilled in the art will be able to make equivalent modifications or variations in accordance with the spirit of the present invention. All should be covered by the following patent application.

20‧‧‧LCD display

21‧‧‧LCD panel

22‧‧‧ scan driver

23‧‧‧Data Drive

24, 34‧‧‧ timing controller

241‧‧‧ Data Processor

242, 342‧‧‧ memory

243, 244, 343, 344, 345‧‧‧ pins

1 is a schematic diagram of the principle of a frame rate control algorithm of a prior art time domain.

2 is a schematic diagram showing the principle of a frame rate control algorithm of a prior art time domain and a spatial domain.

Figure 3 is a schematic illustration of a prior art liquid crystal display.

4 is a schematic view showing a first embodiment of a liquid crystal display of the present invention.

FIG. 5 is a schematic diagram showing the circuit structure of the timing controller in FIG. 4.

FIG. 6 is a schematic diagram showing the correspondence between the logic states of the two pins and the four frame rate control algorithms in FIG. 5.

Figure 7 is a schematic diagram of the principle of a frame rate control algorithm for time domain and spatial domain.

8 is a schematic diagram of a timing controller of a second embodiment of the liquid crystal display of the present invention.

24‧‧‧ timing controller

241‧‧‧ Data Processor

242‧‧‧ memory

243, 244‧‧‧ pin

Claims (10)

A timing controller includes: a data processor, a memory, and at least two pins for storing at least four frame rate control algorithms, wherein the at least two pins are used to select one of the frame rate control algorithms, The data processor uses the frame rate control algorithm to process the initial data signal it receives. The pin is connected to a first power source via a first resistor, and is grounded via a second resistor, and the other pin is connected via a third The resistor is coupled to a second power source and is coupled to ground via a fourth resistor. The timing controller of claim 1, wherein the timing controller selects a corresponding frame rate control algorithm by applying a high potential or a low potential to the pin. The timing controller of claim 1, wherein the four resistors have the same resistance value. The timing controller of claim 3, wherein the memory is an electrically erasable programmable read only memory. The timing controller of claim 2, wherein the number of the pins is three, and correspondingly, the memory stores eight frame rate control algorithms. A liquid crystal display comprising: a liquid crystal panel; a scan driver and a data driver for driving the liquid crystal display panel; and a timing controller for providing the scan driver and the data driver Providing a timing control signal, and providing the data driver with a data signal to be displayed, the timing controller includes a data processor, a memory and at least two pins, wherein the memory is configured to store at least four frame rate control algorithms, the at least The second pin is used to control the data processor to select a frame rate control algorithm, and the data processor uses the frame rate control algorithm to process the received initial data signal into a data signal to be displayed, and provides the data signal to the data driver. The one pin is connected to a first power source via a first resistor, and is grounded via a second resistor. The other pin is connected to a second power source via a third resistor and grounded via a fourth resistor. The liquid crystal display of claim 6, wherein the timing controller selects a corresponding frame rate control algorithm by applying a high potential or a low potential to the pin. The liquid crystal display of claim 6, wherein the four resistors have the same resistance value. The liquid crystal display of claim 6, wherein the memory is an electrically erasable programmable read only memory. The liquid crystal display of claim 7, wherein the number of pins is three, and correspondingly, the memory stores eight frame rate control algorithms.