TWI381265B - A proportional to absolute temperature current and voltage of bandgap reference with start-up circuit - Google Patents

Description

A difference reference circuit having a start-up circuit and simultaneously providing a temperature-independent reference current and a reference voltage

The invention belongs to the field of analog wafer design, and can provide a difference reference circuit having a starting circuit and simultaneously providing a temperature-independent reference current and a reference voltage, in particular, a circuit such as a starting circuit, a reference current circuit and a reference voltage circuit. The composition can simultaneously provide reference current and reference voltage independent of temperature, improve the application breadth and competitiveness of the circuit; further, with the start circuit, the difference reference circuit can be operated under low voltage conditions to achieve power saving effect. By.

Voltage and current reference circuits are widely used in the analog circuit category. An ideal reference circuit should be independent of power supply, temperature, and process parameters. However, temperature changes will greatly affect the physical properties of the semiconductor, and it is easy to cause the operating point of the circuit to shift. Therefore, it is necessary to use the method of canceling the positive and negative temperature coefficients to suppress the influence of temperature on the circuit. This is also a necessary reference circuit. condition.

The first figure shows the basic architecture of a conventional differential reference circuit, which is a combination of two voltage signals. The first voltage signal is the base voltage V _{EB of the} bipolar junction transistor, which is a negative temperature coefficient voltage; the second voltage signal is the positive temperature coefficient voltage V _P , which is amplified by K times and then The first voltage signal is added to achieve temperature compensation.

According to the conventional architecture of the first figure, it has been proposed to develop a low voltage band difference reference circuit with a PMOS input operational amplifier. The second figure shows a conventional low voltage band difference reference circuit 200, which includes a gold-oxygen semiconductor transistor M201, M202, M203, a bipolar junction transistor Q201, Q202, a resistor R201, a R202, a R203, R204, R205, R206 and operational amplifier A201. The circuit can generate a stable reference current I, flowing through the resistor R206 to produce a stable output reference voltage V _{ref_2} . However, the temperature change will still affect the resistance change of the resistor R206, which is easy to cause the fluctuation of the output reference voltage, so further compensation is needed. Furthermore, in the case of single-supply operation, the use of an op amp with a PMOS input has a problem of low DC bias and temperature drift, which causes the ground-biased transistor to be inoperable in the saturation region and malfunctions. The solution can be changed to an NMOS input op amp, but further bias compensation is still needed to make the op amp work properly. As for the application, most of the reference circuits can only provide the reference voltage or the reference current separately. If the temperature-independent reference voltage and reference current can be provided at the same time, the industrial application range of the difference reference circuit can be expanded.

The object of the present invention is to provide a temperature-independent reference circuit, in particular to a start-up circuit, a reference current circuit and a reference voltage circuit, which can simultaneously output a reference current and a reference voltage independent of temperature, thereby improving industrial utilization. And can be operated under low voltage conditions through the startup circuit to achieve power saving effect.

A further object of the invention is to use a start-up circuit comprising three transistor elements, the three transistors being in a closed state when the current flowing through all of the transistors is zero; when the supply voltage is to be added The starting circuit can start the band difference reference circuit under the condition of low voltage (less than 1.5 volts), and enters the off state after completing the starting work, and does not affect the normal operation of the band difference reference circuit.

Another object of the present invention is to increase the functional expandability of the difference reference circuit by utilizing the output of the reference voltage and the reference current which are independent of temperature, and to achieve an effect of expanding the industrial applicability.

To achieve the above objects of the present invention, and in accordance with the related advantages as embodied and generally described, the present invention provides a band difference reference circuit having a start-up circuit and simultaneously providing a temperature-independent reference current and a reference voltage, the technical characteristics of which are The invention is composed of a starting circuit, a reference current circuit and a reference voltage circuit; wherein the starting circuit has a first P-type MOS field effect transistor (Mp) and a second P-type MOS half-field effect The transistor (Ms) is electrically connected with a third N-type gold-oxygen half field effect transistor (Mn) or the like; the reference current circuit has a fourth P-type gold-oxygen half field effect transistor (M1) , a fifth P-type gold-oxygen half-field effect transistor (M2), a seventh P-type gold-oxygen half-field effect transistor (M4), an N-type differential input operational amplifier (N-type OPA), a first Boosting resistor (Ra1), a second boosting resistor (Ra2), a fourth compensating resistor (Rb1), a fifth compensating resistor (Rb2), a seventh biasing resistor (R2), and a first bipolar The electrical connection between the junction transistor (Q1) and a second bipolar junction transistor (Q2); the reference electricity The circuit has a sixth P-type MOS field-effect transistor (M3), an N-type differential input operational amplifier (N-type OPA), a first boost resistor (Ra1), and a second boost resistor (Ra2), a third boosting resistor (Ra3), a fourth compensating resistor (Rb1), a fifth compensating resistor (Rb2), a sixth compensating resistor (Rb3), a seventh resistor (R2), and a The first bipolar junction transistor (Q1), a second bipolar junction transistor (Q2) and a third bipolar junction transistor (Q3) are electrically connected.

In addition, the present invention has a start-up circuit and can simultaneously provide a temperature-independent reference current and a reference voltage difference reference circuit, wherein the first boost resistor (Ra1) and the set voltage difference circuit are provided. The second boosting resistor (Ra2) is used to boost the bias potential of the positive and negative terminals of the operational amplifier of the N-type differential input.

Moreover, the base voltage (V _BE2 ) of the second bipolar junction transistor (Q2) of the reference current circuit has a negative voltage temperature coefficient characteristic, and the fifth compensation resistor (Rb2) has a negative current temperature coefficient. The base voltage difference (ΔV _BE ) of the first bipolar junction transistor (Q1) and the second bipolar junction transistor (Q2) has a positive voltage temperature coefficient such that it flows through the seventh bias resistor (R2) The current has a positive current temperature coefficient, which can cancel out the negative current temperature coefficient of the fifth compensation resistor (Rb2) to form a temperature-independent reference current, via the fourth P-type gold-oxygen half-field effect transistor (M1), A current mirror outputting a reference current composed of a fifth P-type gold-oxygen half-field effect transistor (M2) and a seventh P-type gold-oxygen half-field effect transistor (M4), thereby obtaining a temperature-independent reference current (I _ref ) .

Furthermore, the sixth P-type metal oxide half field effect transistor (M3) of the reference voltage circuit can provide a temperature-independent reference current by a current mirror effect; due to the third bipolar junction transistor (Q3) The base voltage (V _BE ) has a negative voltage temperature coefficient characteristic, and a positive voltage temperature coefficient of the third boosting resistor (Ra3) is added, so that the base of the third bipolar junction transistor (Q3) can be compensated. The negative voltage temperature coefficient of the pole voltage (V _BE ) gives a temperature-independent reference voltage (V _ref ).

In addition, the first boosting resistor (Ra1), the second boosting resistor (Ra2), the third boosting resistor (Ra3), the fourth compensating resistor (Rb1), the fifth compensating resistor (Rb2), and the sixth The compensation resistor (Rb3) is made of N-well and has a high temperature coefficient; and the seventh bias resistor (R2) is made of N-type diffusion region (n ⁺ -diffusion). , has a lower temperature coefficient.

The overall structure and design of the present invention for achieving the object of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. First, referring to the third figure, the present invention has a start-up circuit and can simultaneously provide The temperature-independent reference current and reference voltage difference reference circuit 300 is characterized in that it is composed of a start-up circuit 1, a reference current circuit 2 and a reference voltage circuit 3, and can be at a low voltage (less than 1.5 volts). Working under conditions to achieve power saving effect; wherein the starting circuit (please refer to the third figure), comprising three transistor components, respectively being the first P-type gold-oxygen half field effect transistor (Mp), a second P-type gold oxide half field effect transistor (Ms) and a third N-type gold oxide half field effect transistor (Mn); wherein the first P-type gold-oxygen half field effect transistor (Mp) comprises a first gate, a second source, a third drain, and a fourth body. The first gate is electrically coupled to an output of the N-type differential input operational amplifier, the second source and the second four substrate electrically coupled to the positive terminal of the power supply (V _DD), and the third drain is electrically Connected to a first gate terminal of a second P-type MOS field-effect transistor (Ms); the second P-type MOS field-effect transistor (Ms) includes a first gate, a second source, and a first a third gate and a fourth substrate, the first gate is electrically coupled to the third drain terminal of the first P-type MOS field-effect transistor (Mp), and the second source and the fourth substrate are electrically connected Coupling to the positive terminal (V _DD ) of the power supply, and the third drain is electrically coupled to the negative input terminal (Vin-) of the N-type differential input operational amplifier (N-type OPA); The N-type MOS field-effect transistor (Mn) includes a first gate, a second source, a third drain and a fourth substrate. The first gate, the second source and the first The fourth body is electrically coupled to the ground terminal (V _SS ) of the power source, and the third drain is electrically coupled to the third terminal of the first P-type metal oxide half field effect transistor (Mp). .

Please refer to the third diagram, the fourth diagram and the fifth diagram at the same time. When the strap difference reference circuit is in the no-power state, all the transistors enter the off state, so that the current flowing through the transistor is zero; and when the power supply voltage When V _{DD is} gradually increased (please refer to the fourth figure), because the first P-type gold oxide half field effect transistor (Mp) and the third N-type gold oxide half field effect transistor (Mn) are operated in the triode region (Triode) The potential of the gate terminal of the second P-type metal oxide half field effect transistor (Ms) is about half of the power supply voltage (V _DD ); and when the second P-type gold oxide half field effect transistor (Ms) When the gate voltage (V _{MS, G} ) is rapidly increased, the second P-type MOS field-effect transistor (Ms) immediately enters a conducting state, and the source current I _{MS is} rapidly increased (refer to FIG. 5), flowing through The first boosting resistor (Ra1) and the fourth compensating resistor (Rb1) under the N-type differential input operational amplifier (N-type OPA) make the N-type differential input operational amplifier (N-type OPA) the input voltage is started, while producing an output voltage at an output terminal of the N-type differential input operational amplifier (N-type OPA) of (V _{OPA, out),} and further a first start P-type gold-oxygen half field effect transistor (M1), fifth P-type gold-oxygen half-field effect transistor (M2), sixth P-type gold-oxygen half-field effect transistor (M3) and seventh P-type gold-oxygen half-field effect transistor (M4). After the startup work is completed, the gate voltage (V _{MS, G} ) of the second P-type MOS field-effect transistor (Ms) continues to rise, causing the second P-type MOS field-effect transistor (Ms) to enter an off state. The source current I _MS drops to zero; at this time, the first P-type gold-oxygen half-field effect transistor (Mp) operates in the three-turn region, and its function approximates resistance, thus making the second P-type gold-oxygen half-field effect transistor ( The gate voltage (V _{MS, G} ) of Ms) rises synchronously with the rise of the power supply voltage V _DD , prompting the first P-type gold-oxygen half-field effect transistor (Mp) to enter the off state instantaneously, and the startup circuit is separated from the main circuit. It does not affect the normal operation of the differential reference circuit.

The reference current circuit (please refer to the third figure) has a fourth P-type MOS field effect transistor (M1), a fifth P-type MOS field-effect transistor (M2), and a seventh P Type MOS half-field effect transistor (M4), an N-type differential input operational amplifier (N-type OPA), a first boost resistor (Ra1), a second boost resistor (Ra2), and a fourth Compensation resistor (Rb1), a fifth compensation resistor (Rb2), a seventh bias resistor (R2), a first bipolar junction transistor (Q1), and a second bipolar junction transistor (Q2) And electrically connected to form a temperature-independent reference current (I _ref ), wherein the fourth P-type MOS field-effect transistor (M1) includes a first gate, a second source, and a a third drain is electrically coupled to the output of the operational amplifier of the N-type differential input, and the second source is electrically coupled to the fourth substrate The positive terminal (V _DD ) of the power supply, and the third drain is electrically coupled to the third terminal of the second P-type MOS field-effect transistor (Ms) and the operational amplifier of the N-type differential input The negative input terminal (Vin-); the fifth P type The oxygen half field effect transistor (M2) includes a first gate, a second source, a third drain and a fourth substrate, and the first gate is electrically coupled to the N-type differential input operation An output of the amplifier (N-type OPA), the second source and the fourth substrate are electrically coupled to the positive terminal (V _DD ) of the power source, and the third drain is electrically coupled to the N-type difference a positive input terminal (Vin+) of an operationally input operational amplifier (N-type OPA); the seventh P-type MOS half-effect transistor (M4) includes a first gate, a second source, and a third 汲The first gate is electrically coupled to the output of the operational amplifier of the N-type differential input, and the second source and the fourth substrate are electrically coupled to the positive terminal of the power supply (V) _DD ), the third drain is electrically coupled to the output of the reference current circuit (I _ref ); the N-type differential input operational amplifier (N-type OPA) includes a negative input (Vin-) The positive input terminal (Vin+) and the output terminal (V _{OPA, out} ) and the like, the negative input terminal (Vin-) is simultaneously electrically coupled to the third P-type metal oxide half field effect transistor (Ms)汲 extreme, the fourth P-type gold oxygen half-field effect The third terminal of the transistor (M1) is connected to the first end of the first boosting resistor (Ra1), and the positive input terminal (Vin+) is simultaneously electrically coupled to the fifth P-type gold-oxygen half field effect transistor (M2). The third terminal is connected to the first end of the second boosting resistor (Ra2), and the output terminal (V _{OPA, out} ) is electrically coupled to the first (Mp), the fourth (M1), and the fifth a first gate terminal of the (M2) and the seventh (M4) P-type metal oxide half field effect transistor; the first boosting resistor (Ra1) includes a first end and a second end, the first end is electrically coupled a negative input terminal (Vin-) of the N-type differential input operational amplifier, and the second end is electrically coupled to the first end of the fourth compensation resistor (Rb1) and the first bipolar junction a second emitter terminal of the crystal (Q1); the second boost resistor (Ra2) includes a first end and a second end, the first end is electrically coupled to the positive input of the operational amplifier of the N-type differential input a terminal (Vin+), wherein the second end is electrically coupled to the first end of the fifth compensating resistor (Rb2) and the first end of the seventh bias resistor (R2); the fourth compensating resistor (Rb1) The first end and the second end are included, and the first end is electrically coupled at the same time a second end of the first boosting resistor (Ra1) and a second emitter of the first bipolar junction transistor (Q1), and the second end is grounded; the fifth compensation resistor (Rb2) includes the first And the second end, the first end is electrically coupled to the second end of the second boosting resistor (Ra2) and the first end of the seventh bias resistor (R2), and the second end The seventh bias resistor (R2) includes a first end and a second end, the first end is electrically coupled to the second end of the second boost resistor (Ra2) and the fifth compensation a first end of the resistor (Rb2), and the second end is electrically coupled to the second emitter end of the second bipolar junction transistor (Q2); the first bipolar junction transistor (Q1) includes a first base (Base), a second emitter (Emitter) and a third collector (Collector), the first base is electrically coupled to the second bipolar junction transistor (Q2) at the same time a first base and a ground end, the second emitter is electrically coupled to the second end of the first boosting resistor (Ra1) and the first end of the fourth compensation resistor (Rb1), and the third set Extremely grounded; the second bipolar junction transistor (Q2) includes a first base (Bas e), a second emitter (Emitter) and a third collector (collector), the first base is simultaneously electrically coupled to the first base of the first bipolar junction transistor (Q1) and grounded The second emitter is electrically coupled to the second end of the seventh bias resistor (R2), and the third collector is grounded.

The reference voltage circuit has a fourth P-type gold-oxygen half field effect transistor (M1), a fifth P-type gold-oxygen half-field effect transistor (M2), and a sixth P-type gold-oxygen half-field effect transistor ( M3), an N-type differential input operational amplifier (N-type OPA), a first boost resistor (Ra1), a second boost resistor (Ra2), a third boost resistor (Ra3), and a a fourth compensation resistor (Rb1), a fifth compensation resistor (Rb2), a sixth compensation resistor (Rb3), a seventh bias resistor (R2), a first bipolar junction transistor (Q1), a The second bipolar junction transistor (Q2) and a third bipolar junction transistor (Q3) are electrically connected; wherein the fourth P-type gold oxide half field effect transistor (M1), Five P-type gold-oxygen half-field effect transistor (M2), N-type differential input operational amplifier (N-type OPA), first boost resistor (Ra1), second boost resistor (Ra2), fourth compensation resistor Electrical connection between (Rb1), fifth compensation resistor (Rb2), seventh bias resistor (R2), first bipolar junction transistor (Q1) and second bipolar junction transistor (Q2) The method is the same as the connection method of the reference current circuit, and will not be described again. The sixth P-type MOS field-effect transistor (M3) includes a first gate, a second source, a third drain, and a fourth substrate. The first gate is electrically coupled to the first gate. An output terminal of the N-type differential input operational amplifier, the second source and the fourth substrate are electrically coupled to the positive terminal (V _DD ) of the power supply, and the third drain is electrically coupled to the reference voltage An output terminal (V _ref ) of the circuit; the third boosting resistor (Ra3) includes a first end and a second end, the first end being electrically coupled to the output end (V _ref ) of the reference voltage circuit, and The second end is electrically coupled to the first end of the sixth compensating resistor (Rb3) and the second end of the third bipolar junction transistor (Q3); the sixth compensating resistor (Rb3) includes One end and a second end, the first end is electrically coupled to the second end of the third boosting resistor (Ra3) and the second emitter of the third bipolar junction transistor (Q3), The second end is grounded; the third bipolar junction transistor (Q3) includes a first base (Base), a second emitter (Emitter) and a third collector (Collector). a base is grounded, and the second emitter is simultaneously electrically To a third boost resistor (Ra3,) the second end of the sixth compensating resistors (Rb3) of a first end, and the third set of electrodes is grounded.

The first boosting resistor (Ra1) and the second boosting resistor (Ra2) are used to boost the bias potential of the N-type differential input operational amplifier (N-type OPA), and the third boosting The resistor (Ra3) is used to compensate the base voltage of the third bipolar junction transistor (Q3). That is, the base voltages of the first bipolar junction transistor (Q1), the second bipolar junction transistor (Q2), and the third bipolar junction transistor (Q3) all have a negative voltage temperature. The coefficient characteristic causes the current flowing through the fourth compensation resistor (Rb1), the fifth compensation resistor (Rb2) and the sixth compensation resistor (Rb3) to have a negative current temperature coefficient, and a positive current flowing through the seventh bias resistor The temperature coefficient (the temperature coefficient of the positive voltage generated by the base potential difference between the first bipolar junction transistor (Q1) and the second bipolar junction transistor (Q2)) can be obtained independently of the temperature change. Reference current. Furthermore, since the current flowing through the third boosting resistor (Ra3) is a reference current independent of the temperature change, the voltage across the third boosting resistor (Ra3) exhibits a positive voltage temperature coefficient, which can be used to compensate for the third double The negative voltage temperature coefficient of the base voltage of the pole junction transistor (Q3), thereby obtaining a reference voltage (V _ref ) independent of the temperature change. Please refer to the sixth figure. When the compensation resistor (Rb series) is not added, the variability of the output reference voltage to the temperature change is quite large (the output reference voltage before compensation); and after the compensation resistor is added, the output reference voltage is obviously made. The change in the amount of temperature change is reduced (the compensated output reference voltage) to achieve the compensation effect. Please refer to the seventh figure, which is the output result of the measured reference voltage to temperature change after the circuit is fabricated into a wafer; the average of the difference reference voltage is between 0 °C and 100 °C in the temperature range. The output value is approximately 0.8886 volts (V), and the maximum variation of the output reference voltage due to temperature changes is 4.35 microvolts (mV); if the temperature range is between 30 ° C and 100 ° C, the differential reference voltage The average output value is about 0.88876 volts (V), and the maximum variation of the output voltage due to temperature changes is 0.8 microvolts (mV), which shows that the output reference voltage has reached a stable compensation effect. The eighth figure shows the output result of the output reference voltage measured by the circuit chip to the power supply voltage. It can be known from the output result that the difference reference circuit can be started when the power supply voltage is 1.35 volts. That is, the band difference reference circuit can be operated under low voltage conditions to achieve power saving effect. The ninth figure shows the current output result of the output reference current (nA) measured by the circuit chip and the temperature change (°C). It can be known from the output result that the current output of the band difference reference circuit is quite stable. , has achieved the compensation effect.

Next, please refer to the tenth figure, which is a circuit implementation diagram of an operational amplifier (600) with an N-type differential input used in the present invention, which is composed of a telescope amplification circuit, an output amplification circuit and a compensation circuit. The mirror amplification circuit is composed of an eighth P-type gold-oxygen half field effect transistor (M601), a ninth P-type gold-oxygen half-field effect transistor (M602), and a tenth N-type gold-oxygen half-field effect transistor (M603). And an eleventh N-type gold oxide half field effect transistor (M604) and a twelfth N-type gold oxygen half field effect transistor (M605) and other isoelectric crystals; wherein the eighth P type The metal oxide half field effect transistor (M601) includes a first gate, a second source, a third drain and a fourth body. The first gate is electrically coupled to the ninth a first gate of a P-type gold oxide half field effect transistor (M602), a third gate of the eighth P-type gold-oxygen half field effect transistor (M601), and the tenth N-type gold oxide half field effect transistor (M603) a third drain, the second source and the fourth substrate are electrically coupled to the positive terminal (V _DD ) of the power source, and the third drain is electrically coupled to the eighth P-type gold oxide The first gate of the half field effect transistor (M601), the first gate of the ninth P-type gold oxide half field effect transistor (M602), and the third of the tenth N-type gold oxide half field effect transistor (M603) Bungee pole; the ninth P-type gold oxide half field effect transistor (M602) includes a first gate, a second source, a third drain, and a fourth body, the first gate being electrically coupled to the eighth P-type MOS field-effect transistor (M601) The first gate and the third drain and the third drain of the tenth N-type MOS field-effect transistor (M603), the second source and the fourth substrate are electrically coupled to the positive terminal of the power source ( V _DD ), and the third drain is electrically coupled to the third drain of the eleventh N-type metal oxide half field effect transistor (M604), the thirteenth P-type gold oxide half field effect transistor a first gate of (M606) and a second source of the fifteenth P-type MOS field-effect transistor (M_Rc); the tenth N-type MOS field-effect transistor (M603) includes a first gate a second source, a third drain, and a fourth body. The first gate is electrically coupled to the first end (Vin-) of the first boost resistor (Ra1). The second source and the fourth substrate are simultaneously electrically coupled to the second source of the eleventh N-type metal oxide half field effect transistor (M604) and the twelfth N-type gold oxide half field effect transistor (M605) a third drain, the third drain is electrically coupled to the eighth P-type metal oxide half field effect transistor a first gate and a third drain of (M601); the eleventh N-type metal oxide half field effect transistor (M604) includes a first gate, a second source, a third drain and a first a fourth body electrically coupled to the first end (Vin+) of the second boosting resistor (Ra2), the second source and the fourth substrate being electrically coupled to the tenth a second source of the N-type gold-oxygen half field effect transistor (M603) and a third drain of the twelfth N-type gold-oxygen half field effect transistor (M605), the third drain is electrically coupled to The third source of the ninth P-type gold oxide half field effect transistor (M602), the second source of the fifteenth P-type gold oxide half field effect transistor (M_Rc), and the thirteenth P-type gold oxide half field effect transistor a first gate of (M606); the twelfth N-type gold oxide half field effect transistor (M605) includes a first gate, a second source, a third drain, and a fourth substrate The first gate is electrically coupled to the bias voltage (Vbias) and the first gate of the fourteenth N-type MOS field-effect transistor (M607), the second source and the fourth substrate At the same time, it is electrically coupled to the grounding end, and the third drain is electrically coupled to the first The second source of the N-type metal-oxide-semiconductor field effect transistor (M603) and a second electrode of the source electrode of the eleventh N-type metal-oxide-semiconductor field effect transistor (M604) is.

The output amplifying circuit is composed of a thirteenth P-type gold-oxygen half field effect transistor (M606) and a fourteenth N-type gold-oxygen half field effect transistor (M607) and other transistors; The thirteenth P-type MOS field effect transistor (M606) includes a first gate, a second source, a third drain and a fourth substrate. The first gate is electrically coupled at the same time. Receiving a third drain of the ninth P-type metal oxide half field effect transistor (M602), a third drain of the eleventh N-type gold-oxygen half field effect transistor (M604), and the fifteenth P-type gold a second source of the oxygen half field effect transistor (M_Rc), the second source and the fourth substrate are electrically coupled to the positive terminal (V _DD ) of the power source, and the third drain is electrically coupled to the a first end of the first compensation capacitor (Cc), a first gate of the fourth P-type MOS field-effect transistor (M1), and a first of the fifth P-type MOS field-effect transistor (M2) The gate is the third drain of the fourteenth N-type gold-oxygen half field effect transistor (M607). The fourteenth N-type metal oxide half field effect transistor (M607) includes a first gate, a second source, a third drain and a fourth substrate. The first gate is simultaneously electrically And coupled to the first gate of the twelfth N-type MOS field-effect transistor (M605), the second source and the fourth substrate are electrically coupled to the ground end (V _SS ) of the power source, and the The third gate is electrically coupled to the first end of the first compensation capacitor (Cc), the first gate of the fourth P-type MOS field-effect transistor (M1), and the fifth P-type gold oxide The first gate of the half field effect transistor (M2) and the third gate of the thirteenth P type gold oxide half field effect transistor (M606).

The compensation circuit is composed of a fifteenth P-type MOS field-effect transistor (M_Rc) and a first compensation capacitor (Cc) and the like; wherein the fifteenth P-type MOS half-field effect The transistor (M_Rc) includes a first gate, a second source, a third drain, and a fourth body. The first gate is electrically coupled to the ground, the second source. Simultaneously electrically coupled to the third drain of the ninth P-type MOS field-effect transistor (M602), the third drain of the eleventh N-type MOS field-effect transistor (M604), and the tenth a first gate of the three P-type MOS field-effect transistor (M606), the third gate is electrically coupled to the second end of the first compensation capacitor (Cc), and the fourth substrate is electrically coupled to a positive terminal (V _DD ) of the power supply; the first compensation capacitor (Cc) includes a first end and a second end, the first end being electrically coupled to the thirteenth P-type MOS field-effect transistor (M606) a third gate, a first gate of the fourth P-type MOS field-effect transistor (M1), a first gate of the fifth P-type MOS field-effect transistor (M2), and the tenth The third pole of the four N-type gold oxygen half field effect transistor (M607), Is electrically coupled to the second end of the fifteenth P-type metal oxide semiconductor field effect transistor (M_Rc) of the third drain.

Next, the formula derivation of the difference reference current of the present invention will be described. First, assume that the transistors in the third figure are all ideal, the transistors M1, M2 and M3 are the same, the resistors Ra1 and Ra2 are the same, the resistors Rb1 and Rb2 are the same, and the positive and negative inputs of the amplifier are virtual short circuits (Vin+=Vin-). ,then

V _EB1 =V _EB2 +V _R2 .......................................... ......(Formula 1)

I _Rb1 =I _Rb2 ............................................. ..............(Formula 2)

I _Ra1 =I _Ra2 ............................................. .................(Formula 3)

I _Ra2 =I _Rb2 +I _R2 .......................................... ...........(Formula 4)

Taking (Formula 4) as an example, the change in temperature (T) is

Since I _Rb2 =V _EB1 /R _b2 and I _R2 =(V _EB1 -V _EB2 )/R ₂ , it can be known that I _Rb2 is a negative current temperature coefficient and there is an adjustment factor R _b2 ; similarly, I _R2 is a positive current Temperature coefficient, and there is an adjustment factor R ₂ . By adjusting the adjustment factor, the temperature change values of I _Rb2 and I _R2 can be canceled, and the current I _Ra2 independent of the temperature change is obtained, via the fifth P-type gold-oxygen half-field effect transistor (M2) and the seventh P-type gold. A current mirror composed of an oxygen half-field effect transistor (M4) mirrors the current I _Ra2 to the output current to obtain a reference current (I _ref ) independent of the temperature change.

Referring to the third figure, the reference voltage (V _ref ) of the present invention can be obtained after adding the third boosting resistor (Ra3).

V _ref =I _Ra3 ×R _a3 +V _BE3 ....................................... ...............(Formula 6)

Its change to temperature (T) is

Where I _Ra3 is a reference current independent of temperature changes ( ), the resistor R _a3 is a positive temperature coefficient resistor, and the base voltage of the third bipolar junction transistor (Q3) is a negative voltage temperature coefficient ( By appropriately selecting the values of R _a3 and I _Ra3 , an output reference voltage V _ref independent of the temperature change can be obtained. It is worth noting that all boost resistors (R _a series) and compensation resistors (R _b series) require N-well resistors with a higher temperature coefficient, while the seventh bias resistors require An N-type diffusion region (n ⁺ -diffusion) having a lower temperature coefficient is employed.

The foregoing is a detailed description of the preferred embodiments of the present invention, and the scope of the present invention is not to be construed as being limited to the scope of the present invention. Many modifications and variations of the present invention are possible. Therefore, the present invention covers such modifications and variations as may be apparent from the scope of the appended claims and the equivalents thereof.

Further, in order to make the present invention more expressive and practical, the advantages of its implementation are listed as follows:

1. The present invention is provided with a start up circuit composed of three components. When the differential reference circuit is in normal operation, the startup circuit enters a closed state, which does not affect the normal operation of other circuits; Less, with the advantages of simple architecture, power saving and quick start.

2. The present invention has both a reference voltage and a reference current whose output is independent of temperature variation, which can expand the application range of the present invention, improve the added value of the present invention, and have the advantages of miniaturization and the like.

3. The invention has better temperature compensation function, can make the output value of the reference voltage relatively stable, and can work under low voltage, reduce power consumption, has energy-saving effect, and meets the actual needs of the industrial and commercial circles or industries. With industrial use value.

In summary, the present invention has achieved the desired effect under the prior art structure, and is also unfamiliar to those skilled in the art; further, the present invention is progressive, practical, and obvious. Has met the application requirements of the invention patent, and filed an invention application according to law.

200. . . Low voltage band difference reference circuit

A201. . . Operational Amplifier

M201, M202, M203. . . Gold oxide semi-effect transistor

Q201, Q202. . . Bipolar junction transistor

R201, R202, R203, R204, R205, R206. . . resistance

300. . . Differential reference circuit

1. . . Startup circuit

2. . . Reference current circuit

3. . . Reference voltage circuit

Mp. . . First P-type gold oxide half field effect transistor

Ms. . . Second P-type gold oxide half field effect transistor

Mn. . . Third N-type gold oxygen half field effect transistor

M1. . . Fourth P-type gold oxide half field effect transistor

M2. . . Fifth P-type gold oxide half field effect transistor

M3. . . Sixth P-type gold oxide half field effect transistor

M4. . . The seventh P-type gold oxygen half field effect transistor

OPA. . . N-type input operational amplifier

Ra1. . . First boost resistor

Ra2. . . Second boost resistor

Ra3. . . Third boost resistor

Rb1. . . Fourth compensation resistor

Rb2. . . Fifth compensation resistor

Rb3. . . Sixth compensation resistor

R2. . . Seventh bias resistor

Q1. . . First bipolar junction transistor

Q2. . . Second bipolar junction transistor

Q3. . . Third bipolar junction transistor

V _DD . . . Positive end of the power supply

V _SS . . . Ground terminal of the power supply

I _ref . . . Reference current

V _ref . . . Reference voltage

Cc. . . First compensation capacitor

V _bias . . . Bias voltage

600. . . Operational amplifier with N-type differential input

M601. . . The eighth P-type gold oxygen half field effect transistor

M602. . . Ninth P-type gold oxide half field effect transistor

M603. . . Tenth N-type gold oxygen half field effect transistor

M604. . . The eleventh N-type gold oxygen half field effect transistor

M605. . . Twelfth N-type gold oxygen half field effect transistor

M606. . . The thirteenth P-type gold oxygen half field effect transistor

M607. . . The fourteenth N-type gold oxygen half field effect transistor

M_Rc. . . Fifteenth P-type gold oxide half field effect transistor

The first figure is a basic architecture diagram of a conventional reference circuit with a difference.

The second figure is a circuit diagram of a conventional low voltage band difference reference circuit.

The third figure is a circuit implementation diagram (representative diagram) of the present invention.

The fourth figure is a voltage output waveform diagram of the startup circuit of the present invention.

The fifth figure is a current output waveform diagram of the startup circuit of the present invention.

The sixth graph is an output waveform diagram of the reference voltage output versus temperature change before and after compensation according to the present invention.

The seventh figure is a graph showing the voltage output of the reference voltage versus temperature change of the present invention.

The eighth figure is a graph showing the voltage output measured by the reference voltage of the present invention with respect to the power supply voltage.

The ninth graph is a graph showing the current output of the reference current versus temperature change of the present invention.

The tenth figure is a circuit implementation diagram of an operational amplifier of an N-type differential input used in the present invention.

1. . . Startup circuit

2. . . Reference current circuit

3. . . Reference voltage circuit

Mp. . . First P-type gold oxide half field effect transistor

Ms. . . Second P-type gold oxide half field effect transistor

Mn. . . Third N-type gold oxygen half field effect transistor

M1. . . Fourth P-type gold oxide half field effect transistor

M2. . . Fifth P-type gold oxide half field effect transistor

M3. . . Sixth P-type gold oxide half field effect transistor

M4. . . The seventh P-type gold oxygen half field effect transistor

OPA. . . N-type differential input operational amplifier

Ra1. . . First boost resistor

Ra2. . . Second boost resistor

Ra3. . . Third boost resistor

Rb1. . . Fourth compensation resistor

Rb2. . . Fifth compensation resistor

Rb3. . . Sixth compensation resistor

R2. . . Seventh bias resistor

Q1. . . First bipolar junction transistor

Q2. . . Second bipolar junction transistor

Q3. . . Third bipolar junction transistor

V _DD . . . Positive voltage

V _SS . . . Voltage ground

I _ref . . . Reference current

V _ref . . . Reference voltage

300. . . Differential reference circuit

Claims (8)

A band difference reference circuit having a start-up circuit and simultaneously providing a reference current and a reference voltage independent of temperature, characterized in that: a start circuit, a reference current circuit and a reference voltage circuit; wherein the start circuit It is composed of two P-type field effect transistors and an N-type field effect transistor, and is turned off after starting the band difference reference circuit; the reference current circuit has three P-type MOS half-field effects The transistor, an N-type differential input operational amplifier, two boost resistors, two compensation resistors, a bias resistor and two bipolar junction transistors are electrically connected to each other to output and change temperature. Independent reference current; the reference voltage circuit has a P-type MOSFET, an N-type differential input operational amplifier, three boost resistors, three compensation resistors, a bias resistor and three It consists of electrical connections such as bipolar junction transistors, which can output a reference voltage independent of temperature changes. A difference reference circuit having a start-up circuit and a temperature-independent reference current and a reference voltage, as described in claim 1, wherein the start-up circuit includes a first P-type MOS field-effect transistor, and a second a P-type MOS half-field effect transistor and a third N-type MOS half-field effect transistor; the first P-type MOS half-field effect transistor includes a first gate, a second source, and a third drain a fourth substrate electrically coupled to an output of the N-type differential input operational amplifier, the second source and the fourth substrate being electrically coupled to the positive terminal of the power supply, and the first The third pole is electrically coupled to the first gate terminal of the second P-type metal oxide half field effect transistor; the second P-type gold oxide half field effect transistor includes a first gate, a second source, and a first gate a third drain and a fourth substrate, the first gate is electrically coupled to the third drain of the first P-type MOS field, and the second source is electrically coupled to the fourth substrate To the positive terminal of the power supply, the third drain is electrically coupled to the negative input terminal of the operational amplifier of the N-type differential input; The third N-type metal oxide half field effect transistor includes a first gate, a second source, a third drain and a fourth substrate, and the first gate, the second source and the fourth substrate are simultaneously charged The third drain is electrically coupled to the third terminal of the first P-type MOS field-effect transistor. A difference reference circuit having a start-up circuit and a temperature-independent reference current and a reference voltage, as described in claim 1, wherein the reference current circuit includes a fourth P-type MOS field-effect transistor, Five P-type gold oxygen half field effect transistor, seventh P type gold oxygen half field effect transistor, N type differential input operational amplifier, first boosting resistor, second boosting resistor, fourth compensating resistor, fifth compensation a resistor, a seventh bias resistor, a first bipolar junction transistor, a second bipolar junction transistor, etc.; the fourth P-type MOS half-field effect transistor includes a first gate and a second source a third drain and a fourth substrate, the first gate is electrically coupled to the output of the N-type differential input operational amplifier, and the second source and the fourth substrate are electrically coupled to the power supply a positive terminal, and the third drain is electrically coupled to a third 汲 terminal of the second P-type MOS field-effect transistor and a negative input terminal of the N-type differential input operational amplifier; The P-type gold-oxygen half field effect transistor includes a first gate, a second source, and a third a first gate is electrically coupled to an output of the N-type differential input operational amplifier, and the second source and the fourth substrate are electrically coupled to the positive terminal of the power supply, The third drain is electrically coupled to the positive input terminal of the operational amplifier of the N-type differential input; the seventh P-type gold-oxygen half field effect transistor includes a first gate and a second source. a third drain and a fourth substrate, the first gate is electrically coupled to the output of the N-type differential input operational amplifier, and the second source and the fourth substrate are electrically coupled to the power supply a positive terminal, wherein the third drain is electrically coupled to the current output end of the reference current circuit; the operational amplifier of the N-type differential input includes an anode input terminal, a positive input terminal, and an output terminal. The negative input terminal is electrically coupled to the third 汲 terminal of the second P-type MOS field-effect transistor, the third 汲 terminal of the fourth P-type MOS field-effect transistor, and the first of the first step-up resistor The positive input terminal is simultaneously electrically coupled to the third 汲 terminal and the second liter of the fifth P-type MOS field-effect transistor a first end of the resistor, and the output end is electrically coupled to the first gate terminal of the first, fourth, fifth, and seventh P-type MOS transistors; the first boost resistor includes a first end and a second end, the first end is electrically coupled to the negative input terminal of the N-type differential input operational amplifier, and the second end is electrically coupled to the fourth compensation resistor a second end of the first bipolar junction transistor; the second boosting resistor includes a first end and a second end, the first end is electrically coupled to the N-type differential input a positive input terminal of the operational amplifier, and the second end is electrically coupled to the first end of the fifth compensation resistor and the first end of the seventh bias resistor; the fourth compensation resistor includes a first end and a first end The second end is electrically coupled to the second end of the first boosting resistor and the second emitter of the first bipolar junction transistor, and the second end is grounded; The fifth compensation resistor includes a first end and a second end, the first end is electrically coupled to the second end of the second boost resistor and the seventh bias a first end of the resistor, and the second end is grounded; the seventh bias resistor includes a first end and a second end, the first end is simultaneously electrically coupled to the second of the second boost resistor a first end of the fifth compensation resistor, and the second end is electrically coupled to the second emitter of the second bipolar junction transistor; the first bipolar junction transistor includes a first a base, a second emitter and a third collector, the first base is simultaneously electrically coupled to the first base and the ground of the second bipolar junction transistor, and the second emitter is simultaneously The second terminal is coupled to the first end of the first boosting resistor and the first end of the fourth compensating resistor, and the third collector is grounded; the second bipolar junction transistor includes a first base and a first a second emitter and a third collector, the first base is electrically coupled to the first base and the ground of the first bipolar junction transistor, and the second emitter is electrically coupled to the first The second end of the seven bias resistor, and the third collector is grounded. A difference reference circuit having a start-up circuit and a temperature-independent reference current and a reference voltage, as described in claim 1, wherein the reference voltage circuit includes a fourth P-type MOS field-effect transistor, Five P-type gold-oxygen half-field effect transistor, sixth P-type gold-oxygen half-field effect transistor, N-type differential input operational amplifier, first boosting resistor, second boosting resistor, third boosting resistor, fourth a compensation resistor, a fifth compensation resistor, a sixth compensation resistor, a seventh bias resistor, a first bipolar junction transistor, a second bipolar junction transistor, and a third bipolar junction transistor; The P-type MOS field-effect transistor includes a first gate, a second source, a third drain, and a fourth substrate. The first gate is electrically coupled to the N-type differential input operation. An output end of the amplifier, the second source and the fourth substrate are electrically coupled to the positive end of the power source, and the third drain is electrically coupled to the third P-type MOS field-effect transistor汲 extreme and the negative input terminal of the N-type differential input operational amplifier; the fifth P-type gold oxide The half field effect transistor includes a first gate, a second source, a third drain and a fourth substrate. The first gate is electrically coupled to the output of the N-type differential input operational amplifier. The second source and the fourth substrate are electrically coupled to the positive terminal of the power supply, and the third drain is electrically coupled to the positive input terminal of the operational amplifier of the N-type differential input; the sixth P The MOS field-effect transistor includes a first gate, a second source, a third drain and a fourth substrate, and the first gate is electrically coupled to the N-type differential input operational amplifier The second source and the fourth substrate are electrically coupled to the positive end of the power supply, and the third drain is electrically coupled to the voltage output of the reference voltage circuit; the N-type differential input The operational amplifier includes an anode input terminal, a positive input terminal and an output terminal, and the negative input terminal is electrically coupled to the third 汲 terminal of the second P-type MOS field-effect transistor, and the fourth P-type The third end of the gold-oxygen half-field effect transistor and the first end of the first step-up resistor, the positive input is electrically coupled at the same time Received the fifth P-type MOS half-field effect a third end of the transistor and a first end of the second boost resistor, and the output is electrically coupled to the first, fourth, fifth, and sixth P-type MOS half-effect transistors a first boosting resistor includes a first end and a second end, the first end electrically coupled to the negative input of the operational amplifier of the N-type differential input, and the second end Simultaneously coupled to the first end of the fourth compensating resistor and the second end of the first bipolar junction transistor; the second boosting resistor includes a first end and a second end, the first end Electrically coupled to the positive input terminal of the N-type differential input operational amplifier, and the second end is electrically coupled to the first end of the fifth compensation resistor and the first end of the seventh bias resistor; The fourth compensation resistor includes a first end and a second end. The first end is electrically coupled to the second end of the first boost resistor and the second end of the first bipolar junction transistor. Extremely, the second end is grounded; the fifth compensation resistor includes a first end and a second end, and the first end is electrically coupled to the second end simultaneously a second end of the resistor and a first end of the seventh bias resistor, and the second end is grounded; the sixth compensating resistor includes a first end and a second end, the first end is electrically coupled at the same time a second end of the third boosting resistor and a second emitter of the third bipolar junction transistor, and the second end is grounded; the seventh bias resistor includes a first end and a second end The first end is electrically coupled to the second end of the second boost resistor and the first end of the fifth compensating resistor, and the second end is electrically coupled to the second bipolar junction a second emitter of the transistor; the first bipolar junction transistor includes a first base, a second emitter and a third collector, the first base being electrically coupled to the second pair simultaneously a first base and a ground end of the pole-connecting transistor, the second emitter being electrically coupled to the second end of the first boosting resistor and the first end of the fourth compensating resistor, and the third set The second bipolar junction transistor includes a first base, a second emitter and a third collector, and the first base is electrically coupled to the first bipolar The first base and the ground terminal of the transistor, the second emitter terminal is electrically coupled to the second bias resistor of the seventh, and the third header grounded; the third bipolar The junction transistor includes a first base, a second emitter and a third collector. The first base is grounded, and the second emitter is electrically coupled to the second end of the third boost resistor. And a first end of the sixth compensation resistor, and the third collector is grounded. A reference current circuit having a start-up circuit and a temperature-independent reference current and a reference voltage, as described in claim 3, wherein the fourth compensation resistor, the fifth compensation resistor, and the sixth compensation resistor are used The negative current temperature coefficient is generated, and the positive current temperature coefficient generated by the base potential difference of the three bipolar junction transistors can be easily canceled to obtain a reference current irrespective of the temperature change. A reference voltage circuit having a start-up circuit and a temperature-independent reference current and a reference voltage, as described in claim 4, wherein the first boost resistor and the second boost resistor are used to boost the N The input and output potentials of the positive and negative terminals of the differential input operational amplifier; further, since the current flowing through the third boosting resistor is a reference current independent of the temperature change, the voltage across the third boosting resistor exhibits a positive voltage The temperature coefficient can be used to compensate the negative voltage temperature coefficient of the base voltage of the third bipolar junction transistor to obtain a reference voltage independent of the temperature change. A reference voltage circuit having a start-up circuit and a temperature-independent reference current and a reference voltage as described in claim 4, wherein the operational amplifier having an N-type differential input is a mirror amplification circuit and an output The amplification circuit and the compensation circuit are composed of: an eighth P-type gold oxygen half field effect transistor, a ninth P-type gold oxygen half field effect transistor, a tenth N-type gold oxygen half field effect transistor, An eleventh N-type gold oxygen half field effect transistor is electrically connected with a twelfth N-type gold oxygen half field effect transistor isoelectric crystal; the output amplification circuit is composed of a thirteenth P-type gold oxygen half field effect The transistor is electrically connected with a fourteenth N-type gold-oxygen half field effect transistor isoelectric crystal; the compensation circuit comprises a fifteenth P-type gold-oxygen half field effect transistor and a first compensation capacitor and the like. Electrical connection The eighth P-type MOS field-effect transistor includes a first gate, a second source, a third drain and a fourth substrate, and the first gate is electrically coupled at the same time. a first gate of the ninth P-type MOS field effect transistor, a third gate of the eighth P-type MOS field-effect transistor, and a third 该 of the tenth N-type MOS field-effect transistor The second source and the fourth substrate are electrically coupled to the positive end of the power source, and the third drain is electrically coupled to the first gate of the eighth P-type metal oxide half field effect transistor a first gate of the ninth P-type metal oxide half field effect transistor and a third gate of the tenth N-type gold oxide half field effect transistor; the ninth P-type gold-oxygen half field effect transistor includes a first a gate, a second source, a third drain and a fourth substrate, the first gate being electrically coupled to the first gate and the third of the eighth P-type MOS field-effect transistor a drain and a third drain of the tenth N-type MOS field-effect transistor, the second source and the fourth substrate are electrically coupled to the positive terminal of the power source, and the third drain is electrically coupled at the same time Connected to the eleventh a third drain of the N-type gold-oxygen half field effect transistor, a first gate of the thirteenth P-type gold-oxygen half field effect transistor, and a second source of the fifteenth P-type gold-oxygen half field effect transistor; The tenth N-type MOS field effect transistor includes a first gate, a second source, a third drain and a fourth substrate, and the first gate is electrically coupled to the first boost a first end of the resistor, the second source and the fourth substrate are simultaneously electrically coupled to the second source of the eleventh N-type metal oxide half field effect transistor, and the twelfth N-type metal oxide half field effect a third drain of the crystal, the third drain is electrically coupled to the first gate and the third drain of the eighth P-type metal oxide half field effect transistor; the eleventh N-type gold oxygen half-field power The crystal includes a first gate, a second source, a third drain, and a fourth substrate. The first gate is electrically coupled to the first end of the second boost resistor, the second source The pole and the fourth substrate are electrically coupled to the second source of the tenth N-type metal oxide half field effect transistor and the third drain of the twelfth N-type gold oxygen half field effect transistor, the third Extremely electrically coupled to the first The second source of the third buck and the fifteenth P-type MOS half-effect transistor of the N-type P-type gold-oxygen half-field effect transistor The first gate of the thirteenth P-type gold-oxygen half field effect transistor; the twelfth N-type gold-oxygen half field effect transistor comprises a first gate, a second source, a third drain and a fourth a first gate electrically coupled to a bias voltage and a first gate of the fourteenth N-type MOSFET, the second source and the fourth substrate being electrically coupled at the same time To the ground, the third drain is electrically coupled to the second source of the tenth N-type metal oxide half field effect transistor and the second source of the eleventh N-type gold oxide half field effect transistor; The thirteenth P-type MOSFET has a first gate, a second source, a third drain and a fourth substrate, and the first gate is electrically coupled to the first gate at the same time. a third drain of the ninth P-type gold oxide half field effect transistor, a third drain of the eleventh N-type gold oxide half field effect transistor, and a second source of the fifteenth P-type gold oxide half field effect transistor The second source and the fourth substrate are electrically coupled to the positive end of the power source, and the third drain is electrically coupled to the first end of the first compensation capacitor, the fourth P-type gold Oxygen half field effect a first gate of the crystal, a first gate of the fifth P-type MOS field effect transistor, and a third drain of the fourteenth N-type MOS field-effect transistor; the fourteenth N-type gold oxide The half field effect transistor includes a first gate, a second source, a third drain and a fourth substrate, and the first gate is electrically coupled to the twelfth N-type metal oxide half field power a first gate of the crystal, the second source and the fourth substrate are electrically coupled to the ground of the power source, and the third drain is electrically coupled to the first end of the first compensation capacitor, a first gate of the fourth P-type MOS field effect transistor, a first gate of the fifth P-type MOS field-effect transistor, and a third 该 of the thirteenth P-type MOS field-effect transistor The fifteenth P-type metal oxide half field effect transistor includes a first gate, a second source, a third drain and a fourth substrate, and the first gate is electrically coupled a grounding end, the second source is electrically coupled to the third drain of the ninth P-type MOS field-effect transistor, the third drain of the eleventh N-type MOS field-effect transistor, and the second drain Thirteenth P type Oxide semiconductor field effect transistor has a first gate electrode, the third drain is electrically coupled to the first compensation capacitor The second end is electrically coupled to the positive end of the power supply; the first compensation capacitor includes a first end and a second end, and the first end is electrically coupled to the thirteenth P-type gold a third drain of the oxygen half field effect transistor, a first gate of the fourth P-type metal oxide half field effect transistor, a first gate of the fifth P-type metal oxide half field effect transistor, and the fourteenth N The third drain of the type of gold oxide half field effect transistor, the second end is electrically coupled to the third drain of the fifteenth P type gold oxide half field effect transistor. A difference reference circuit having a start-up circuit and a temperature-independent reference current and a reference voltage, as described in claim 1, wherein the step-up resistor and the compensation resistor are both N-wells (N-well Made of a higher temperature coefficient; and the seventh bias resistor is made of an N-type diffusion region (n ⁺ -diffusion) with a lower temperature coefficient.