lOL 6. 12 1380268 年月日條正替換頁 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種液晶顯示器及採用該液晶顯示器之 電腦系統。 【先前技術】 液晶顯示器由於具有重量輕、耗電少、韓射低及攜帶 方便等優點而在電腦系統中得到非常廣泛的應用。 通常液晶顯示器係藉由視頻圖形陣列（vide〇 Graphic Array，VGA)介面或數位視頻介面（Digital visual Interface， · DVI)接收來自一電腦主機之視頻訊號，並根據該視頻訊. 號，顯示對應之晝面以供使用者觀看。 凊參閱圖1，係先前技術一種液晶顯示器之結構示意 圖。该液晶顯不器100包括一液晶面板J丨〇、一閘極驅動 窃120、一源極驅動器13〇及一時序控制器15〇。 該液晶面板110包括複數平行間隔設置之閘極線&、 X2 X2m，複數與該閘極線χΐ、X2、…X2m絕緣垂直設置 之資料線Y丨、Y2、…Yh，以及複數由該閘極線&、&、…每 乂2:與5亥倉料線Y,、γ2、...γ2η分隔界定且呈矩陣分佈之晝 素單，170其中’该開極線Χι、、…&阳連接至該閘極 驅=器12G，用於接收該閘極驅動器12G發出之掃描訊號。 該資料線γ】、γ2 ' ..·Υ2η連接至該源極驅動器m，用於接 收該源極驅動器丨3 〇輸出之資料訊號。 該畫素單元17〇包括一薄膜電晶體17卜一晝素電極172 及一公共電極173。該薄膜電晶體m之閘極、源極及汲極 1380268 a 6, 1 9 101 6· < ._ 年月日修正替換頁 分別與该閘極線X/KiUm)、該資料線叫郎叫及該畫 素電極172對應連接。該畫素電極172、該公共電極m及炎 * 於其間之液晶層（圖未示）構成一液晶電容〗74。 該時序控制器W包括H序訊㈣出端155及— •第二時序訊號輸出端156。其中’該第—時序訊號輸出端155 連接至該源極驅動H 130 ’用於輸出該時序㈣器15〇内部 產生之貧料時序控制訊號。該第二時序訊號輸出端156連接 至δ亥閘極驅動器120，用於輸出該時序控制器15〇内部產生 ♦之掃福時序控制訊號。且，該時序控制器15〇藉由一資料總 .線180連接至該源極驅動器丨3〇,該資料總線180用於傳送該 時序控制器150所輸出之視頻訊號。 當该液晶顯示器100工作時，該時序控制器i 5〇通過一 介面電路（圖未示）接收來自一電腦主機之視頻訊號，並根 據該視頻訊號分別產生一掃描時序控制訊號及一資料時序 控制訊號，並進一步藉由該第二時序訊號輸出端15.6及該第 :時序訊號輸出端155分別將該掃描時序控制訊號及該資 料時序控制訊號輸出至該閘極驅動器！ 2 〇及該源極驅動器 130。同時，該時序控制器15〇將該視頻訊號轉換為低振幅 差为 afl 號（Reduced Swing Differential Signal, RSDS)，並藉 •由該資料總線180將該低振幅差分訊號輸出至該源極驅動 器 130 〇 該閘極驅動器120根據其所接收之掃描時序控制訊 號產生複數知杂脈衝訊號，並依序施加至該閘極線X〗、 X2、…X2m。當該掃描脈衝訊號施加至該第ί(1<Κ2πι)條閘 7 (:· 1380268 101 6. 12__ L 年月日修正替換頁 極線兄時，與該閘極線Xi相連接之第i(^k2m)列薄膜電晶 體17!導通。該源極驅動器130將其接收到之低振幅差分= 號轉換成對應之資料電壓，並在該資料時序控制訊號作用 下，將該資料電壓輸出至該第i列畫素單元17〇之晝素電極 172。同時’該公共電極173接收_公共電壓電路（圖未示） 發出之公共電壓。由此，於該畫素單元17〇中，該晝素電極 172與該公共電極173之間形成一灰階電壓，在該灰階電壓 產生之電場作用下，夾於該畫素電極172與該公共電極Η] 間之液晶分子發生旋轉，控制光線通過量以顯示晝面。籲 、然^該液晶顯示器100僅可接受單獨一電腦主機輸出 ，視頻訊號’並對該視頻訊號進行處理從而顯示該視頻訊 f對應之畫面。而在曰常工作中某些特定場合，如進行產 °〇展示或會議控制，需要同時顯示複數電腦主機所輸出之 $頻訊號。由於該液晶顯示器1〇〇不具備分屏同時顯示不 5電腦主機輸出之視頻訊號之功能，因此，在此情況下使 者便品要配備複數液晶顯示器} 來對應該複數電腦主 ’才此滿足畫面顯示需要，該液晶顯示器1 不能滿足多儀齡 功能之顯示要求，給使用者造成許多不便。 【發明内容】 有於此’有必要提供一種可分屏顯示複數電腦主機 ^之視頻訊號’滿足多功能顯示要求之液晶顯示器。 · 同時有必要提供一種使用該液晶顯示器之電腦系統。 及一^種液晶顯示器，其包括一液晶面板、一時序控制器 顯不選擇電路’該時序控制器接收複數視頻訊號，該 JOUZD6 JOUZD6 〇. 年月日條正替換頁 :::擇電？向該時序控制器輪出一顯示模式控制訊號 二J控!】時據該11 *模式控祕號，控制該液晶面板 刀‘·’頁不。亥複數視頻訊號所對應之畫面或全屏顯示其中-視頻訊號所對應之晝面。 -種液晶顯示器’其包括一液晶面板、一時序控制器 :顯不選擇電路，該時序控制器接收複數視頻訊號，該 :兮^擇，路向5亥時序控制器輸出-顯示模式控制訊號， ‘4不_式控制訊號為—第—訊號時，該時序控制器控 制該液晶面板分屏顯示該複數視頻訊號所對應之晝面，當 式控制訊號切換至一第二訊號時’該時序控制器 f制该液晶面板全屏顯示其中一視頻訊號所對應之晝面， ❺該顯示模式控制訊號切換至―第三料 器控制該液晶面板全屏顯示另一視頻訊號所對應之 主撫另種電腦糸統，其包括一第一電腦主機、-第二電腦 =及-液晶顯不器，該液晶顯示器包括一液晶面板、一 二'顯示選擇電路，該時序控制器分別接收該 Ϊ擇==第二電腦主機輸出之視頻訊號，該顯示 =擇電路向②時序控制器輸出—顯示模式控制訊號， ==電^:及該第二電腦主機輸出之視』 主機所輪出之視頻訊號所對應之晝面。 或第二電腦 相較於先前技術，本發明之液晶顯示器增加— 擇電路，並根據該顯示選擇電路輪出之顯示模式控制： l〇L 6. 12 !380268 --—~~1日修毛替換頁 號，控制該液晶面板分屏顯示該複數視頻訊號所對應之晝 面或全屏顯示其中一視頻訊號所對應之畫面。因此 明之液晶顯示器僅採用一顯示器便可實現同時顯示複數^ 頻訊號源所輸出之視頻訊號，克服先前技術在同時顯示複 數視頻訊號源所輸出之視頻訊號時需要配備複數液晶顯示 器而帶來之諸多不便，該液晶顯示器由此滿足多功= 示要求，使得使用者使用起來簡單方便。 相較於先前技術，本發明之電腦系統採用一具有顯示 選擇電路之液晶顯示器，該液晶顯示器可根據該顯示選擇 電路輸出之顯示模式控制訊號，分屏同時顯示二電腦主機 輸出之視頻訊號對應之畫面或全屏顯示其中任一電腦主機 所輸出之視頻訊號所對應之畫面。因此，本發明之電腦系 統僅採用一顯示器便可實現同時顯示該二電腦主機所輸出 之視頻讯號，克服先前技術在同時顯示二電腦主機所輸出 之視頻訊號時需要配備二液晶顯示器而帶來之諸多不便， 該液晶顯示器由此滿足多功能之顯示要求，使得使用者使 用起來簡單方便。 【實施方式】 請參閱圖2,係本發明液晶顯示器第一實施方式之結構 示意圖。該液晶顯示器2〇〇包括一液晶面板21〇、一閘極驅 動器220、一第一源極驅動器23〇、一第二源極驅動器24〇、 一時序控制器250、一顯示選擇電路260、一第一介面電路 280及一第二介面電路29〇。 该液晶面板210包括複數平行間隔設置之閘極線&、 丄柳咖 lot 6. 12 年月日絛正替換頁 X、…’複數與該閘極線Χι、X2、."Xh絕緣垂直設置 之資料線Yl、Y2、...Y2n，以及複數由該閘極線X,、χ2、… X2f該資料線w ·.、分隔衫且呈矩陣分佈之畫 素單^270其中，該閘極線Xl、X2、...X2m連接至該閘極 驅，器220 ’用於接收該閘極驅動器22〇輸出之掃描訊號。 '資料線Y! Y2、... γη連接至該第一源極驅動器，用 於接枚4第-源極驅動器23G輸出之資料訊號。該資料線 Yn+1、Yn+2、…Yh連接至該第二源極驅動器24〇,用於接收 該第二源極驅動器240輸出之資料訊號。 將處於第i列第j行之晝素單元2γ〇記為p(⑶（1<K2m， lSjS2n)，位於第1至11行之所有畫素單元i 一jSn)構成一第一顯示區211，而位於第n+1至2n行之晝素 單元Ρ(α(1^<2ηι，n+KjUn)構成一第二顯示區212。該 畫素單元Ρ(α包括一薄膜電晶體271、一晝素電極272及一 公共電極273。該薄膜電晶體271之閘極、源極及汲極分別 與該閘極線Xi(l 、該資料線Yj(1 g <2η)及該晝素電 極272對應連接。且，該晝素電極272、該公共電極273及夾 於其間之液晶層（圖未示）形成一液晶電容274。 该第一介面電路280及該第二介面電路29〇可為視頻圖 形陣列介面電路或數位視頻介面電路，其分別連接至一第 一視頻訊號源（圖未示）及一第二視頻訊號源（圖未示），並接 收该第一視頻訊號源及該第二視頻訊號源所輸出之視頻訊 號。且’該第一介面電路280及該第二介面電路290具有縮 放功能’其可將所接收之任意解析率之視頻訊號縮放成為 10L 6. 12 1380268 年月 日修正替換頁 —滿足該液晶面板210輸出需要之解析率之視頻訊號。本實 施方式中’縮放後得到之視頻訊號之解析率為2mxn，且該 第一介面電路280及該第二介面電路29〇可於其内部將縮放 _ 後得到之視頻訊號轉換成低壓差分訊號（L〇w v〇hage 、lOL 6. 12 1380268 The following is a replacement page. 9. Description of the Invention: The present invention relates to a liquid crystal display and a computer system using the same. [Prior Art] Liquid crystal displays are widely used in computer systems due to their advantages of light weight, low power consumption, low Hanni shooting, and portability. Generally, a liquid crystal display receives a video signal from a host computer through a video graphics array (VGA) interface or a digital video interface (DVI), and displays corresponding signals according to the video signal number. The face is for the user to watch. Referring to Fig. 1, there is shown a schematic structural view of a liquid crystal display of the prior art. The liquid crystal display device 100 includes a liquid crystal panel J, a gate drive 120, a source driver 13A, and a timing controller 15A. The liquid crystal panel 110 includes a plurality of gate lines &, X2 X2m arranged in parallel, and a plurality of data lines Y丨, Y2, ..., Yh which are vertically insulated from the gate lines X, X2, ..., X2m, and a plurality of gates Polar line &, &, ... each 乂 2: and 5 单 料 料 γ γ γ γ γ γ γ γ γ γ γ γ γ γ γ 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 And a positive connection to the gate driver 12G for receiving the scan signal from the gate driver 12G. The data line γ], γ2 ' . . . Υ 2η is connected to the source driver m for receiving the data signal outputted by the source driver 丨3 。. The pixel unit 17 includes a thin film transistor 17 and a common electrode 173. The gate, source and drain of the thin film transistor m 1380268 a 6, 1 9 101 6 · < ._ year and month correction replacement page and the gate line X/KiUm respectively, the data line is called Lang The pixel electrodes 172 are connected to each other. The pixel electrode 172, the common electrode m and the liquid crystal layer (not shown) between them form a liquid crystal capacitor 74. The timing controller W includes an H sequence (four) output 155 and a second timing signal output 156. The 'the timing signal output terminal 155 is connected to the source driver H 130 ' for outputting the poor timing control signal generated internally by the timing device 14 . The second timing signal output 156 is coupled to the delta gate driver 120 for outputting a timing control signal internally generated by the timing controller 15 . Moreover, the timing controller 15 is connected to the source driver 丨3〇 via a data bus 180 for transmitting the video signal output by the timing controller 150. When the liquid crystal display device 100 is in operation, the timing controller i5 receives a video signal from a host computer through an interface circuit (not shown), and generates a scan timing control signal and a data timing control according to the video signal. And outputting the scan timing control signal and the data timing control signal to the gate driver by the second timing signal output terminal 15.6 and the first timing signal output terminal 155 respectively! 2 该 and the source driver 130. At the same time, the timing controller 15 converts the video signal into a Reduced Swing Differential Signal (RSDS), and outputs the low amplitude differential signal to the source driver 130 by the data bus 180. The gate driver 120 generates a complex pulse signal according to the scan timing control signal received by the gate driver 120, and sequentially applies the gate lines X, X2, ..., X2m. When the scan pulse signal is applied to the ί(1<Κ2πι) gate 7 (: 1380268 101 6. 12__ L year and month to correct the replacement page polar line brother, the i-th connected to the gate line Xi ( The ^k2m) column thin film transistor 17! is turned on. The source driver 130 converts the received low amplitude differential = sign into a corresponding data voltage, and outputs the data voltage to the data voltage control signal. The pixel electrode 172 of the i-th column pixel unit 17 is at the same time. The common electrode 173 receives a common voltage from a common voltage circuit (not shown). Thus, in the pixel unit 17〇, the pixel A gray-scale voltage is formed between the electrode 172 and the common electrode 173, and the liquid crystal molecules sandwiched between the pixel electrode 172 and the common electrode 发生 rotate under the electric field generated by the gray-scale voltage to control the light throughput. The liquid crystal display 100 can only accept a single computer mainframe output, and the video signal 'processes the video signal to display the corresponding picture of the video f. However, in the abnormal work, some For specific occasions, such as production °〇Display or conference control, it is necessary to display the $frequency signal output by the plurality of computer mainframes at the same time. Since the liquid crystal display does not have the function of splitting the screen and simultaneously displaying the video signal output by the 5 computer mainframe, in this case, The messenger has to be equipped with a plurality of liquid crystal displays} to correspond to the plurality of computer mains' to meet the screen display needs, the liquid crystal display 1 can not meet the display requirements of the multi-age function, causing a lot of inconvenience to the user. It is necessary to provide a liquid crystal display that can display the video signal of a plurality of computer mainframes to meet the requirements of multi-functional display. · It is also necessary to provide a computer system using the liquid crystal display, and a liquid crystal display, which includes A liquid crystal panel, a timing controller does not select a circuit 'The timing controller receives a plurality of video signals, the JOUZD6 JOUZD6 〇. Year, month, and day are replacing the page::: Selecting a power? Turning a display mode to the timing controller Control signal two J control!] According to the 11 * mode control secret number, control the LCD panel knife '·' page does not. The picture corresponding to the plurality of video signals or the full screen displays the corresponding side of the video signal. - A liquid crystal display comprising a liquid crystal panel, a timing controller: a display circuit is selected, and the timing controller receives the plurality of video signals. The 兮^ select, the way to the 5H timing controller output-display mode control signal, the '4' _ control signal is the - signal, the timing controller controls the liquid crystal panel to display the complex video signal correspondingly Thereafter, when the control signal is switched to a second signal, the timing controller f causes the liquid crystal panel to display a full screen of the video signal corresponding to the video signal, and the display mode control signal is switched to the third device. Controlling the LCD panel to display another video signal corresponding to another video signal, comprising a first computer host, a second computer=and a liquid crystal display, the liquid crystal display comprising a liquid crystal panel, a second 'display selection circuit, the timing controller respectively receives the video signal of the selection == second computer host output, the display = select circuit to 2 timing controller A - a display mode control signal, electrical == ^: and the corresponding wheel of the view of the "host the second host computer video output signal day surface. Or the second computer, compared with the prior art, the liquid crystal display of the present invention adds a circuit, and controls the display mode according to the display selection circuit: l〇L 6. 12 !380268 ---~~1 day hair removal Replacing the page number, controlling the LCD panel to display the picture corresponding to one of the video signals corresponding to the corresponding video signal or the full screen. Therefore, the liquid crystal display can realize the simultaneous display of the video signal output by the plurality of frequency signal sources by using only one display, and overcomes the need for multiple liquid crystal displays when the video signal output by the plurality of video signal sources is simultaneously displayed in the prior art. Inconvenience, the liquid crystal display thus satisfies the multi-function display requirement, making the user simple and convenient to use. Compared with the prior art, the computer system of the present invention adopts a liquid crystal display having a display selection circuit, and the liquid crystal display can control the signal according to the display mode outputted by the display selection circuit, and the split screen simultaneously displays the video signals output by the two computer mainframes. The screen corresponds to the screen corresponding to the video signal output by any host computer. Therefore, the computer system of the present invention can simultaneously display the video signals output by the two computer mainframes by using only one display, and overcomes the prior art, and needs to be equipped with two liquid crystal displays when simultaneously displaying the video signals output by the two computer mainframes. The inconvenience is that the liquid crystal display thus satisfies the display requirements of the multi-function, making the user simple and convenient to use. [Embodiment] Please refer to Fig. 2, which is a schematic view showing the structure of a first embodiment of a liquid crystal display of the present invention. The liquid crystal display 2 includes a liquid crystal panel 21A, a gate driver 220, a first source driver 23A, a second source driver 24A, a timing controller 250, a display selection circuit 260, and a The first interface circuit 280 and a second interface circuit 29 are. The liquid crystal panel 210 includes a plurality of parallel spaced gate lines & 丄柳咖lot 6. 12 月 绦 替换 replacement page X, ... 'plural and the gate line Χι, X2, ." Xh insulated vertical The set data lines Y1, Y2, ..., Y2n, and the plural number of the pixel lines of the gate line X, χ 2, ... X2f, the dividing shirt and the matrix distribution are 270, wherein the gate The pole lines X1, X2, ... X2m are connected to the gate driver, and the device 220' is for receiving the scan signal output by the gate driver 22. The data line Y! Y2, ... γη is connected to the first source driver for receiving the data signal output from the 4th-source driver 23G. The data lines Yn+1, Yn+2, ..., Yh are connected to the second source driver 24A for receiving the data signals output by the second source driver 240. The pixel unit 2γ in the jth row of the i-th column is denoted as p((3)(1<K2m, lSjS2n), and all the pixel units i-jSn in the first to eleventh rows) constitute a first display area 211, The pixel unit Ρ (α(1^<2ηι, n+KjUn) located in the n+1th to 2nth row constitutes a second display area 212. The pixel unit Ρ (α includes a thin film transistor 271, a a halogen electrode 272 and a common electrode 273. The gate, the source and the drain of the thin film transistor 271 are respectively connected to the gate line Xi (1, the data line Yj (1 g < 2η) and the halogen electrode The liquid crystal layer 272, the common electrode 273 and the liquid crystal layer (not shown) sandwiched therebetween form a liquid crystal capacitor 274. The first interface circuit 280 and the second interface circuit 29 can be The video graphics array interface circuit or the digital video interface circuit is respectively connected to a first video signal source (not shown) and a second video signal source (not shown), and receives the first video signal source and the first a video signal output by the second video signal source, and 'the first interface circuit 280 and the second interface circuit 290 have a zoom function' The received video signal of any resolution can be scaled to 10L. The frequency of the video signal that satisfies the required resolution of the liquid crystal panel 210. In the present embodiment, the video signal obtained after zooming The resolution is 2mxn, and the first interface circuit 280 and the second interface circuit 29 can convert the video signal obtained after the scaling _ into a low-voltage differential signal (L〇wv〇hage,
DifferentialSign^LVDS)。其中，該第一視頻訊號源及第 · 二視頻訊號源分別為一電腦主機。 ^該時序控制器25〇包括一第一時序訊號輸出端255、一 第一時序號輸出端256及一顯示控制輸入端257。其中， 該第一時序訊號輸出端255連接至該第一源極驅動器23〇及參 該第二源極驅動器240，用於輸出該時序控制器25〇内部產 生之資料時序控制訊號。該第二時序訊號輸出端256連接至 該閘極驅動器220，用於輸出該時序控制器25〇内部產生之 掃描時序控制訊號。該顯示控制輸入端257連接至該顯示選 擇電路260,用於接收該顯示選擇電路26〇輸出之顯示模式 控制訊號。且’該時序控制器25〇分別藉由一第一低壓差分 訊號總線206及一第二低壓差分訊號總線2〇7連接至該第一 介面電路280及該第二介面電路290,該第一低壓差分訊號儀齡 總線206及一第二低壓差分訊號總線2〇7分別用於傳送該第 一介面電路280及第二介面電路29〇所輸出之低壓差分訊 號。該時序控制器250還分別進一步藉由一第一資料總線 208及一第二資料總線209連接至該第一源極驅動器23〇及 該第二源極驅動器240，該第一資料總線2〇8及該第二資料 總線209用於傳送該時序控制器25〇所輸出之視頻訊號。 請一併參閱圖3，係圊2所示液晶顯示器200之時序控制 § 12 耻 6· 12 1380268 年月日修正替換頁 器250之内部結構圖。該時序控制器25〇還包括依次連接之 一接收單元25卜一資料轉換器252及一輸出單元253，以及 - 一連接至該資料轉換器252之計數器254。該接收單元251 分別連接至該第一低壓差分訊號總線206及該第二低壓差 • 分訊號總線207，用於接收該第一低壓差分訊號總線206及 該第二低壓差分訊號總線207所傳送之低壓差分訊號。該資 料轉換器252連接至該顯示控制輸入端257，用於對該低壓 差分訊號進行解析操作，從而分解出同步訊號及資料訊 •號。且，該資料轉換器252為一可變位轉換器，其可根據由 "亥顯示控制輸入端2 5 7接收到之顯示模式控制訊號，將一路 k位之低壓差分訊號直接解析成為一路k位的資料訊號，或 將一路k位之低壓差分訊號解析成為兩路的資料訊號。 其中該資料轉換器252所進行之訊號解析可採用軟體控制 ，現。該輸出單元253分別連接至該第一資料總線2〇8及該 第一貧料總線209，其接收該資料轉換器252輸出之資料訊 0唬，並將該資料訊號轉換成低振幅差分訊號，並進一步分 別藉由該第一資料總線208及第二資料總線2〇9輸出。該計 數β 254分別連接至該第一時序訊號輸出端乃5及該第二時 序汛號輸出端256’其接收該同步訊號，並於其内部對該同 -步訊號進行計數從而分別得到一資料時序控制訊號及一掃 描時序控制訊號，進而將該資料時序控制訊號輸出至該第 :時序減輸ίϋ端255,將該掃描時序控制訊號輸出至該第 一時序訊號輸出端256。 請參閱圖4,係圖2所示液晶顯示器細之顯示選擇電路 13 10L 6 . 12 1380268 年月 日傣正替換頁 260之電路圖。該顯示選擇電路260包括一直流電源％卜一 上拉電阻262、一下拉電阻263、一模式選擇開關及一連 接器265。其中該模式轉換開關264包括一第一端子266、一 第二端子267及一第三端子268。該第一端子266藉由該上拉 電阻262連接至該直流電源26卜該第三端子268藉由該下拉 電阻263接地，該第二端子267懸空。該連接器265包括一輸 入端2651及一輸出端2652，其中該輸出端2652連接至該顯 示控制輸入端257’該輸入端2651可根據用戶選擇連接至該 模式轉換開關264之任一端子。在該顯示選擇電路26〇中，着 當該輸入端2651連接至該模式轉換開關264之其中一端子 時，該輸出端2652便輸出一對應之顯示模式控制訊號，即 當该輸入端2651連接至該第一端子266，該輸出端2652輸出 一高電平；當該輸入端2651連接至該第三端子268，該輸出 端2652輸出一低電平；當該輸入端2651連接至該第二端子 267，s亥輸出端2652處於高阻態，輸出一高阻態訊號。 該液晶顯示器200之工作原理如下所述： 當该液晶顯不器200工作時，首先，該液晶顯示器2〇〇 瞻 刀別藉由忒第一介面電路28〇接收該第一視頻訊號源所輸 出之第路視頻讯唬，同時藉由該第二介面電路290接收該 -第二視頻訊號源所輸出之第二路視頻訊號。接著，該第一 ，面電路280及第二介面電路29〇對其接收之第一路視頻訊 號及第二路視頻訊號進行縮放處理，使該第一路視頻訊號 及該第二路視頻訊號分別轉換成一解析率為2mxn之視頻 訊號。再接著，該第-介面電路28〇及第二介面電路29〇分 1380268 ·* ιοί 6.12 年月日條正替換頁 別將該視頻訊號轉換成為一第一路低壓差分訊號及一第二 路低壓差分訊號，並輸出至該時序控制器250。且，該第一 ' 路低壓差分訊號及該第二路差分低壓訊號均為k位訊號。 • 該時序控制器250藉由該接收單元251分別接收該第一 * 路低壓差分訊號及第二路低壓差分訊號’並進一步將該第 一路及第二路低壓差分訊號送入該資料轉換器252。該資料 轉換器252同時藉由該顯示控制輸入端257從該顯示選擇電 路260接收一顯示模式控制訊號，並根據該顯示模式控制訊 鲁號對該第一路低壓差分訊號及該第二路低壓差分訊號進行 解析轉換。 具體而言，當該顯示模式控制訊號為一高電平，即該 顯示選擇電路260中，該連接器265之輸入端2651連接至該 模式選擇開關264之第一端子266時，該高電平控制該資料 轉換器252便將該k位之第一路低壓差分訊號解析轉換為一 Π步Λ 5虎及一路k位之資料訊號，該二路k位之資料訊號即 •為一 k位之第一路資料訊號及一 k位之第二路資料訊號。該 資料轉換器252接著進一步將該同步訊號送至該計數器 254’同時將該第一路資料訊號及該第二路資料訊號分別送 ， 至該輸出單元253。 . 當該顯示模式控制訊號為一低電平，即該顯示選擇電 • 路260中’該連接器265之輸入端2651連接至該模式選擇開 關264之第三端子268時，該低電平控制該資料轉換器 便將該k位之第二路低壓差分訊號解析轉換為—同步訊號 及二路k位之資料訊號，該二路k位之資料訊號即為一 k位之 15 10L 6. 12 1380268 -月日條正替換百 第一路資料訊號及一 k位之第二路資料訊號。該資料轉換哭 252接著進一步將該同步訊號送至該計數器254，同時將該 第一路資料訊號及該第二路資料訊號分別送至該輸出單元 253。 當該顯示模式控制訊號為一高阻態訊號，即該顯示選 擇電路260中’該連接器265之輸入端2651連接至該模式選 擇開關264之第二端子267時，該高阻態訊號控制該資料轉 換器252工作於缺省狀態’即便將該k位之第一路低壓差分 訊號分解成一第一同步訊號及一 k位之第一路資料訊號，同籲 時將該k位之第二路低壓差分訊號分解成一第二同步訊號 及一 k位之第二路資料訊號。該資料轉換器252接著進一步 將該第一同步訊號及該第二同步訊號進行同步處理，得^ 一綜合同步訊號並送至該計數器254,同時將該第一路資料 訊號及該第二路資料訊號輸出至該輸出單元253。 接著，該計數器254對其接收之同步訊號進行計數，從 而^別=到一掃描時序控制訊號及資料時序控制訊號，並 進一步藉由該第一時序訊號輸出端2 5 5將該資料時序控制· 訊號輸出至該第一源極驅動器2 3 〇及該第二源極驅‘器 24〇 ’同時藉由該第二時序訊號輸出端256將該掃描時序控， 制訊號輸出至該閘極驅動器22()。另—方面，該輸出單元加 將該第一路資料訊號轉換成一第一路低振幅 . 藉由該第-資料總線期輸出至該第—源極驅^ 路資料訊號轉換成一第二路低振幅差分訊號， 並措由5亥第二資料總線209輸出至該第二源極驅動器24〇。 助· 6. I3S0268 年月 日條正替換頁 該閘極驅動器220根據其所接收之掃描時序控制訊號， 產生複數掃描脈衝訊號，並依序施加至該閘極線Xl、χ2、… X2m。當該掃描脈衝訊號施加至該第i( 1幺丨<2m)條閘極線Xi 時’與5玄閘極線Xj相連接之第列薄模電晶體271 導通。 該第一源極驅動器230將該第一路低振幅差分訊號轉 換成對應之資料電壓，並在該資料時序控制訊號作用下， 將5玄資料電壓輸出至該第一顯示區2丨1内部之畫素單元 iq<n)之晝素電極272。該第二源極驅動器 240將该第二路低振幅差分訊號轉換成對應之資料電壓，並 在該資料時序控制訊號作用下，將該資料電壓輸出至該第 二顯示區212内部之畫素單元P(ij)(1sk2m，n+kg2n)之 晝素電極272。 同4，δ亥公共電極273接收一公共電壓電路（圖未示） 發出之公共電壓。由此，於該晝素單元ρ(Μ)(^Κ2ιη， jS2n)中，该晝素電極272與該公共電極之間形成一灰階 電壓。在該灰階電壓產生之電場作用T，夾於該晝辛電極 =與該公共電極273間之液晶分子發生旋轉，控制光線通 過罝以顯示晝面。 由此’於該液晶顯示器2⑼中，當該資料轉換器加工 時於由m態’ μ該顯示模式控制訊號為一高阻態訊號 由於该第-顯示區211所顯示之晝面對應 =所輸出之視頻訊號，而該第二顯示區212所顯示：書員 、、於及第—視頻訊號源所輸出之視頻訊號，此時該液 101 6. 1 1380268 I__年月日條正替換頁DifferentialSign^LVDS). The first video signal source and the second video signal source are respectively a computer host. The timing controller 25 includes a first timing signal output 255, a first time sequence output 256, and a display control input 257. The first timing signal output terminal 255 is connected to the first source driver 23 参 and the second source driver 240 for outputting a data timing control signal generated by the timing controller 25 . The second timing signal output terminal 256 is coupled to the gate driver 220 for outputting a scan timing control signal internally generated by the timing controller 25A. The display control input 257 is coupled to the display selection circuit 260 for receiving a display mode control signal output by the display selection circuit 26A. The first low voltage is connected to the first interface circuit 280 and the second interface circuit 290 by a first low voltage differential signal bus 206 and a second low voltage differential signal bus 2〇7, respectively. The differential signal aging bus 206 and a second low voltage differential signal bus 〇7 are respectively used to transmit the low voltage differential signals output by the first interface circuit 280 and the second interface circuit 29 。. The timing controller 250 is further connected to the first source driver 23 and the second source driver 240 by a first data bus 208 and a second data bus 209, respectively. The first data bus 2〇8 And the second data bus 209 is configured to transmit the video signal output by the timing controller 25A. Please refer to FIG. 3 together with the timing control of the liquid crystal display 200 shown in FIG. 2 § 12 Shame 6·12 1380268 The internal structure of the replacement page 250 is corrected. The timing controller 25A further includes a receiving unit 25, a data converter 252 and an output unit 253, and a counter 254 connected to the data converter 252. The receiving unit 251 is connected to the first low-voltage differential signal bus 206 and the second low-drop differential signal bus 207 for receiving the first low-voltage differential signal bus 206 and the second low-voltage differential signal bus 207. Low voltage differential signal. The data converter 252 is coupled to the display control input 257 for parsing the low voltage differential signal to resolve the synchronization signal and the data signal. Moreover, the data converter 252 is a variable bit converter that can directly parse a k-bit low-voltage differential signal into a k-channel according to a display mode control signal received by the "Hai display control input terminal 257. The data signal of the bit, or the k-bit low-voltage differential signal is parsed into two data signals. The signal analysis performed by the data converter 252 can be controlled by software. The output unit 253 is connected to the first data bus 2〇8 and the first poor bus 209, and receives the data signal outputted by the data converter 252, and converts the data signal into a low-amplitude differential signal. And further outputted by the first data bus 208 and the second data bus 2〇9, respectively. The counting β 254 is respectively connected to the first timing signal output terminal 5 and the second timing signal output terminal 256 ′, which receives the synchronization signal, and internally counts the same-step signal to obtain one respectively. The data timing control signal and a scan timing control signal are further outputted to the first: timing subtraction terminal 255, and the scan timing control signal is output to the first timing signal output terminal 256. Please refer to FIG. 4, which is a circuit diagram of the liquid crystal display shown in FIG. 2, which is a fine display selection circuit 13 10L 6 . 12 1380268. The display selection circuit 260 includes a DC power supply pull-up resistor 262, a pull-up resistor 263, a mode selection switch, and a connector 265. The mode changeover switch 264 includes a first terminal 266, a second terminal 267, and a third terminal 268. The first terminal 266 is connected to the DC power source 26 by the pull-up resistor 262. The third terminal 268 is grounded by the pull-down resistor 263, and the second terminal 267 is suspended. The connector 265 includes an input terminal 2651 and an output terminal 2652. The output terminal 2652 is coupled to the display control input terminal 257'. The input terminal 2651 can be connected to any one of the terminals of the mode changeover switch 264 according to a user selection. In the display selection circuit 26, when the input terminal 2651 is connected to one of the terminals of the mode switch 264, the output terminal 2652 outputs a corresponding display mode control signal, that is, when the input terminal 2651 is connected to The first terminal 266, the output terminal 2652 outputs a high level; when the input terminal 2651 is connected to the third terminal 268, the output terminal 2652 outputs a low level; when the input terminal 2651 is connected to the second terminal 267, shai output 2652 is in a high impedance state, outputting a high impedance signal. The working principle of the liquid crystal display 200 is as follows: When the liquid crystal display device 200 is operated, firstly, the liquid crystal display device 2 receives the output of the first video signal source by the first interface circuit 28? The second video signal is received by the second interface circuit 290, and the second video signal output by the second video signal source is received. Then, the first circuit 280 and the second interface circuit 29 scale the received first video signal and the second video signal to make the first video signal and the second video signal respectively Converted into a video signal with a resolution of 2mxn. Then, the first interface circuit 28 and the second interface circuit 29 are divided into 1380268 · * ιοί 6.12 year and day is replacing the page to convert the video signal into a first low voltage differential signal and a second low voltage The differential signal is output to the timing controller 250. Moreover, the first 'channel low voltage differential signal and the second differential low voltage signal are k-bit signals. The timing controller 250 receives the first *channel low-voltage differential signal and the second low-voltage differential signal respectively by the receiving unit 251 and further sends the first and second low-voltage differential signals to the data converter. 252. The data converter 252 receives a display mode control signal from the display selection circuit 260 through the display control input 257, and controls the first low voltage differential signal and the second low voltage according to the display mode. The differential signal is parsed and converted. Specifically, when the display mode control signal is a high level, that is, the display selection circuit 260, the input terminal 2651 of the connector 265 is connected to the first terminal 266 of the mode selection switch 264, the high level The data converter 252 controls the k-channel first low-voltage differential signal to be converted into a data signal of a step 5 and a k-bit, and the data signal of the two k-bits is a k-bit The first road information signal and the second road information signal of one k. The data converter 252 then further sends the synchronization signal to the counter 254' to simultaneously send the first path data signal and the second path data signal to the output unit 253. When the display mode control signal is a low level, that is, the input terminal 2651 of the connector 265 is connected to the third terminal 268 of the mode selection switch 264 in the display selection circuit 260, the low level control The data converter converts the k-channel low-voltage differential signal into a synchronous signal and two k-bit data signals, and the data signals of the two k-bits are 15 kL of a k-bit. 1380268 - The month of the month is replacing the information signal of the first road and the second road of the k. The data is switched to cry 252 and then the synchronization signal is further sent to the counter 254, and the first data signal and the second data signal are sent to the output unit 253, respectively. When the display mode control signal is a high impedance signal, that is, the input terminal 2651 of the connector 265 is connected to the second terminal 267 of the mode selection switch 264 in the display selection circuit 260, the high resistance signal controls the The data converter 252 operates in a default state 'even if the k-bit first low-voltage differential signal is decomposed into a first synchronization signal and a k-bit first data signal, and the k-bit second path is simultaneously invoked The low voltage differential signal is decomposed into a second synchronization signal and a k-th second data signal. The data converter 252 then further synchronizes the first synchronization signal and the second synchronization signal to obtain a comprehensive synchronization signal and sends the integrated synchronization signal to the counter 254, and simultaneously the first data signal and the second data. The signal is output to the output unit 253. Then, the counter 254 counts the synchronous signal received by the counter 254, so as to control the signal and the data timing control signal, and further controls the data timing by the first timing signal output terminal 255. The signal is output to the first source driver 2 3 〇 and the second source driver 24 〇 ' while the scan timing is controlled by the second timing signal output 256, and the signal is output to the gate driver twenty two(). In another aspect, the output unit converts the first path data signal into a first path low amplitude. The first data path is outputted to the first source drive data signal to be converted into a second low amplitude. The differential signal is outputted to the second source driver 24 by the second data bus 209. Assist 6. 6. I3S0268 Year and Day Positive Replacement Page The gate driver 220 generates a plurality of scan pulse signals according to the scan timing control signals it receives, and sequentially applies the gate lines X1, χ2, ... X2m. When the scan pulse signal is applied to the ith (1 幺丨 < 2m) gate line Xi, the column thin mode transistor 271 connected to the 5th gate line Xj is turned on. The first source driver 230 converts the first low-amplitude differential signal into a corresponding data voltage, and outputs a 5-thin data voltage to the first display area 2丨1 under the action of the data timing control signal. The pixel electrode 272 of the pixel unit iq<n). The second source driver 240 converts the second low-amplitude differential signal into a corresponding data voltage, and outputs the data voltage to the pixel unit in the second display area 212 under the action of the data timing control signal. A halogen electrode 272 of P(ij) (1sk2m, n+kg2n). Similarly, the δ hai common electrode 273 receives a common voltage from a common voltage circuit (not shown). Thus, in the halogen element ρ(Μ) (^Κ2ιη, jS2n), a gray scale voltage is formed between the halogen electrode 272 and the common electrode. The electric field generated by the gray-scale voltage acts as T, and the liquid crystal molecules sandwiched between the symplectic electrode and the common electrode 273 rotate, and the light is controlled to pass through the 罝 to display the surface. Therefore, in the liquid crystal display 2 (9), when the data converter is processed, the display mode control signal is a high-resistance signal by the m state 'μ, and the corresponding display is displayed by the first display area 211. The video signal, and the second display area 212 displays: the video signal output by the booklet, the source, and the first video signal source. At this time, the liquid 101 6. 1 1380268 I__ year, month, and day are replacing the page.
晶顯>示器200便實現左右分屏分別顯示該第一視㈣H 及該第二視頻訊號源之視頻訊號。而當該顯示模式控制訊 號為-高電平時，該液晶顯示器鳩全屏顯示該第一視頻訊 號源之視頻訊號’·當該顯示模式控制訊號為一低電平時， 該液晶顯示器200全屏顯示該第二視頻訊號源之視頻訊 號:而且由於該顯示模式控制訊號所輸出之訊號可由使用 者藉由該模式選擇開關264手動控制選擇，因此該液晶顯示 器200可簡單方便地實現分屏顯示模式與全屏顯示模式之 轉換，以及在全屏模式下對不同視頻訊號源所輸出之視頻 訊號進行切換顯示。 相較於先前技術，本發明之液晶顯示器2〇〇增加一顯示 選擇電路260，並於該時序控制器25〇内部使用一可變位之 貝料轉換252，由此通過使用者手動控制該顯示選擇電路 260以選擇不同之顯示模式，進一步控制該資料轉換器μ] 在不同顯示模式下進行資料解析轉換，一方面實現對°不同 視頻訊號源所輸出之視頻訊號進行全屏顯示切換，另一方 面實現分屏同時顯示複數視頻訊號源所輸出之視頻訊號。 因此本發明之液晶顯示器有效克服先前技術在同時顯 不複數電腦主機所輸出之視頻訊號時需要配備複數液晶顯 不器100而帶來之諸多不便，由此滿足日常工作中多功能之 顯不要求，並可有效節省使用空間，降低使用成本。且， 该液晶顯示器200使得使用者進行顯示操作及觀看顯示畫 面時眼睛僅需注視單獨顯示器，避免由於經常性轉換至不 同顯不器而容易帶來之疲勞，提高使用者之工作效率。 I3.80268 101 6. 12_ 年月日修正替換頁 4參閱圖5 ’係本發明液晶顯示器第二實施方式之結構 不意圖。該液晶顯示器300與該液晶顯示器200之區別在 於.該液晶顯示器300包括一第一閘極驅動器321及一第二 閘極驅動器322。該液晶面板3 1〇中，該閘極線Χι、χ2、…The crystal display unit 200 displays the video signals of the first view (four) H and the second video signal source respectively. When the display mode control signal is -high level, the liquid crystal display 鸠 displays the video signal of the first video signal source in full screen. · When the display mode control signal is a low level, the liquid crystal display 200 displays the full screen. The video signal of the second video signal source: and since the signal output by the display mode control signal can be manually controlled by the user through the mode selection switch 264, the liquid crystal display 200 can realize the split screen display mode and the full screen display simply and conveniently. The mode is switched, and the video signals output by different video signal sources are switched and displayed in the full screen mode. Compared with the prior art, the liquid crystal display 2 of the present invention adds a display selection circuit 260, and uses a variable bit beet conversion 252 inside the timing controller 25A, thereby manually controlling the display by the user. The selection circuit 260 selects different display modes, further controls the data converter μ] to perform data analysis and conversion in different display modes, and realizes full-screen display switching of video signals output by different video signal sources on the other hand. The split screen simultaneously displays the video signals output by the plurality of video signal sources. Therefore, the liquid crystal display of the present invention effectively overcomes the inconvenience caused by the need to equip the plurality of liquid crystal display devices 100 when the video signals output by the computer mainframe are displayed at the same time in the prior art, thereby satisfying the requirements of the multi-function in daily work. And can effectively save space and reduce the cost of use. Moreover, the liquid crystal display 200 allows the user to only look at the individual display when performing the display operation and viewing the display screen, thereby avoiding the fatigue easily caused by frequent switching to different display devices, and improving the working efficiency of the user. I3.80268 101 6. 12_ Year Month Day Correction Replacement Page 4 Referring to Figure 5, the structure of the second embodiment of the liquid crystal display of the present invention is not intended. The difference between the liquid crystal display 300 and the liquid crystal display 200 is that the liquid crystal display 300 includes a first gate driver 321 and a second gate driver 322. In the liquid crystal panel 3 1 , the gate lines Χι, χ 2, ...
Xm連接至該第一閘極驅動器321，該閘極線Xm+i、Xm+2、… Χπ連接至該第二閘極驅動器322。該第一閘極驅動器321 及邊第二閘極驅動器322分別接收該時序控制器35〇輸出之 掃榣時序控制訊號。且，位於第1至m列之畫素單元p(i j)( j —i幺m，1 22η)構成一第一顯示區311，而位於第至 2爪列之晝素單元P(ij)(m+1^2m，！叫2n)構成一第二顯 ，區312。該資料線Yl、a、…丫〜於該第一顯示區311與該 第二顯示區312交界處斷開，且該資料線Υι、γ2、…γ2η位 於該第一顯示區311之部份連接至該第一源極驅動器33〇， 其位於5亥第二顯示區3丨2之部份連接至該第二源極驅動器 340 = ° 該液晶顯示器300與該液晶顯示器2〇〇之工作原理基本 相同，5亥液晶顯不器300分別接收二視頻訊號源（圖未示） 所輸出之視頻訊號後，根據使用者手動控制該顯示選擇電 路360輸出之顯示模式控制訊號，實現對不同視頻訊號源所 輸出之視頻訊號進行全屏切換顯示，或上下分屏同時顯示 該二視頻訊號源所輸出之視頻訊號。 惟，本發明之液晶顯示器200及3〇〇並不侷限於以上實 施方式所描述。如，該液晶顯示器200及300可僅藉由一介 面電路連接至一視頻訊號源，並顯示該視頻訊號源所輸出 19 10L 6. 12 1380268 __日佟正替換頁 之視頻訊號。該液晶顯示器2〇〇還可進行擴展，即採用複數 介面電路連接至多個視頻訊號源，並全屏切換或同時分屏 顯示該複數視頻訊號源所輸出之視頻訊號。該顯示選擇電 路260及360輸出之顯示模式控制訊號還可藉由軟體控制自 動輸出等。 請參閱圖6 ’係本發明電腦系統之結構示意圖。該電腦 系統600包括一液晶顯示器61〇、一第一電腦主機62〇及一第 了電腦主機630。其中，該液晶顯示器61〇可採用該液晶顯 不器200及300，該第-電腦主機62〇及該第二電腦主機⑽ /刀別連接至該液晶顯示H61()，作為其視頻訊號源^該液晶 顯示器610藉由-第—介面電路（圖未示）從該第—電腦主 機620接收第一路視頻訊號’同時藉由一第二介面電路（圖 未不)由該第二電腦主機62〇接收第二路視頻訊號，並通過 使用者選擇其顯示模式，全屏顯示該第一電腦主機62〇或該 第二電腦主機630所輸出之視頻訊號，或分屏同時顯示該第 一電腦主機620及該第二電腦主機伽所輸出之視頻訊號。 綜上料，本發縣合發料财件，1依法提出專 利申請。m所述㈣為本發明之較佳實施方式 發明之範圍並不以上述實施方式為限，舉凡熟悉本案技敲 之人士，在援依本案發㈣神所作之等效修#或變化 應包含於以下申請專利範圍内。 【圖式簡單說明】 圖1係先前技術-種液晶顯示器之結構示意圖Xm is connected to the first gate driver 321, and the gate lines Xm+i, Xm+2, ... Χπ are connected to the second gate driver 322. The first gate driver 321 and the second gate driver 322 respectively receive the broom timing control signal output by the timing controller 35. Moreover, the pixel units p(ij)( j —i幺m, 1 22η) located in the first to the mth columns constitute a first display area 311, and the pixel units P(ij) located in the second to the second claw row ( m+1^2m, !2n) constitutes a second display, zone 312. The data line Y1, a, ..., 丫 is disconnected from the boundary between the first display area 311 and the second display area 312, and the data lines Υι, γ2, ... γ2η are located in the first display area 311. To the first source driver 33A, the portion of the second display area 3丨2 located at 5 hai is connected to the second source driver 340=°. The working principle of the liquid crystal display 300 and the liquid crystal display 2 is basically Similarly, the 5H liquid crystal display device 300 receives the video signal output by the second video signal source (not shown), and then manually controls the display mode control signal output by the display selection circuit 360 to realize different video signal sources. The output video signal is displayed in full screen switching, or the video signals output by the two video signal sources are simultaneously displayed on the upper and lower divided screens. However, the liquid crystal displays 200 and 3 of the present invention are not limited to those described in the above embodiments. For example, the liquid crystal displays 200 and 300 can be connected to a video signal source only by a interface circuit, and display the video signal output by the video signal source. The liquid crystal display 2 can also be expanded, that is, a plurality of interface signals are connected to a plurality of video signal sources, and the video signals output by the plurality of video signal sources are displayed in full screen switching or simultaneously. The display mode control signals output by the display selection circuits 260 and 360 can also be controlled by software to control the automatic output or the like. Please refer to FIG. 6 for a schematic diagram of the structure of the computer system of the present invention. The computer system 600 includes a liquid crystal display 61, a first computer main unit 62, and a first computer main unit 630. The liquid crystal display unit 61 can adopt the liquid crystal display devices 200 and 300, and the first computer main unit 62 and the second computer main unit (10)/knife are connected to the liquid crystal display H61 () as the video signal source thereof. The liquid crystal display 610 receives the first video signal from the first computer host 620 by a first interface circuit (not shown) and is also used by the second computer host 62 by a second interface circuit (not shown). 〇 receiving the second video signal, and displaying the video signal output by the first computer host 62 or the second computer host 630 in full screen by the user, or displaying the first computer host 620 by splitting the screen. And the video signal output by the second computer host. In summary, the county issued a joint financial statement, 1 patent application. m (4) The preferred embodiment of the present invention is not limited to the above-described embodiments, and those who are familiar with the skill of the present invention should be included in the equivalent repairs or changes made by God in the case of aiding the case. It is within the scope of the following patent application. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing the structure of a prior art liquid crystal display
S 20 10L 6. 12 1380268 年月日條正替換頁 圖2係本發明液晶顯示器第一實施方式之結構示意圖。 圖3係圖2所示液晶顯示器之時序控制器之内部結構圖。 圖4係圖2所示液晶顯示器之顯示選擇電路之電路圖。 圖5係本發明液晶顯示器第二實施方式之結構示意圖。 圖6係本發明電腦系統之結構示意圖。S 20 10L 6. 12 1380268 Year, the following is a replacement page. Fig. 2 is a schematic view showing the structure of the first embodiment of the liquid crystal display of the present invention. 3 is an internal structural diagram of a timing controller of the liquid crystal display shown in FIG. 2. 4 is a circuit diagram of a display selection circuit of the liquid crystal display shown in FIG. 2. Fig. 5 is a schematic view showing the structure of a second embodiment of the liquid crystal display of the present invention. Figure 6 is a schematic view showing the structure of the computer system of the present invention.
【主要元件符號說明】 液晶顯示器 200 、 300 、 610 第一視頻訊號總線 206 第二視頻訊號總線 207 第一資料總線 208 第一資料總線 209 液晶面板 210 ' 310 第一顯示區 211 、 311 第二顯示區 212 、 312 閘極驅動器 220 ' 321 > 322 第一源極驅動器 230 、 330 第一源極驅動器 240 ' 340 時序控制器 250 ' 350 接收單元 251 資料轉換器 252 輪出單元 253 計數器 254 第一時序訊號輸出端 255 第二時序訊號輸出端 256 21 1380268 10L 6. 12 年月 日條正替換苜 顯示控制輸入端 顯示選擇電路 直流電源 上拉電阻 下拉電阻 模式選擇開關 連接器 輸入端 輸出端 第一端子 第二端子 第三端子 畫素單元 薄膜電晶體 晝素電極 公共電極 液晶電容 第一介面電路 第二介面電路 電腦糸統 第一電腦主機 第二電腦主機 257 260 ' 360 261 262 263 264 265 2651 2652 266 267 268 270 271 272 273 274 280 290 600 620 630[Main component symbol description] Liquid crystal display 200, 300, 610 First video signal bus 206 Second video signal bus 207 First data bus 208 First data bus 209 Liquid crystal panel 210' 310 First display area 211, 311 Second display Zone 212, 312 gate driver 220'321 > 322 first source driver 230, 330 first source driver 240' 340 timing controller 250' 350 receiving unit 251 data converter 252 wheeling unit 253 counter 254 first Timing signal output terminal 255 Second timing signal output terminal 256 21 1380268 10L 6. 12 year month and day strip replacement 苜 display control input display selection circuit DC power supply pull-up resistor pull-down resistor mode selection switch connector input terminal output One terminal second terminal third terminal pixel unit thin film transistor halogen electrode common electrode liquid crystal capacitor first interface circuit second interface circuit computer system first computer host second computer host 257 260 ' 360 261 262 263 264 265 2651 2652 266 267 268 270 271 272 273 274 280 290 600 620 630
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