TWI379234B - Motherboard, storage device and controller thereof and booting method - Google Patents

Abstract

A motherboard, a storage device and a controller thereof and a booting method are provided. In the present invention, when powered on, an unfetch signal is transmitted to a central processor unit (CPU) by a controller such that an operation of the CPU is suspended. Next, a system firmware in the storage device is loaded by the controller. After the system firmware is loaded, a fetch-done signal is transmitted to the CPU by the controller such that the CPU starts executing a booting procedure.

Description

1379234 PSPD-2008-0034 29393tw£doc/n VI. Description of the Invention: [Technical Field] The present invention relates to a computer system, and more particularly to a motherboard having a storage device controller, having a system Firmware storage device and boot method. [Prior Art] Generally speaking, during the startup of a personal computer (PC), the basic input/output system (BIOS) is responsible for initializing hardware, detecting hardware functions, and guiding jobs. The action of the system. BI〇s are usually stored in a memory that will not be lost after power-off, and the memory with the boot program is generally called System Firmwa; e) Read-only memory (Read 〇niy Memory) 'ROM'. When the PC system is powered down or reset, the address of the first instruction to be executed by the Central Processing Unit (CPU) will be located in the firmware of the system firmware. The program starts executing. The system's dynamic read-only memory is fixedly configured on the motherboard of the personal computer, first and through the low-digit digits (L〇w pin c〇unt) bus or serial peripheral interface (SefialPefiph(10)I-,〗 The bus bar is connected to the (4) wafer_Southbridge wafer towel. Since the read-only memory is fixedly disposed on the domain board, it is quite inconvenient in terms of maintenance. 3 1379234 PSPD-2008-0034 29393twf.doc/n SUMMARY OF THE INVENTION The present invention provides a storage device that is divided into two major and system data 'and configuration-storage device control = to read the board' through the object controller. The invention provides a booting method, which is a reading delay problem caused by a meta-reading system and a residual body. In detail, the present invention proposes a storage device for crying, and a micro-four (4) early pain to the motherboard (four) central processing single heart a to the storage device controller, micro-control single field power supply; to central processing Unit, Personnel = Fu to Micro Control Unit, Buffer = Control Early Unit is used to store the storage module (4) _^ (Sy_, load to buffer ϋ. ^ interface control · group wa ^ e device financial processing The interface control module is used when the micro control unit controls the device through the peripheral device: after the system is loaded into the buffer, the micro control unit will: = the central processing unit 'to enable the t-port to pass through the interface The system of the buffer is purchased to perform the booting process. In addition, the present invention proposes a motherboard, including a central storage device control (four) and a storage group. The f, the domain device 4 1379234 PSPD- 2008-0034 29393twf.doc/n where the storage module is coupled to the storage device controller, when the power is connected to the main 3 = profit, the storage device controller communicates with the storage module. = = ί storage device controller Will send the load is not completed. ^ yarn ί early, so that After the central processing unit suspends the execution of the boot process, after the second sub-device controller loads the system, the storage device controls, and sends the completion signal to the central processing unit, so that the two single 7L read system firmware performs the booting. Program., storage = group, including with system · health device control (four) will send unfinished irm: single storage device controller will perform opening 7 ^ ' to enable the central processing unit to read the system _ to control In the case of the rushing person, the above storage device controller includes: micro-, and the single-core is connected to the motherboard; ^ is not signaled or loaded to the central processing unit: micro at = early 70 Suspend or start the service program. The buffer n is connected to the peripheral device control unit - to the micro control unit, ίί ~, the storage module. The peripheral device control unit is the buffer system, to the buffer. The interface control module, buffer And the central processing unit. The interface control module uses::: 5 PSPD-2〇〇8-〇〇34 29393twf.d ioc/n system firmware in the punch. Stealing one of the embodiments of the present invention The micro control unit further includes - control 'Eli Use the control pin to transfer the load unfinished signal or load the input of the 'control pin and the central processing unit's reset and gate logic and gate (LogicANDGate), and the output of the logic and gate is turned Connected to the central processing unit. In the interface embodiment, the above interface control module includes a lexical = two-body interface control unit _ body address temporary storage address register is _ when the data is stored in the buffer from the café The coffee is temporarily stored according to the address stored in the above address. The above interface control module further includes a storage unit and a medium===== secret to the micro control through the storage device (four) It can be passed through, and the interface control unit can pass through the system data transmission through the system. The above-mentioned wire-body transmission interface is, for example, connected to a central processing unit Peripheral Interfaee, fat) busbar peripheral "Serial (Serial) ISA) busbar and 6 1379234 PSPD-2008*0034 29393twf.doc/n

Count, LPC) One of the bus bars. The system data transmission interface is, for example, a Peripheral Controller Interface (JPCI) bus, a PCI Express bus, and a parallel high-order attachment technology (Paralld).

Advanced Technology Attachment (PATA) bus and one of the serial Advanced Technology Attachment (SATA) bus bars. In an embodiment of the invention, the system firmware includes a boot block code and a run block code. The central processing unit reads the boot block code through the firmware interface control unit to initialize at least the storage device interface control unit, the main memory of the control chip set and the motherboard. Afterwards, the central processing unit can read the running block code through the storage device interface control unit to execute the subsequent booting process. °° From another point of view, the present invention proposes a booting method suitable for use in a computer system. The computer system has a central processing unit, a storage controller and a storage module, and the storage device controller is coupled between the central unit and the storage module. In this booting method, when the power supply to the first button is transmitted by the storage device control H, the manned unfinished signal is sent to the central processing unit, and the central processing unit is called to suspend the execution of the sequence. The middle hunting is transferred from the storage limb control system to the storage model. After the helper is loaded, the storage device controller = enters the completion of the server, and the boot program is loaded. In an embodiment of the present invention, the above-mentioned system segment (Code Segment) is in the above booting method; 7 1379234 PSPD'2008-0034 29393twf d0c/n = system firmware loaded in the storage module is loaded Step, the body is loaded into the storage device controller - the buffer: the address processing unit of the first read request is sent to the first address of the upper four program sections - the first program section is loaded to After buffering, the location of the step of transferring the completion signal to the central processing unit is stored. (4) The second reading of the receiving processing unit is the second address of the receiving processing unit. Fall in the health = ^. When the second address does not fall in the ^ program section, the second program section corresponding to the second address is loaded into the buffered by the device (4), and the booting method can be further The reset signal used to control the central processing unit is logically operated to control the operation of the central processing unit. In the real implementation, the above-mentioned transmission-completion signal is based on the above, and the present invention will be used in the system firmware and system personnel--in this group, the original space can be saved in the motherboard: i; memory space' Saves extra production system firmware only 2 . In addition, it is more practical - an interface control module that allows the lieutenant to deal with the 8 PSPD-2008-0034 29393twf.doc/n firmware that has been used to manage the model and solve the read latency. problem. The above features and advantages of the present invention will be more apparent from the following description. [Embodiment] A block diagram of a computer system shown in green form according to an embodiment of the present invention. s month to know the map! The computer system 100 includes a central processing unit (CPU) 110, and controls "group 120, financial device 13 (Uxa main memory (Main)

Memory ) (10). The central processing unit i 1 , the control chip group i2 , and the main memory 16G are disposed in the motherboard 17G. The control day and day group 12 is divided into the central processing unit 11G and the main memory _. In the present embodiment, the main memory ϋ 160 is, for example, a dynamic random access memory (DRAM). The central processing unit 110 is operative to execute instructions on the computer system 1 to control the operation of the computer system 100. The control chip set 120 is used to electrically connect the central processing unit 11 to other components on the electrical system 1', for example, the storage device 13 is a virtual main δ memory 160. In this embodiment, the control chip set 120 is an integrated North Bridge Chip and a South Bridge chip (s〇uth Bridge).

The single chip of the function of Chip) is implemented. In other embodiments, the control chip set 120 can also include two independent wafers, a north bridge wafer and a south bridge wafer. The storage device 130 includes a storage module 140 and a storage device controller 150. In this embodiment, the 'storage module H〇 is implemented by using non-volatile memory 1379234 PSPD-2008-0034 29393twf.doc/n (Non-Volatile Memory 'NVM) to simultaneously store system firmware and system data. . The storage module 14A will be described below by way of an example. 2 is a block diagram of a memory module in accordance with an embodiment of the invention. Referring to FIG. 2, the storage module 140 includes a firmware region 141 and a data region 143. The firmware region 141 is used to store a system firmware 145. Here, the system firmware 145 is, for example, a basic input/output system (Basic Input/〇utput System ’ BIOS), or a unified extendable firmware interface (Unified).

Extensible Firmware Interface ’ UEFI). The data area 143 is used to store system data, such as operating systems, drivers, and broadcast systems. The above system firmware 145 can be further divided into a Boot Block Code 147 and a running block code (Runtime B1〇ck).

Code) 149 two major blocks. The boot block code 147 is responsible for setting the initial value of the booting of the computer system 100 and the initial setting of the hardware. The running block code 149 is used by the computer system to control the performance and other functions of the hardware device. In general, the boot block code 丨47 can be directly ordered without decompression. The running block code 149 needs to be decompressed before it can be executed. Therefore, at least the booting chip group 120 and the main memory 16 are initialized in the boot block code 147 to transfer the running block code 149 to the main after the boot block code 147 is directly executed. The memory 160 is decompressed to speed up the execution of the system firmware 145. The memory device controller 150 is coupled between the control chip set 120 1379234 PSPD-2008-0034 29393 twf.doc/n and the storage module, such that the central processing unit u = the device 15. To read the system in the storage module just _ Μ: Let's take another example to illustrate the internal components of the storage device controller 15〇. Figure 3A is a block diagram of a device in accordance with an embodiment of the present invention. Referring to FIG. 3 and FIG. 3A simultaneously, the storage device=150 includes an interface control module 3〇〇, a micro control unit 2: and a peripheral device control unit 33〇β 320 unit fit unit 31G secret to the central processing of the motherboard 17G.兀110' its negative shell; the kneading control module 3〇〇, ί control single U. And through the internal data sink "38 ϊϊΐ exchange action. F δ υ贞 babe ship 320 is coupled to the micro control unit 310, which provides a space for the temporary control of the exchange of data when the interface is controlled. In the embodiment, the buffer 32G can be further divided into two parts, temporarily storing the system body moved by the micro control unit 310, and the knife is a system test device control unit for temporarily storing the moved by the micro control unit. To the micro control unit 310, buffer 310 punch. Here, the cycle == 4 = rib loading to the slow w surface control module 300 to the micro control unit 31 缓冲器, buffer 1379234 PSPD-2008-0034 29393twf.d〇c/n and the central processing unit (10), the interface control module 3 (10) is used to read the system firmware in the buffer 320 to perform the booting operation. The following is a storage instruction with the storage device controller ls〇 The storage device controller 150. The clothing control device 300 is in the form of a storage device with a storage device control L as shown in the embodiment. Intensive interface control The unit 34 〇 j and the storage device "the collision unit H", in other embodiments, the surface control module & 300 $ may be only the (four) interface control unit 34 〇. In the present embodiment, the peripheral device control unit %(4) is more than two address mapping register (AddreSSMappingRegister) 331 (four) save ^ 333 ' to record the system data and the system's initial physical (four) address and entity The _ mapping relationship of the address. The tool body interface control unit 34 is lightly connected to the micro control unit 31 缓冲 and the buffer η; f ' and is intercepted to the central processing unit via the control crystal group 12 = = interface control unit 34 〇 includes the body address register 341 Ϊ 343. The address address register 341 is used to temporarily store the address carried by the read request sent by the UG 70 UG, so that the "face control unit 340 reads from the buffer 320 according to the address = body. The blade data buffer 343 is used to temporarily store the system firmware read according to the above address. In addition, the 'cut-body interface control unit 34 可 is permeable to the system Boolean wheel 2, and is coupled to the central processing unit via the control chip set 120, that is, the 'Left interface control unit 3 40 can be used to pass the system 12 1379234 PSPD -2008-〇〇34 29393twf.doc/n 136G transmitted read request decoding, and according to this read 2 unaddressed, to access the silkworm access system dynamic transmission interface 36, for example Sequence surrounding _

Wfaee's SPI) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Storage device interface control unit 350 to micro control unit 31

The buffer 32' is consuming and is consuming to the central processing unit 110 via the control chip set (10). After the central processing unit 110 reads the tidal body through the subtraction interface control unit 34 而 and initializes the storage device interface control unit 35 ’, the storage module 140 can be accessed through the storage device interface control unit.

The storage device interface control unit 350 further includes a task register 351 and a firmware loading interface 353. The task register 351 is used to provide a set of functions for writing, capturing, and controlling the data area of the storage module 14A by the software of the power supply system 100. The firmware loading interface 353 function is similar to the task temporary storage 351' is to provide a set of hardware configuration control interface, so that the software can write or read the system stored in the storage module just through this interface. firmware. In addition, the storage device interface control unit 350 can also be coupled to the central processing unit 110 via the control chipset 12 through the system data transmission interface 3-0. The system data transmission interface 370 is, for example, a Peripheral Controller Interface (PCI) bus bar 'PCI Express bus bar, parallel high-order attachment technology (paraUel Advanced Techn〇1〇gy 13 1379234 PSPD-2008-0034 29393twf.doc/ n

Attachment ’ PATA ) bus and serial high-end attachment technology (Serial

Advanced Technology Attachment (SATA) is one of the bus bars. When the π 书 土 电 电 田 田 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存At this point, the micro control unit will send the load unfinished signal to the central processing unit 11〇, so that the central processing unit ιι〇 temporarily? Execute the boot process. After the micro control unit trains the system to load into the buffer 32 through the peripheral device control unit 330, the micro control unit 310 sends a load completion signal to the central processing unit u, and the central processing unit 11 transmits The body interface control unit 34 reads the system firmware of the buffer 320 to perform the boot process. °° Here, it can be set on the micro-control solution. (4) Bu: Use 311 to transmit the loading unfinished signal or the loading completion signal and the i example to control how to control the central processing unit 110. - Partial 10,000 block diagram of the computer system shown in the embodiment. Referring to FIG. 4 in March, the slanting foot 4 Λ 1 · & central processing unit 110 performs resetting, and the control pin 3U used for control + The turn-in terminal of the reset H-use micro-control unit 310 AND Gate 410 is connected to the logic gate (L〇gic is connected to the central processing unit 1ω. The output terminals of #35 and 41G are limited to this. In this second; f It should be understood that the present invention does not pass through the system transport interface 36 311 or pin 4_ to the input of the logical 2::me transmission interface 370 and the weight 410 (not shown). According to 1379234 pSPD- 2008-0034 29393twf.doc/n This 'false reset signal is "1", the load unfinished signal is "〇,, then, enter. After the line avoidance and the transport difference" logic and gate 410 will output a The signal ''〇, and is transmitted to the central processing unit 110' to cause the central processing unit 11 to pause. Otherwise, the reset signal is assumed to be "1" When the load completion signal is "i,", after the logic is performed, the logic and gate 410 outputs a signal "1" and transmits it to the central processing unit 110' to start the central processing unit 11 〇 <> However, this is merely an example and is not intended to limit the implementation of the present invention. The present invention also provides a corresponding method for opening the computer system 100 with the following method. FIG. 5 is a flow chart showing a booting method according to an embodiment of the present invention. Please refer to FIG. 2, FIG. 3B and FIG. 5 simultaneously. First, in the steps. In S505, when the power is supplied to the computer system, the micro control unit 3 transmits a load uncompleted signal to the central processing unit 11A, so that the central processing unit U0 suspends the execution of the boot process. Example #, The incomplete signal is logically ANDed with the reset signal used to control the central processing unit 110, and the central processing unit 110 is suspended. Next, in step S510, the micro control unit 31 is configured to be stored. The first program section of the system firmware 145 in the group 140 is loaded into the buffer state 320. The micro control unit 31 first sets the firmware address mapping register 333 in the peripheral device control unit 330, and then the system The firmware 145 moves to the buffer 320. This is because the system firmware 145 in the storage module 140 is directly purchased through the system firmware transmission interface 36, which may cause a problem of read delay. The system firmware 145 is moved to the buffer 1379234 PSPD-2008-0034 29393twf.doc/n 320. In detail, the system firmware 145 can be divided into a plurality of program sections depending on the capacity of the buffer 32A. When the power is turned on, the internal micro control unit 310 of the storage device 13 starts to read the code of the first program segment from the storage module 14A into the buffer 32 of the storage device. The first program section refers to the section where the address addressed by the first read request is located when the central processing unit 110 is powered on. Here, a scenario area _ segment size A lOOOOh is assumed, and the address of the first program section is assumed to be FOOOOh-FFFFOh. After that, after the first program section is all loaded into the buffer 320, as shown in step S515, the micro control unit 31 transmits the load completion 5 holes to the central processing unit H0, so that the central processing unit 11 〇 Start the boot process. That is, after the code of the first program section is read into the buffer 320, the micro control unit 31 transmits the load completion signal by using the control pin 311 to cause the central processing unit 11 to start the operation. Then, in step S520, the storage device 13 receives the read request transmitted by the central processing unit 11 through the system firmware/transport interface 36. When the central processing unit 110 issues a read request and the storage device 13 receives the request via the system transport interface 360, the firmware interface control unit 340 inside the storage device 130 determines the address of the read request. Whether it falls within the address of the program section temporarily stored in the buffer 320. If yes, step S530 is performed; if not, step S535 is performed. In the case that the first program section currently buffered by the buffer 320 is F0000h-FFFF0h, when the read request address falls within 1379234 PSPD-2008-0034 29393twf.doc/n FOOOOh-FFFFOh, the steps are as follows. μ%*, with the knife interface control unit 340 will read the relevant content from the buffer 32〇. That is to say, the boot block code 147 in the buffer 32 is read by the firmware interface control unit 340 to start the initialization operation. The boot block code, for example, must include the minimum requirements for initializing the storage device interface control unit 35, the control chip set 12A, and the primary memory 160. The firmware interface control unit 340 uses the address of the read request to read φ to obtain the program segment of the boot block code that is preloaded in the buffer 320, and the data corresponding to the address. The firmware data buffer 380 is stored in the firmware interface control unit 34 via the internal data sink 380. The body interface control unit 340 then transmits the data stored in the firmware data temporary 343 back through the system firmware transmission interface 36. However, the central processing unit 110 will continuously read the system firmware 145' via the system firmware transfer interface 360 to complete the initialization of other hardware on the computer system 1. On the other hand, when the address required for reading (for example, E2〇〇〇h) does not fall within • F〇〇〇〇h-FFFFOh, as shown in step S535, the firmware interface control unit 34 can pass through the UI. The Tongwei blade transmission interface 360 returns an error message to the central processing unit 110. Then, in step S540, the micro control unit 31 loads the program section corresponding to the read request from the storage module 14A according to the address carried by the read request. For example, the micro control unit 31 载入 loads the program segment of E0000h-EFFF0h from the storage module 140 into the buffer 320 according to the address E2000h of the central processing unit 110. Thereafter, 17 1379234 PSPD-2008-0034 29393twf.doc/n returns to step S520. - It should be noted that, in the above step S535, when the element 110 receives the error message returned by the 1-blade interface control unit 340: Nothing will be done, and the change is made to make the micro-control fresh element move down = program area segment. Taking the BI0S code as an example, when the program requires the address of the area f to execute another piece of code during execution, a command φ for reading the start address of the sector and a code can be added before the jump. An instruction to wait for the zone to play time. The slice of 7 is the excitation s, according to the embodiment of the present invention. . The king code is not intended. Please refer to Figure 6, "farjumpe2 (9) (1), ^ program code to jump to another section of the instruction. And "Read E0_": address. "Wait 1Gms" is used to wait for the section to move you here, the special area The time of the segment shift is determined according to the time when the micro control unit moves the program segment to the buffer 32G. The step S5〇5_step S540 is repeatedly performed to complete the _ Γ control unit 350, the control chip group 120, and The main memory == work. After that, the central processing unit can access the data in the storage module M0 through the memory device control unit 350. The following is an example of the data access steps. The method for accessing data according to the embodiment is shown in FIG. 2. Referring to FIG. 2 and FIG. 7, the central processing unit 11 first sets the medium through the storage device interface control=350. Internal fine-grained loading interface (brain coffee) 353. Among them, 'Wei blade body loading interface dressing including system Bo Bo 145 wants to pass 1379234 PSPD-2008-0034 29393twf.doc/n to the main memory 160 target address (Target Address), to read The R 〇 M Base Address of the 勒 勒 勒 145 and the Move Size of the system firmware 145 to be read. Then the storage device interface control unit 350 initiates a direct memory storage. The DMA Enable ' DMA^ Direct Memory Access is taken to trigger the micro control unit 310.

Then, in step S710, the micro control unit 310 can load the other program sections of the system firmware 145 in the storage module 14 into the buffer 32 according to the firmware loading interface 353. In detail, the micro control unit 31 设定 sets the firmware address mapping register 333 in the peripheral device control unit 330 according to the starting address set by the firmware base address, and then stores the storage module 140. After the other program sections of the system firmware 145 are moved to the buffers #, , , ^, as shown in step S715, the data in the human transport buffer 320 is transmitted through the system data transmission interface 370 to the main memory (10). Storage device

70 35() converts the data loaded into buffer 320 into a transport packet on the interface 以 to be transmitted to the address of the primary memory 160 that is only in the destination address. The second step = step 715 and step S715 until all the orders are loaded to the main memory 160. According to this, the central processing body (4), but the direct ===: to read the system diligence = saving via the material to be transmitted 1379234 PSPD-2008-0034 29393twf.doc / n. f - mention is 'in the above storage device The controller i5〇's 写 过 储存 储存 储存 储存 储存 储存 储存 亦 亦 亦 亦 亦 亦 亦 亦 亦 亦 亦 亦 亦 亦 亦 亦 控制器 控制器 控制器 控制器 控制器 控制器 控制器 控制器 控制器 控制器 控制器 控制器 控制器 控制器 控制器 控制器 控制器 控制器 控制器 控制器 控制器 控制器 控制器The length of the system is off, the body base address of the person to be written, the DataPort, and then the start-write signal. _ Ϊ = said that the micro control unit 310 will be triggered, so that the micro control unit sets the start address of the mobile device base address to be written, and the mobile device address mapping in the peripheral device control unit 330 temporarily stores 333°. . Thereafter, the data to be written is transferred to the buffer 32. The central processing unit writes the system $blade, and the system to be written is also continuously moved to the buffer E 32〇. After the data of the buffer 32() reaches a write level=segment size, the peripheral device control single magic light will write one of the program segments of the system dynamics in the buffer 320 to the storage module. Writes are repeated this way until the entire system firmware is completely written. In the above embodiment, the storage device controller (10) is integrated in the storage device, however, in other embodiments, the storage device controller 15 can also be integrated in the motherboard 17G. As shown in Figure 8. FIG. 8 is a block diagram of a computer system in accordance with another embodiment of the present invention. The computer system ^ includes a central processing unit 810, a control chip set 82A, a storage device controller 830, a storage module 84A, and a main memory 85A. The central processing unit 810, the control chip group 820, the storage device controller 83A, and the main memory unit 850 are disposed in the motherboard 860. The control chip set 820 is respectively surfaced 20 1379234 PSPD-2008-0034 29393 twf.doc/n to the central processing unit 810, the storage module 84 〇 and the main memory 85 〇. In the present embodiment, the storage device controller (4) {integrated in the control chipset (4), and the central processing unit 810, the control chipset 820, the storage device controller 83, the storage module 84A, and the main memory energy of the present embodiment respectively The power/b of the central processing unit, the control chip set 160, the storage module 140, and the main memory 160 are the same or similar. Therefore, it will not be repeated here. In addition to the board integration, it can also be a single-device. Here, it is not == whole person=1. In the above embodiment, the system object and system data are used: in the module, according to which the host can be saved. The cost of using the two bodies in the board. In addition, the 'more practical-storage processing unit can be through the present invention, and the above embodiments are disclosed as above, but it is not intended to limit the knowledge of the technical field to the general knowledge, without leaving the hair. Fan _ 'When you can make some changes and retouching, so this insurance•, after the sight (four), please define the side; subject to. BRIEF DESCRIPTION OF THE DRAWINGS Figure θ 疋 、 、 、 、 、 电脑 电脑 电脑 电脑 电脑 电脑 电脑 电脑 电脑 电脑 电脑 电脑 电脑 电脑 电脑 电脑 电脑 电脑 电脑 电脑 电脑 电脑 电脑 电脑 电脑 电脑 电脑 电脑 电脑 电脑 电脑 电脑 电脑 电脑 电脑 电脑 电脑 电脑 电脑 电脑 电脑 电脑-0034 29393twf.doc/n Figure. In accordance with an embodiment of the present invention, a storage device (4), a block diagram of a storage device having a memory controller, in accordance with an embodiment of the present invention. ,

Block 7 is a partial view of the invention of the present invention. FIG. 5 is a flow chart of the method for riding the display according to the present invention. FIG. 5 is a partial flow of the BI〇S according to the present invention. The method is a partial process of the BI〇S. Method block diagram of the data Figure 8 is a side view of a computer system according to another embodiment of the present invention. [Main component symbol description] 100, 800: computer system 110, 810: central processing unit 120, 820: control chip Group 130: storage device 140, 840: storage module 150, 830: storage device controller 160, 850: main memory 170, 860: motherboard 22 1379234 PSPD-2008-0034 29393twf.doc / n ' 141: firmware Area 143: Data Area 145: System Firmware 147: Boot Block Code 149: Run Block Code 300: Interface Control Module 310: Micro Control Unit 311: Control Pin φ 320: Buffer 330: Peripheral Device Control unit 331: data address mapping register 333: firmware address mapping register 340: firmware interface control unit 341: firmware address register 343: firmware data register 350 · · storage device interface control Unit 351: Task Register • 353 ·· Firmware Loading Interface 3 60: system firmware transmission interface 370: system data transmission interface 380: internal data bus 401: reset pin 410: logic and gate S505~S540: steps S705 to S715 of the booting method according to an embodiment of the present invention: Method for accessing data in an embodiment step 23

Claims (1)

1379234 101-6-26 Year of the Amendment This application area: --- 1. A storage device controller, comprising: a micro control unit coupled to a central processing unit, when powered to the storage device controller At the time, the micro control unit sends a load to the central processing unit to cause the central processing unit to suspend execution of a power-on sequence; a buffer is coupled to the micro-control unit; The unit is coupled to the micro control unit and a storage module, wherein the peripheral device control unit is configured to load a system firmware of the storage module into the buffer, and an interface control module, coupled Up to the micro control unit and the central processing unit 7L, the interface control module is configured to read the system in the buffer; wherein, when the central processing unit suspends executing the booting process, the micro control Loading, by the peripheral device control unit, a first program segment of the system firmware disposed in the storage module to the buffer, when the first program segment is all loaded into the buffer Thereafter, the micro control unit sends a load completion signal to the central processing unit, so that the central processing unit reads the firmware of the system firmware of the buffer through the interface control module; When the interface control module receives the read request from the central processing unit, it determines whether the address of the read request falls within the address of the first program segment stored in the device, if The address of the read request falls within the address of the first program segment temporarily stored in the buffer 24 1379234 j 〇 1-6-26 - the address according to the read request, the transparent interface (4) transmitting, in the module buffer, the code of the first program section of the sarcophagus to the t-processing unit; if the address required for the reading does not fall in the first-program section, The fresh element is based on the read address of the face. The health of the (4) rib is corresponding to the second to the buffer. In the case of the storage device controller described in the first item, the micro-control unit further includes a control pin, and the control pin transmits the unfinished shouting signal. And the control pin and the reset pin of the central processing unit are connected to the input end of the logic and the gate, and the output end of the logic and the gate is coupled to the central processing unit. 3. The storage device controller as claimed in claim 1, wherein the interface control group comprises a secret interface surface unit, and the shaft body control unit comprises: a second two-dimensional object address H' temporary storage of the towel The address requested by the domain management unit is such that the interface interface control unit reads the system firmware from the buffer according to the address; and - the object data temporarily stores H, the temporary mechanical basis The system firmware read by the health center. 4. The storage device controller of claim 3, wherein the firmware control unit further comprises a system body transmission interface, wherein the system transmission interface is a serial peripheral interface (SPI). One of the busbars, the Industiy Architecture (ISA) bus and the low pin count (L〇wpinC〇unt, 25 1379234 101-6-26 LpC) bus. 5. As described in claim 3, the interface control module further comprises: a device control device, which is connected to the central processing unit, when the central processing unit executes the element and the storage After the device interface control unit is initialized, the storage device interface control unit accesses the storage mode. 70 ^ The storage of her coffee, which takes two tons of _ _ group to write, read inside _ ^ = ^ face 'ribs write people or read Wei in the storage module 7. If t please please The five said memory device controllers, the 21 storage unit (4) unit further includes a pure data ageing surface, and the ηBei transmission interface is a peripheral controller interface (Pe away from - Corner Interfaee, ρα) bus bar, ρα Εχρ卿汇排排, Parallel Advanced Techn〇i〇gy Attachment 'PATA) bus and serial high-end attachment technology (such as Advanced Technology Attachment, SATA) bus - ο 8. a motherboard, comprising: a central processing unit; - a storage device control gamma, secret to the towel processing unit; and 26 1379234 101-6-26 - a storage group 'connected to the storage device control (four), and the storage The module has at least one system; and, t, two: When the motherboard is sent, the storage device controller sends 7 packets to the towel processing unit to make the central processing unit = pause Obsessed -_Program's county control (4) is configured in the storage module A first program section of the system is loaded into the buffer of the storage controller, and when the first program section is all loaded to the buffer, the remote control is sent to the carrier. Transmitting the central processing unit to enable the central processing unit to pass the storage device controller to perform the booting process; wherein, when the storage device controller receives the central processing unit When a read request is made, it is determined whether the address requested by the read falls within the address of the first program segment temporarily stored in the buffer, if the address of the read = request falls in the buffer In the address of the first program section temporarily stored in the device, the memory device controller reads the system in the buffer according to the address of the read request, and the first program section of the body a code to return the $ central processing unit; if the address requested by Wei reads does not fall within the first private section, the storage miscellaneous control verifies the address of the read request, from the storage mode The corresponding program in the group, the _ body, is loaded into the buffer. 9. The motherboard as claimed in claim 8, wherein the device controller comprises: a micro control unit coupled to the central processing unit, and when the power is supplied to the motherboard, the control unit is The loading unit is not completed _ to the ^ 27 1379234 101-6-26 processing unit, the buffer is coupled to the micro control unit; a peripheral device control unit is coupled to the micro control unit and the storage module, the periphery The device control unit is configured to load the storage module firmware into the buffer; and an interface control module coupled to the micro control unit and the central processing unit 7G. The interface control module is used The body in the buffer is read, wherein 'when the micro control unit transparently passes the system through the peripheral device control unit, the Lai unit sends the completion signal to the central processing unit. /0 = Please refer to the motherboard mentioned in item 9 of the patent scope. The control 7L further includes: (4) = the pin is transmitted to the manned unfinished signal or the job is completed. The key unit 'where' the (four) pin has no central processing The single pin field is connected to the input end of the logic switch, and the logic and the output terminal are connected to the central processing unit. 11. The motherboard according to claim 9 of the patent application, wherein the element=module comprises a “lein interface control unit”, and the _ body interface control list is temporarily stored in the temporary storage unit 11 for temporarily storing the reliance sent by the central processing unit. The 'send the address' causes the (four) interface control unit to read the system firmware from the buffer; and the system register temporarily stores the 28 read according to the address 101-6-26 face control; the motherboard of the model range, wherein the medium unit is connected to the micro control unit and the eccentric central processing unit to execute the (10) body :2:: After the initialization, the central processing unit is permeable to the 杂 ( ( (4) monofilament access. A motherboard as claimed in claim 12, further comprising: - a system carcass transfer interface is coupled between the central body interface control unit; and a H Mingpo 2_ material transfer wheel interface, minus Between the central processing unit disk and the storage device interface control unit. M. As claimed in the patent scope 帛u, = include - boot block code and a running block program, = two t 2? through: the chapter blade interface control unit reads the boot area Block code to at least reduce the simplification of the interface _ unit, _ = and: the main memory, and the central processing unit through the; storage; the unit reads the running block block to perform after 15. The storage device comprises: a health storage device (4) H, touches the medium money material; and, the storage device is connected to the storage device control device (4), and the group has at least one system firmware; the child chess, the ^, when the power supply To the silk material, _ storage device controller 迗 载 载 载 未 元 峨 峨 峨 射 射 射 射 射 射 射 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The system & 4 memory device control - the configuration is stored in the storage device controller - slow = body ^ a program section is loaded into the buffer, the first program section of the storage Entering the central processing unit to open the device controller to send a load completion signal to the controller =_==: through the storage The second read memory device controller that receives the control receives the address of the current processing unit, and the address of the current address === is determined to fall in the address of the read request. The code of the program section of the body to return the processing unit; if the address requested by the read is not private, the - ^ and 'missing device control (4) according to the address of the read request, The storage module loads the corresponding second program segment in the system into the buffer. 16. The storage device of claim 15, wherein the j-module comprises a region and a data region, wherein the body region stores the body of the system. The storage device of claim 15, wherein the storage device controller comprises: a micro control unit coupled to the central processing unit, when powered to the storage device, the micro control unit Sending the load uncompleted signal to the central processing unit, the buffer is coupled to the micro control unit; 30 1379234 101-6-26 ★ - peripheral device control unit, secret to the micro control fresh element and the storage The core group 'the peripheral device control unit is used to read the buffer; and the interface control side group 'secrets to the micro control unit and the central processing unit'. The interface control module is used to read the buffer. The system in the device takes the blade body, / wherein, after the micro control unit loads the ί 该 through the peripheral device control unit, the micro control unit sends the manned message to the Central processing unit. The storage device of item 17 of the micro-control side, wherein the number to 3:: single-incomplete signal or the loading completion message is 70, wherein the control pin and the input of the central processing unit 2 'And the logic and interface! The storage device described in the 17th patent, wherein the unit 3 i body interface control fresh element, the suppression interface control body address temporary storage ^, temporarily store the address sent by the towel processing unit 'Let the coffee interface control unit read the system firmware in a five-figure η Haibu buffer 1 §; and the system is tough - 2 〇. Such as _ please patent scope I9 item storage 2 = data register ' The temporary storage is based on the position that he has read, wherein the 31 101-6-26 101-6-26 interface control module further includes a central unit = a single unit 1 to the micro control unit and the storage device interface control unit Initializing the ^^ system (4) and the storage device is referred to by the other device; the central processing unit accesses the storage device through the interface control unit. The system described in claim 20 is a body. Including 1 block code and - 'where the central processing unit Passing the remaining interface control code, and the code 'at least initializing the storage device interface control block, the control chip set and a primary memory host perform the subsequent boot process ^ reading the running block code, The 1 right boot method is applicable to the computer system, the computer (4) group 2 = single unit 2 storage device controller and -4: memory module, and the boot 1 = in the central processing unit Stop executing the 1 program; (4) central processing the early system, the controller will be configured in the storage module, and the program will be loaded into the storage device controller. The segment is all entered, the device controller transmits - the manned completion signal to the central two = the 4th central processing unit begins to perform the shutdown procedure; 32 when the storage device controller receives the central processing read request' The address of the m segment temporarily stored by the required health h is obtained; if the address requested by the read falls within the address of the segment in the buffer, the storage device controller Read the address, t buy the The first requested code of the system firmware in the buffer is returned to the central processing unit; and the x-sinus if the address requested by the read does not fall in the first-stage fun, the controller According to the address of the read request, the corresponding second program section of the first module is loaded from the storage module to the buffer. .23. The booting method as described in claim 22 of the patent application, further includes logically summing the load completion signal or the load uncompleted signal with a reset signal for controlling the central processing unit. The booting method of claim 22, wherein the first program section of the system configured in the storage module is loaded into the storage device control by the storage device control H The buffering step of the device includes: loading the first program segment of the system firmware of the storage module into the device through a peripheral device control unit of the storage device controller. 25. The booting method of claim 22, wherein after the step of transmitting the loading completion signal to the central processing unit by the storage device controller, the method further comprises: transmitting one through the storage device controller Firmware interface control unit, read 1379234 101-6-26 The secret of the buffer n towel, read the service program and the health device control n - storage device interface (4) unit and - control group = group and a main Memory initialization. [26] The method of booting according to claim 24, i after the storage device is controlled by the storage device control unit and the initialization of the chip group and the social memory, further comprising: Second, the boot device interface control unit 'reads the system to perform the boot process. 34 1379234