九、發明說明： 【發明所屬之技術領域】 本發明係種歸記憶體之管理核以及方法，更且體來 說，侧於-種制久未制者糾〈Lea議咖丨y _，咖〉策略或 是先進先獅祕偷，FI_略的梅速掃表的時間。 【先前技術】 快閃記憶體(Hash M__—非揮發性(跡她㈣之記憶體在電 源關閉時仍可保祕前寫人的資料1其他儲存媒體(如硬碟、軟碟或磁帶 等)比較，_雄猶體積小、重餘、防絲、存輯無機械動作延遲 與低耗電科性。由於快閃記龍的這些雜，因此近年來料性電子產 品、嵌入式系統或可攜式電腦等資料儲存媒體皆大量採用。 决閃Alt體主要可分雜：Nqr型快閃記題與ναν〇独閃記憶 體。職型娜己舰的優點為低龍、存取快且穩定性高，因此已被^ 量應用於可攜式電子裝置及電子通訊裝置，諸如個人電腦 Computer > PC) Mf 1¾ > ^A^^^Jl(perS〇nal Digital Assistance « PDA) 以及轉頻器(Set，B()x，STB)等。NAND型快閃記憶體是專門為資料儲存 用地而wf·之㈣記憶體，通常應用於儲存並保存大量的資料的儲存媒 "如可攜式 s 己憶卡(SDMemoryCard，CompactFlash Card，Memory Stick 等等）。备快閃兄憶體在執行寫入(Write)、抹除(Ε·)及讀取(Read)運作時， 可透過㈣的電綠合(CcmpIing)有效地㈣漂浮_⑽吨G㈣上電荷 的移動’進而齡該漂浮閘可根據該電荷的移動而献下層電晶體的間值 1379197 電壓。換言之，當負電子注入該漂浮閘時，該漂浮閘的儲存狀態便會從i 變成〇;而當負電子從該漂浮閘移走後，該漂浮閘的儲存狀態便會從〇變成 1 ° 請參閱第1圖’第1圖係先前技術iNAND快閃記憶體之示意圖cNAND 陕閃5己憶體100内部由複數個區塊(bi〇ck)i2所組成。每一區塊12包含複數個 頁(page)14，每一頁η則可分為資料儲存區141以及備用區(spare扯從)142， 資料儲存區141的資料容量可為512個位元組，用來儲存使用資料，備用區 142用來儲存錯誤修正碼田⑽c〇rrecti〇n c〇de，ECC) ^與奶尺型快閃記憶 體不同，NAND型快閃記憶體之讀取與寫入單位皆為一個頁，資料讀寫的 動作必須先向晶片發出讀取或寫入指令後才可進行。 然而，快閃記憶體本身無法原地直接更改資料(update_in place)，也就是 說’若要對已寫過資料位置再次寫入資料時，必須先執行抹除的動作。而 且NAND快閃記憶體寫人單位顧，而抹除單位為區塊^所以當向晶片發出 寫入請求時，必須先抹除一整個區塊12，才能把資料寫入至該區塊12的頁 14。而且一般來說一個區塊12抹除動作需要的時間約為一個頁“寫入動作 時間的10〜20倍。如果當一個抹除的單位大於寫入的單位，這表示若要執 行區塊抹除動作，必須先將欲抹除區塊中的有效頁搬移至其它區塊後才可 進行。 由於上述快閃記憶體的特性，因此能有效管理快閃記憶體的管理系統 是非常需要的。傳紅’目祕f松隨作紐存顧所設計的槽案系統 架構有如Microsoft FFS、师82與YAFFS等髓系統。這些槽案系統較有 6 1379197 效率，但只能使用在管理以快閃記憶體建構之儲存媒體上。另—種作法則 是採用一 FTL(FlashTrans丨ationLayer)中間層，將快閃記憶體模擬為區塊裝 置，如硬碟機一般。因此在FTL的上層就可使用一般的檔案系統，如FAT32 或EXT3等等，對下層發出區段(sector)讀寫請求，經由ftl來存取快閃記 憶體内容。對NAND Flash做資料存取則’ FTL包含一個邏輯-實體位址對 照表LUT，用以紀錄邏輯區塊位址〈Logical Block Address，LB A〉轉換成 實體區塊位址〈Physical Block Address，PBA〉的關係，邏輯區塊位址是棺 案系統要求存取資料的區塊位址，實體區塊位址則是邏輯區塊位址所對應 到的實際在快閃記憶體中的區塊位址。 請參閱第2圖，第2圖係儲存邏輯位址與實體位址之一範例。假設每一 區塊有η頁的資料。當上層檔案系統要求讀取邏輯位址1的資料，透過邏 輯-實體位址對照表16得知邏輯位址1對應之實體位址為(區塊〇·頁1)，所 以系統會取得實體位址(區塊〇-頁1)内的資料並傳回。若上層檔案系統要求 更新邏輯位址3的内容，由於不允許直接再次寫入，所以系統之動作為將 實體位址(區塊0-頁〇)至(區塊〇-頁2)寫入(區塊2-頁0)至(區塊2-頁2)，再 將更新資料寫入至(區塊2_頁3)，並將實體位址(區塊〇-頁4)到(區塊〇-頁η-1) 寫入(區塊2-頁4)到(區塊2-頁η-l) ’然後將實體位址(區塊〇)的資料標示為 無效，最後將位址對照表丨6中邏輯位址3之對應資訊由(Β0-Ρ3)改為 (Β2-Ρ3)，如此下一次要存取邏輯位址3的資料，就會對應至實體位址(區塊 2-頁3)存取資料。 請參閱第3圖，第3圖係先前技術之對照表16與NAND快閃記憶體存 7 1379197IX. Description of the invention: [Technical field to which the invention pertains] The present invention relates to a management core and method for a memory, and more specifically, a side-by-side system for a long time is not corrected. Strategy or advanced lion thief secret, FI_ slightly time to speed the table. [Prior Art] Flash memory (Hash M__- non-volatile (the memory of her (4) memory can still protect the data of the person before the power is turned off 1 other storage media (such as hard disk, floppy disk or tape, etc.) In comparison, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Computer and other data storage media are widely used. The flashing Alt body can be divided into several types: Nqr flash flashing and ναν〇 single flash memory. The advantages of the Na Na ship are low dragon, fast access and high stability. Therefore, it has been applied to portable electronic devices and electronic communication devices, such as personal computers Computer > PC) Mf 13⁄4 > ^A^^^Jl (perS〇nal Digital Assistance « PDA) and transponders (Set , B () x, STB), etc. NAND-type flash memory is specifically for data storage and wf · (four) memory, usually used to store and store a large amount of data storage media "such as portable s Memory card (SDMemoryCard, CompactFlash Card, Memory Stick, etc.) When the brother recalls the write (Write), erase (Ε·), and read (Read) operations, it can effectively (4) float _ (10) tons of G (four) on the movement of charge through the fourth (CcmpIing) The floating gate can provide a voltage of 1379197 between the layers of the transistor according to the movement of the charge. In other words, when the negative electron is injected into the floating gate, the storage state of the floating gate changes from i to 〇; After the floating gate is removed, the storage state of the floating gate will change from 〇 to 1 °. See Figure 1 'Figure 1 is a schematic diagram of prior art iNAND flash memory. cNAND Each block 12 comprises a plurality of pages 14 each of which can be divided into a data storage area 141 and a spare area (spare pull) 142, data storage The data capacity of the area 141 can be 512 bytes for storing the usage data, and the spare area 142 is used for storing the error correction code field (10) c〇rrecti〇nc〇de, ECC) ^ Unlike the milk-size flash memory, The read and write units of the NAND flash memory are all one page, and the data read and write operations must be This can only be done after a read or write command is issued to the wafer. However, the flash memory itself cannot directly change the data (update_in place) in place, that is, 'If you want to write the data again to the already written data location, you must first perform the erase operation. Moreover, the NAND flash memory writes the unit unit, and the erase unit is the block. Therefore, when a write request is issued to the wafer, an entire block 12 must be erased before the data can be written to the block 12. Page 14. Moreover, in general, the time required for a block 12 erase operation is about 10 to 20 times the write operation time. If an erased unit is larger than the written unit, this means that block erase is performed. In addition to the action, the valid page in the block to be erased must be moved to other blocks before it can be performed. Due to the characteristics of the flash memory described above, it is highly desirable to be able to effectively manage the management system of the flash memory. Chuanhong's secrets are designed by the company, such as Microsoft FFS, Division 82 and YAFFS. These slot systems have 6 1379197 efficiency, but can only be used in management to flash. The memory is constructed on the storage medium. Another method is to use an FTL (FlashTransation Layer) middle layer to simulate the flash memory as a block device, such as a hard disk drive. Therefore, it can be used on the upper layer of the FTL. A general file system, such as FAT32 or EXT3, issues a sector read and write request to the lower layer, and accesses the flash memory content via ftl. For FAN data access, the FTL contains a logical-entity. The address comparison table LUT is used to record the relationship between the logical block address <Logical Block Address, LB A> and the physical block address (Physical Block Address, PBA>, and the logical block address is required by the file system. The block address of the data, the physical block address is the block address actually corresponding to the logical block address in the flash memory. Please refer to Figure 2, Figure 2 is the storage logic bit. An example of address and physical address. Assume that each block has n pages of data. When the upper file system requires reading the data of logical address 1, the corresponding logical address 1 is obtained through the logical-physical address comparison table 16. The physical address is (block 〇·page 1), so the system will retrieve the data in the physical address (block 〇-page 1) and return it. If the upper file system requires updating the content of logical address 3, It is not allowed to write directly again, so the action of the system is to write the physical address (block 0-page 〇) to (block 〇-page 2) (block 2-page 0) to (block 2-page) 2), then write the update data to (block 2_page 3), and write the physical address (block 〇 - page 4) to (block 〇 - page η-1) (block 2 - page 4) to (block 2 - page η-l) ' Then the physical address (block 〇) data is marked as invalid, and finally the address is compared with the logical address 3 in Table 6 The corresponding information is changed from (Β0-Ρ3) to (Β2-Ρ3), so the next time you want to access the data of logical address 3, the data will be accessed corresponding to the physical address (block 2 - page 3). Figure 3, Figure 3 is a prior art comparison table 16 with NAND flash memory 7 1379197
- 取之示意圖。晶月内可供程式使用的記憶體有限，不可能一次將全部NAND • 鋼記憶體所有的區塊位址都記錄起來。也就是說，對照表16必須隨著棺 案系統資料存取的要求，去動態的建立或更新對照表16的内容^對照表16 . 會預H魏謂22來常駐靖NAND綱記紐zone G的區塊位 址，原因是因為NAND快閃記憶體的z〇ne 〇通常是用來存放標案系統 FAT的地方’而餘純為了存取财會經常需要存取FAT表。所以為了 籲提升對,、、、表I6的效&，會先把存放FA丁的區塊位址常駐記錄在對照表Μ 的第一記憶空間22内，這樣就不用經常為了 FAT而重建對照表.若是 檔案系統所要求存取資料的位址已被目前的對照表％記錄於第二記憶空間 Μ，亦即目前的域表LUT不需要重建。如果下—讀㈣統使用到目前 對照表LUT所沒有記錄到的NAND快閃記憶體位址，則棺案系統會以樓案 系統所要求存取資料的區塊位址為中心點，向上與向下合計約ι〇〇〇個區塊 範圍掃也這些區塊的冗餘(Redundant)區域來建立對照表咖，亦即將新 籲的區塊位址的相關資訊紀錄於對照表16的第二記憶空間24。 由於建立 <更新〉對照表16時所需的資訊，一般來說是存放在ΝΑΝ〇 快閃記憶體之冗餘區域裡，所以執行建立〈更新〉對照表i6的動作，就必 ^把^圍内的所有區塊的冗餘區域都掃描讀出一次。這個動作是必需但卻 .疋相田友有效率。因此，如果能改進掃描讀取對照表16的時間’則快 .憶齡、統的存轉可大大提升。 【發明内容】 8 1379197 有鑑於此，本發明係提供一種nand快閃記憶體之管理系統以及方 法’利用久未使用者移出〈Least Recently Used，LHU〉策略或β先進先出 (Firstln First Out，FIFO)策略的方式加迷掃描對照表的時間，以改善先前技 術的問題 本發明之-目的係提供-種快閃記憶體管理系統，其包含快閃計憶 體、複數侧絲、複數料數如及騎單元。触閃記㈣包含複數 個記憶叢集’每-記憶叢集包含至少-區I每―對照表對應於其中之一 記憶叢集，用來嫌該賴記麵之實舰齡轉換成—職系統存取 之邏輯區塊位址的關係。每-計數器對應於其中之—聰表，用來計算一 預設時_職之麟絲的棘她。該躺單元用來鎌賴數個計 數器所計算之棘錄’更_魏個對絲以及騎應之該複數個記憶 叢集。 依據本發日壯述之實施例’該_單元係絲控制更新存取次數最少 的植器賴應的·《表以及轉，日絲騎應之記,隨集。該快閃記憶體 係一 NAND快閃記憶體。 依據本發明之另-目的係提供—種快間記憶體管理系統，其包含其包 含快閃計憶體、複數細《表、暫存器以及躺單心該網記憶體包含 複數個記憶叢集’每-記憶叢集包含至少—區塊。每—龍表對應於其中 之-記憶叢集，用來記錄該快閃記憶體之實體區塊位址轉換成—標案系统 存取之邏輯區塊位址的關係。該暫存器用來記錄該複數個舰表。該判斷 單元用來依據該複數個對照表儲存於該暫存㈣次序，更新該複數個對照 9 1379197 表以及所對應之該4复數個記憶叢集。 依據本發明上述之實施例，該暫存器係-先進先出(First In First 〇ut， FIFO)暫存g 斷單元制來細㈣最先被儲存於該先進先出暫存器 對照表以及該賴表所對應之記㈣集。該_記憶體係-NAND快閃記 憶體。 本發月之X目的係提供一種加快—快閃記憶體存取效率之方法，該 快閃記憶體包含魏個記憶錢，每—記憶叢集包含至少-_blQCk)，該 籲方法包含下列步驟：（輕生減個對絲，每表對應於其中之-記 隱叢集’用來鱗該快閃記憶體之實體區塊位址轉換成—儲系統存取之 k輯區塊位址的關係，（b)計算—職時間崎—賴表的存取次數；以及 (C)依據絲對絲所計算的存取次數，複數侧絲以及所對應 之該複數個記憶叢集。 依據本發日壯述之實補’步驟(e)包含更新存取次數最少的計數器所 對應的對照表以及該對照表所對應之記憶叢集。該快閃記憶體係一·^ 快閃記憶體。 本發明之再-目的係提供—種加快—快閃記顏雜效率之方法，該 决門讀體包含複數個記憶叢集，每__記憶叢集包含至少_區塊(此洗)，該 方法包3下列步驟·（a)產生複數個對照表，每—對照表對應於其中之一記 隐叢集’用來記錄職閃記憶體之實體區塊位址轉換成_齡純存取之 I輯區塊位址的關係，（b)提供_先進先出(朽时&細⑽，fif〇)暫存器以 記錄該複數個對照表；以及⑹依據該複數個對照表儲存於該先進先出暫存 1379197 器的次序’更雛先被财於該先秋崎存騎絲錢雜照表所對 應之記憶叢集。 依據本發明上述之實施例’該快閃記憶體係、—NAND_記憶體。 為讓本發明之上勒容能更_純，下文特舉較佳實施例並配合所 附圖式，作詳細說明如下。 【實施方式】 〇月參閱第4圖’第4圖係本發明之第—實施例之快閃記憶體管理系統 10之功能方塊圖。快閃記憶體管理系、统10包含判斷單元12〇、計數單元 130、轉換單元140以及快閃記，隨16〇。在本實施例中，快閃記憶體· 可為NAND [綱a己憶體，其内部的每—個區塊(肠⑻均由個耳办㈣ 所組成，每-個頁為2K位元組(bytes)或是512位元㈣大小。轉換單元 140包含複數個邏輯·實體位址對照表咖，為便於說明，本實施例中轉換 單元包含8個對照纟LUT1_LUT8，實際上對照表的健可視設計需要調 整。每-對照表LUT1-LUT8分別對應於快閃記憶體16〇其中之一記憶叢集 (partition) ’用來紀錄該對應記憶叢集的實體區塊位址(拖知㈤m〇ck Address > Block Address .. lba)的轉換關係。舉例來說，對照表LUT1對應於記憶叢集2〇3，對照表 LUT3對應於記憶叢集2〇卜對照表咖6對應於記憶叢集2〇2。轉換單元 ⑽的資料容量可視對照表LUT的個數或是對縣LUT的所對應的每一記 憶叢集的大小調整之。計數單元13Q包含複數個計㈣muNT，每一計數 器C0UNT1-C0UNT8分職應於其中之—對喊LUT1_LUT8，用來計算 1設__之韻表的存取魏。_元12G係―齡於記憶體 之軟體程式碼。 凊一同參閱第4圖以及第5圖，第5圖係第4圖之快閃記憶體管理系 運作方法流程圖。s棺案系統丨π下達—指令欲存取快閃記憶體1 之魏叢集時(步驟5〇2)，判斷單元⑶會先判斷該欲存取的記憶叢集是否 有對應的對M LUT(频5G4)。如林，則概鑛絲錄據檔案系統 150的指令内的邏輯區塊位址’找出快閃記憶體⑽_實體區塊位址，並 存取之(步驟506)。舉例來說，檔案系統15〇欲存取記憶叢集2〇1的某一區 塊的資料，®為對照表LUT3對應齡記憶叢集201的區塊資料，所以對 照表LUT3會通知檔案系統15〇該指定區塊對應於快閃記憶體16〇的記憶 叢集201的實體區塊位址。此時，對照表LUT3對應的計數器c〇〇NT3計 數值的累計次數會加K步驟508)，以表示對照表LUT3已被存取一次。同 樣地’當檔案系统ISO欲存取記憶叢集202的某一區塊的資料，則對照表 LUT6會通知檔案系統15〇該指定區塊對應於快閃記憶體16〇的記憶叢集 202的實體區塊位址。此時，對照表LUT6對應的計數器C〇UNT6計數值 的累計次數會加1，以表示對照表LUT6已被存取一次(步驟508)。 如果檔案系統150欲存取記憶叢集204的某一區塊的資料，但是記憶 叢集204因為先前並沒有被存取的機會，所以轉換單元140内也沒有任何 對照表有紀錄其實體區塊位址與邏輯區塊位址的關係。因此判斷單元120 會判斷依據複數個計數器COUNin_COUNT8在一預設時段内所計算之次 數(步驟510)，決定要更新哪一個對照表以及所對應的記憶叢集。舉例來說， 12 1379197 若判斷單元120偵測到計數器C0UNT1的計數值最小(步驟51〇),表示在該 預設時段内，記憶叢集203被存取的次數最少，因此該判斷單元12〇就會 控制更新對照表LUT1 ’使得對照表LUT1重新紀錄記憶叢集2〇4的實體區 塊位址與邏輯區塊位址的對照關係(步驟512)。之後，就會將轉換單元mo 内的所有計數器COUNT1-COUNT8全部歸零(步驟514)。 請參閱第6圖’第6圖係本發明之第二實施例之快閃記憶體管理系統 20之功能方塊圖。管理系統20包含判斷單元220 '先進先出暫存器230、 轉換單元140以及快閃記憶體160。在本實施例中，快閃記憶體16〇可為一 NAND快閃記憶體，其内部的每一個區塊(Block)均由64個頁(page)所組 成，每一個頁為2K位元組(bytes)或是512位元(bits)大小。轉換單元240 包含複數個邏輯-實體位址對照表LUT，為便於說明，本實施例中轉換單元 包含8個對照表LUT1-LUT8 ’實際上對照表的個數可視設計需要調整。每 一對照表LUT1-LUT8分別對應於快閃記憶體160其中之一記憶叢集 (partition) ’用來紀錄該對應記憶叢集的實體區塊位址(phySicai Bi〇ck Address ’ PBA)和檔案系統所判讀的邏輯區塊位址(Logical Block Address， LBA)的轉換關係。舉例來說，對照表LUT1對應於記憶叢集203，對照表 LUT3對應於記憶叢集2(n、對照表LUT6對應於記憶叢集2〇2。轉換單元 240的資料容量可視對照表的個數或是對照表LUT的所對應的每一記 憶叢集的大小調整之。判斷單元220係一儲存於記憶體之軟體程式碼。 請一同參閱第6圖以及第7圖，第7圖係第6圖之快閃記憶體管理系 統20之運作方法流程圖。當檔案系統150下達一指令欲存取快閃記憶體160 13 1379197 之記憶叢集時(步驟702)，判斷單元220會先判斷該欲存取的記憶叢集是否 有對應的對照表LUT(步驟704)。如果有，則複數個對照表會依據檔案系統 uo的指令内的邏輯區塊位址，找出快閃記憶體16〇内的實體區塊位址(步 驟5〇6)。舉例來說，檔案系統150欲存取記憶叢集201的某一區塊的資料， 因為對照表LUT3對應儲存記憶叢集2〇1祕塊資料，所以對照表LUT3 會通知槽案系統lS〇該指定區塊對應於快閃記憶體⑽的記憶叢集2〇1的 實體區塊位址，並存取之(步驟7〇6)。此時，對照表luT3會儲存於先進先 出暫存器23〇(步驟7〇8)。同樣地，當棺案系统15〇欲存取記憶叢集2〇2的 某-區塊的麟，麟照表LUT6會通知齡系統15G該指定區塊對應於 決閃》己It體160的記憶叢集2〇2的實體區塊位址。此時，對照表LUT6會 儲存於先進先出暫存器.230(步驟708)。如果接下來，檔案系統15〇又在一 人存取5己憶叢集2〇1的某一區塊的資料，此時，對照表LUT3儲存於先進 先出暫存器230的次序就會晚於對照表LUT6(步驟7〇8)。 如果槽案系統ISO欲存取記憶叢集2〇4的某一區塊的資料，但是記憶 叢集2〇4因為先前並沒有被存取的機會，所以轉換單元⑽内也沒有任何 對照表有紀錄其實體區塊位址與邏輯區塊位址的關係。因此判斷單元no 找出會最先被儲存於先進先出暫存器现的對照表以及該對照表所對應之 記憶叢集(步驟，並更狀。勒咖，虹親之例，絲進先出暫存 器230最先被儲存的是對照表LUT6，且先進先出暫存器23〇已被存滿，因 此該判斷單元22〇就會控制更新對照表，使得對照表敗0重新紀錄 ’、、叢集204的實體區塊位址與邏輯區塊位址的對照關係(步驟612)。 14 1379197 相杈於先刚技術僅有單一對照表，雖然單一對照表可以對應於較大但 位址連β的單讀叢集’―但蹄系統⑽欲存⑽區塊並*在該單一 記憶叢㈣’珊糾新單—賴表的_纽較長。但是本實施例將單 一對照表分賴數_、崎絲，每—賴表別對應至 快閃記憶體160内的一獨立守，陪f隹 苟°己隱叢集。也就是說’如果遇到先前並未存取 過-己隐叢糾’目為母—職表較小，所鱗描更輯應触存取過記憶 叢集的對縣_間_，再搭配計絲紀錄最少婦取的賴表的_ 或是暫存於先進先㈣存器的卿，本實施例更騎絲的_將可大幅 減少’故可加快存取快閃記憶體的效率。 ^ •斤述雖然本發明已較佳實施例揭露如上，然其並非用以限 疋本發明’物mt項技齡，林雌本發·精神和細内，當可 作各種更動_ ’因此本發日此保護_視_之帽專: 定者為準。 卜 【圖式簡單說明】 第1圖係先前技狀NAND,_記,隨之示意圓。 第2圖係儲存邏輯位址與實體位址之-範例。 第3圖係先前技術之對絲_ΑΝ〇_記憶體存取之示意圖。 第4圖係本發明之第_實補之侧記憶體管理纽之功能方塊圖。 第5圖係第4圖之，_記管理系統之運作方法流程圖。 圖 第6圖係本翻之第二實施例之‘關記憶體管_統之功能方塊 15 1379197 第7圖係第6圖之快閃記憶體管理系統之運作方法流程圖。 【主要元件符號說明】 10 ' 20 快閃記憶體管理系統 12 區塊 14 頁 16 對照表 22 第一儲存空間 24 第二儲存空間 100 、 160 快閃記憶體 141 資料儲存區 142 備用區 120、220 判斷單元 130 計數單元 140 轉換單元 150 檔案系統 201-204 記憶叢集 230 先進先出暫存器 COUNT 1-COUNT8 計數器 LUT1-LUT8 對照表 16- Take the schematic. The memory available for the program in Crystal Moon is limited, and it is impossible to record all the block addresses of all NAND•steel memory at one time. That is to say, the comparison table 16 must dynamically establish or update the contents of the comparison table 16 according to the requirements of the file system access of the file system ^ comparison table 16. The pre-H Wei said 22 to be resident in the NAND program New Zealand G The block address is because the z〇ne NAND of the NAND flash memory is usually used to store the FAT of the standard system. And Yu Chun often needs to access the FAT table in order to access the accounting. Therefore, in order to call for the improvement of the effect of,,, and Table I6, the block address of the stored FA is first recorded in the first memory space 22 of the look-up table, so that it is not necessary to re-establish the control for FAT. Table. If the address requested by the file system for accessing the data has been recorded in the second memory space by the current comparison table %, that is, the current domain table LUT does not need to be reconstructed. If the next-read (four) system uses the NAND flash memory address that is not recorded in the current LUT, the file system will use the block address of the data required by the building system as the center point, upward and upward. The total number of blocks in the block is also the Redundant area of these blocks to establish a comparison table, and the information about the block address of the new call is recorded in the second memory of the comparison table 16. Space 24. Since the information required to establish the <update> comparison table 16 is generally stored in the redundant area of the flash memory, the execution of the <update> comparison table i6 is performed, and ^^ Redundant areas of all blocks within the perimeter are scanned and read once. This action is necessary but it is very effective. Therefore, if the time for scanning and reading the comparison table 16 can be improved, it is fast. The memory of the age and the system can be greatly improved. SUMMARY OF THE INVENTION 8 1379197 In view of this, the present invention provides a nand flash memory management system and method 'Using a long-term user to remove <Least Recently Used, LHU> strategy or β first in first out (Firstln First Out, FIFO) The manner of the strategy adds the time to scan the look-up table to improve the problems of the prior art. The present invention provides a flash memory management system including a flash memory, a plurality of side wires, a plurality of materials, such as And riding unit. The touch flash (4) contains a plurality of memory clusters. The per-memory cluster contains at least - the area I per control table corresponds to one of the memory clusters, and is used to convert the real age of the Lai Kee into the logic of the system access. The relationship of block addresses. Each counter corresponds to one of them, the Cong table, which is used to calculate the spine of a preset time. The lie unit is used to count the number of ticks that are calculated by several counters, and the plurality of memory clusters that are supposed to ride. According to the embodiment of the present invention, the _ unit ray control is updated with the least number of accesses, and the table and the turn, the Japanese silk ride should be recorded. The flash memory is a NAND flash memory. Another object of the present invention is to provide a fast memory management system including a flash memory, a plurality of fine tables, a register, and a single memory. The memory includes a plurality of memory clusters. Each-memory cluster contains at least a block. Each of the dragon tables corresponds to the memory cluster, and is used to record the relationship between the physical block address of the flash memory and the logical block address accessed by the standard system. The register is used to record the plurality of ship tables. The determining unit is configured to store the plurality of comparison tables in the temporary (four) order according to the plurality of comparison tables, and update the plurality of comparison 9 1379197 tables and the corresponding plurality of memory clusters. According to the above embodiment of the present invention, the first in first FIFO (FIFO) temporary storage unit is finely divided (4) first stored in the FIFO register and The set of records (four) corresponding to the table. The _memory system - NAND flash memory. The X-purpose of this month provides a method for speeding up the access efficiency of flash memory. The flash memory contains Wei memory, and each memory cluster contains at least -_blQCk. The method includes the following steps: Lightly reduce the pair of wires, each table corresponds to the relationship between the block-address of the flash block that is used to convert the physical block address of the flash memory into the block address of the k-system block access, (b Calculating the number of accesses to the time-stable-based table; and (C) the number of accesses calculated based on the wire-to-wire, the complex side wires, and the corresponding plurality of memory clusters. The supplemental step (e) includes a lookup table corresponding to the counter that updates the least number of accesses and a memory cluster corresponding to the lookup table. The flash memory system is a flash memory. The re-purpose of the present invention provides - a method of speeding up - flashing the efficiency of the color, the reading body comprises a plurality of memory clusters, each __ memory cluster contains at least _blocks (this wash), the method includes the following steps: (a) generating a plurality a comparison table, each of which corresponds to the comparison table The hidden cluster 'is used to record the relationship between the physical block address of the flash memory and the I block address of the _ age-only access, and (b) provides the _ first-in first-out (the aging time & fine (10), a fif〇) register to record the plurality of comparison tables; and (6) in accordance with the plurality of comparison tables stored in the order of the first-in-first-out temporary storage 1379197 'the more pre-emptive money in the first Qiuzaki deposit and the money The memory cluster corresponding to the table. According to the above embodiment of the present invention, the flash memory system, NAND_memory, in order to make the above aspect of the present invention more pure, the following preferred embodiments are combined with The drawings are described in detail below. [Embodiment] FIG. 4 is a functional block diagram of the flash memory management system 10 of the first embodiment of the present invention. Flash memory management The system 10 includes a judging unit 12, a counting unit 130, a converting unit 140, and a flash, followed by 16. In the present embodiment, the flash memory can be a NAND [a remembrance, each of which is internal One block (intestines (8) consists of one ear (4), each page is 2K bytes (bytes) The conversion unit 140 includes a plurality of logical and physical address comparison tables. For convenience of description, the conversion unit in the embodiment includes eight comparisons 纟LUT1_LUT8, and the health visual design of the comparison table needs to be adjusted. Each of the comparison tables LUT1-LUT8 corresponds to one of the memory blocks of the flash memory 16 用来, respectively, which is used to record the physical block address of the corresponding memory cluster (towing (5) m〇ck Address > Block Address . The conversion relationship of lba). For example, the comparison table LUT1 corresponds to the memory cluster 2〇3, and the comparison table LUT3 corresponds to the memory cluster 2, and the comparison table 6 corresponds to the memory cluster 2〇2. The data capacity of the conversion unit (10) can be adjusted according to the number of comparison tables LUT or the size of each memory cluster corresponding to the county LUT. The counting unit 13Q includes a plurality of (four) muNTs, and each of the counters C0UNT1-C0UNT8 should be assigned to it - the pairing LUT1_LUT8 is used to calculate the access of the rhyme table of the setting __. _ Yuan 12G is the software code of the age of memory. Referring to Figure 4 and Figure 5 together, Figure 5 is a flow chart of the operation method of the flash memory management system of Figure 4. s 丨 丨 下 — — — — — — — 指令 指令 指令 指令 指令 指令 指令 指令 指令 指令 指令 指令 指令 指令 指令 指令 指令 指令 指令 指令 指令 指令 指令 指令 指令 指令 指令 指令 指令 指令 指令 指令 指令 指令 指令 指令 指令 指令 指令 指令 指令 指令 指令 指令5G4). If the forest is located, the logical block address in the instruction of the file system 150 is found to find the flash memory (10)_physical block address and access it (step 506). For example, the file system 15 wants to access the data of a certain block of the memory cluster 2〇1, and the reference table LUT3 corresponds to the block data of the age memory cluster 201, so the comparison table LUT3 notifies the file system 15 The designated block corresponds to the physical block address of the memory cluster 201 of the flash memory 16〇. At this time, the cumulative number of counters corresponding to the counter c〇〇NT3 corresponding to the table LUT3 is incremented by K step 508) to indicate that the lookup table LUT3 has been accessed once. Similarly, when the file system ISO wants to access the data of a certain block of the memory cluster 202, the lookup table LUT6 notifies the file system 15 that the specified block corresponds to the physical region of the memory cluster 202 of the flash memory 16〇. Block address. At this time, the cumulative number of counters C 〇 UNT 6 corresponding to the table LUT 6 is incremented by one to indicate that the lookup table LUT 6 has been accessed once (step 508). If the file system 150 wants to access the data of a certain block of the memory cluster 204, but the memory cluster 204 has not been previously accessed, there is no comparison table in the conversion unit 140 to record its physical block address. Relationship to logical block addresses. Therefore, the judging unit 120 judges the number of times calculated by the plurality of counters COUNin_COUNT8 in a predetermined period of time (step 510), and determines which of the lookup tables and the corresponding memory clusters to update. For example, 12 1379197, if the determining unit 120 detects that the counter value of the counter C0UNT1 is the smallest (step 51〇), indicating that the memory cluster 203 is accessed the least number of times during the preset time period, the judging unit 12 The update lookup table LUT1' is controlled such that the lookup table LUT1 re-records the relationship between the physical block address of the memory cluster 2〇4 and the logical block address (step 512). Thereafter, all of the counters COUNT1-COUNT8 in the conversion unit mo are all zeroed (step 514). Please refer to Fig. 6', which is a functional block diagram of the flash memory management system 20 of the second embodiment of the present invention. The management system 20 includes a judging unit 220, a first in first out register 230, a conversion unit 140, and a flash memory 160. In this embodiment, the flash memory 16A can be a NAND flash memory, and each block in the internal block is composed of 64 pages, each page being a 2K byte. (bytes) or 512 bits (bits) size. The conversion unit 240 includes a plurality of logical-entity address comparison tables LUT. For convenience of description, the conversion unit in the embodiment includes eight comparison tables LUT1-LUT8'. Actually, the number of comparison tables needs to be adjusted. Each of the lookup tables LUT1-LUT8 corresponds to one of the memory partitions of the flash memory 160, which is used to record the physical block address (physicai Bi〇ck Address ' PBA) and the file system of the corresponding memory cluster. The conversion relationship of the logical block address (LBA). For example, the comparison table LUT1 corresponds to the memory cluster 203, and the comparison table LUT3 corresponds to the memory cluster 2 (n, the comparison table LUT6 corresponds to the memory cluster 2〇2. The data capacity of the conversion unit 240 can be regarded as the number of the comparison table or the comparison The size of each memory cluster corresponding to the table LUT is adjusted. The determining unit 220 is a software code stored in the memory. Please refer to FIG. 6 and FIG. 7 together, and FIG. 7 is a flash of FIG. A flowchart of the operation method of the memory management system 20. When the file system 150 issues an instruction to access the memory cluster of the flash memory 160 13 1379197 (step 702), the determining unit 220 first determines the memory cluster to be accessed. Is there a corresponding lookup table LUT (step 704). If so, the plurality of lookup tables will find the physical block address in the flash memory 16〇 according to the logical block address in the file system uo's instruction. (Step 5〇6). For example, the file system 150 wants to access the data of a certain block of the memory cluster 201, because the comparison table LUT3 corresponds to the storage memory cluster 2〇1 secret block data, so the comparison table LUT3 will notify the slot Case system lS〇 The fixed block corresponds to the physical block address of the memory cluster 2〇1 of the flash memory (10), and is accessed (step 7〇6). At this time, the comparison table luT3 is stored in the first in first out register 23 〇 (Step 7〇8) Similarly, when the file system 15 wants to access the lining of a certain block of the memory cluster 2〇2, the lining table LUT6 will notify the age system 15G that the designated block corresponds to the flash. The physical block address of the memory cluster of the It 160 is stored. At this time, the lookup table LUT6 is stored in the FIFO register. 230 (step 708). If then, the file system 15 is again One person accesses the data of a certain block of the cluster 2 〇1, and at this time, the order of the lookup table LUT3 stored in the FIFO register 230 is later than the comparison table LUT6 (steps 7〇8). The slot system ISO wants to access the data of a certain block of the memory cluster 2〇4, but the memory cluster 2〇4 has no chance of being accessed, so there is no comparison table in the conversion unit (10) to record the entity. The relationship between the block address and the logical block address. Therefore, the judgment unit no finds that it will be stored first in the FIFO register. According to the table and the memory cluster corresponding to the comparison table (step, and more. Lejia, Hongjia example, the first in and out of the register 230 is stored in the comparison table LUT6, and the first in first out temporary storage The device 23〇 is already full, so the judging unit 22〇 controls the update comparison table, so that the comparison table loses 0 and records the relationship between the physical block address of the cluster 204 and the logical block address. 612) 14 1379197 There is only a single look-up table for the technology, although a single look-up table may correspond to a larger but address-only single-read cluster of '', but the hoof system (10) wants to save the (10) block and * Single memory bundle (4) 'Shanzheng new single-------------------------- However, in this embodiment, the single comparison table is divided into _, 崎, and each 赖 别 corresponds to an independent keeper in the flash memory 160, accompanied by f 隹 己 ° hidden cluster. That is to say, 'If you encounter a previously un-accessed----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- The silk record of the youngest woman's _ or _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Although the preferred embodiment of the present invention has been disclosed above, it is not intended to limit the present invention to the technical age of the mt, the female, the hair, the spirit, and the fineness, when various changes can be made. This day's protection _ _ _ hat special: the standard shall prevail.卜 [Simple description of the diagram] The first figure is the previous technique NAND, _ note, followed by a circle. Figure 2 is an example of storing logical and physical addresses. Figure 3 is a schematic representation of prior art wire-to-memory access. Fig. 4 is a functional block diagram of the side memory management button of the _th complement of the present invention. Figure 5 is a flow chart of the operation method of the management system in Figure 4. Figure 6 is a flow chart of the operation method of the flash memory management system of the second embodiment of the second embodiment of the function memory module 15 1379197. [Main component symbol description] 10 ' 20 Flash memory management system 12 Block 14 Page 16 Comparison table 22 First storage space 24 Second storage space 100, 160 Flash memory 141 Data storage area 142 Spare area 120, 220 Judging unit 130 counting unit 140 converting unit 150 file system 201-204 memory cluster 230 first in first out register COUNT 1-COUNT8 counter LUT1-LUT8 comparison table 16