200949536 九、發明說明： . 【發明所屬之技術領域】 本發明係有關-種NAND快閃記_之管理系統以及方法更具體來 說’係翻帛久未棚者移ϋ aeastReeentlyUsed， 是先進先_池—伽，阳0)策略的方式加速掃描對照表的時間。 【先前技術】 © ‘I·夬閃記憶體(Flash Memory)為-非揮發性(n〇n_v〇latile)之記憶體在電 源關閉時仍可保存先前寫入的資料。與其他儲存媒體(如硬碟、軟碟或磁帶 等)比較’快閃記憶體有體積小、重量輕、防震動、存取時無機械動作延遲 與低耗電等特性。由於快閃記憶體的這些特性，因此近年來消費性電子產 品、嵌入式系統或可攜式電腦等資料儲存媒體皆大量採用。 快閃記_主要可分_ : NOR型_記麵與NAND型快閃記憶 體NOR型快閃記憶體的優點為低電壓、存取快且穩定性冑，因此已被大 ®量應用於可攜式電子裝置及電子通訊裝置，諸如個人電腦的職μ200949536 IX. Description of the invention: [Technical field of the invention] The present invention relates to a management system and method for a NAND flash flash _ more specifically, 'the 帛 帛 帛 ϋ a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a Gamma, yang 0) The way the strategy speeds up the scanning of the look-up table. [Prior Art] © ‘I·Flash Memory is a non-volatile (n〇n_v〇latile) memory that can save previously written data when the power is turned off. Compared with other storage media (such as hard disk, floppy disk or tape), the flash memory has the characteristics of small size, light weight, anti-vibration, no mechanical delay and low power consumption during access. Due to these characteristics of flash memory, in recent years, data storage media such as consumer electronic products, embedded systems or portable computers have been widely used. Flash _ Mainly _ : NOR type _ face and NAND type flash memory NOR type flash memory has the advantages of low voltage, fast access and stable stability, so it has been used in portable Electronic devices and electronic communication devices, such as personal computers
Computer > Ρ〇 > , (Personal Digital Assistance ^ PDA) 以及轉頻器(Set-topBox，STB)等。NAND型快閃記麵是專門為資料儲存 用途而D又汁之快閃記憶體，通常應用於儲存並保存大量的資料的儲存媒 介，如可攜式記憶卡(SDMemoryCard，c〇mpactFlashCard，Mem〇iy Stkk 等等）。當快閃記憶體在執行寫入(Write)、抹除(Erase)及讀取(Read)運作時， 可透過内’冑雜合(CGUPling)有舰控繼浮卿1⑽ting Gate)上電荷 的移動’進而使得該漂浮閘可根據該電荷的軸而決定下層電晶體的閥值 5 200949536 電壓。換言之’當負電子注入該漂浮閘時，該漂浮閘的儲存狀態便會從1 - 變成0;而當負電子從該漂浮閘移走後，該漂浮閘的儲存狀態便會從0變成 1 ° 請參閱第1圖，第1圖係先前技術之NAND快閃記憶體之示意圖。NAND 快閃記憶體100内部由複數個區塊(bi〇ck)12所組成。每一區塊12包含複數個 頁(page)14，每一頁14則可分為資料儲存區141以及備用區(spare area)142， 資料儲存區Ml的資料容量可為犯個位元組，用來儲存使用資料，備用區 © M2用來儲存錯誤修正碼(Error Correction Code, ECC)。與NOR型快閃記憶 體不同，NAND型㈣記髓之讀取與寫人單位料―個ff料讀寫的 動作必須先向晶片發出讀取或寫入指令後才可進行。 然而，快閃記憶體本身無法原地直接更改資料(update_in place)，也就是 說，若要對已寫過資料位置再次寫入資料時，必須先執行抹除的動作。而 且NAND侧記舰寫人單位為頁，而齡單位輕塊。所以當向晶片發出 寫入請求時，必須先抹除一整個區塊12，才能把資料寫入至該區塊Ο的頁 _ 14。而且-般來說—個區塊12抹除動作需要的時間約為—個頁μ寫入動作 時間_〜2〇倍。如果當一個抹除的單位大於寫入的單位這表示若要執 行區塊抹義作，必須先將欲齡區射的有效移至其它區塊後才可 進行。 8由於上述_記憶體的特性，因此能有效管理_記㈣的管理系統 是非常需要的。傳統上，目前快閃記憶體作讀存媒體所設計的槽案系統 架構有如FFS、脑與聊s等檔案系統。這些槽案系田統較有 6 200949536 效率，但只能使用在管理以快閃記憶體建構之儲存媒體上。另一種作法則 •是採用一 FTL (Flash Translation Layer)中間層，將快閃記憶體模擬為區塊裝 置’如硬碟機一般。因此在FTL的上層就可使用一般的檔案系統，如FAT32 或EXT3等等’對下層發出區段(sect〇r)讀寫請求，經由FTL來存取快閃記 憶體内容。對NAND Flash做資料存取前，FTL包含一個邏輯-實體位址對 照表LUT ’用以紀錄邏輯區塊位址〈Logical Block Address，LBA〉轉換成 實體區塊位址〈Physical Block Address，PBA〉的關係，邏輯區塊位址是棺 ® 案系統要求存取資料的區塊位址，實體區塊位址則是邏輯區塊位址所對應 到的實際在快閃記憶體中的區塊位址。 請參閱第2圖，第2圖係儲存邏輯位址與實體位址之一範例。假設每一 區塊有η頁的資料。當上層檔案系統要求讀取邏輯位址1的資料，透過邏 輯-實體位址對照表I6得知邏輯位址1對應之實體位址為(區塊0-頁1)，所 以系統會取得實體位址(區塊0-頁1)内的資料並傳回。若上層檔案系統要求 更新邏輯位址3的内容，由於不允許直接再次寫入，所以系統之動作為將 實體位址(區塊0-頁0)至(區塊0-頁2)寫入(區塊2-頁0)至(區塊2-頁2)，再 將更新資料寫入至(區塊2-頁3)，並將實體位址(區塊0-頁4)到(區塊0-頁η-1) 寫入(區塊2-頁4)到(區塊2-頁η-1)，然後將實體位址(區塊0)的資料標示為 無效，最後將位址對照表16中邏輯位址3之對應資訊由(Β0-Ρ3)改為 (Β2-Ρ3)，如此下一次要存取邏輯位址3的資料，就會對應至實體位址(區塊 2-頁3)存取資料。 請參閱第3圖，第3圖係先前技術之對照表16與NAND快閃記憶體存 7 200949536 取之示意圖。晶片内可供程式使用的記憶體有限，不可能一次將全㈣細 快閃記憶體所有的區塊位址都記錄起來。也就是說，對照表^必須隨著樓 案系統資料存取的要求，去動態的建立或更新對照表16的内容。對昭表μ 會預留-第-記‘_ 22來常駐記錄NAND_記憶體q的區塊位 址，原因是因為NAND快閃記憶體_ζ〇_通常是用來存放稽案系統 FAT的地方，而播案系統為了存取樓案會經常需要存取表。所以為了 提升對照表16的效能，會先把存放财的區塊位址常駐記錄在對照表π 的第-記憶空間22内’這樣就不用經常為了 FAT而重建對照表16。若是 檔案系統所要求存取資料的位址已被目前的對照表16記錄於第二記憶空間 24亦即目㈣對照表LUT不需要重建。如果下―次職系統使用到目前 對照表LUT所沒有記錄到的NAND快閃記憶想位址，則構案系统會以樓案 系統所要求存取資料的區塊位址為中心點，向上與向下合計約1〇〇〇個區塊 範圍掃描這些區塊的冗餘(Redundant)區域來建立對照表lut，亦即將新 ❹的區塊位址的相關資訊紀錄於對絲16的第二記憶空間24。 由於建立〈更新〉對照表16時所需的資訊，一般來說是存放在ΝΑΝ〇 决閃德體之冗餘區域裡’所以執行建立〈更新〉對照表16的動作，就必 /頁把範圍内的所有區塊的冗舰域都雜讀丨—次。這働作是必需但卻 疋相备沒有效率。因此’如果能改進掃描讀取對照表16的時間，則快閃記 憶體系統的存取效率將可大大提升。 【發明内容】 8 200949536 有鑑於此，本發明係提供-種NAND快閃記憶體之管理系統以及方 法，利用久細者㈣〈Lea遷entlyUsed，LRu〉㈣是先進先出 ㈣1心遍’鹏)策略的方式加速掃描對照表的時間，以改善先前技 術的問題。 φComputer > Ρ〇 > , (Personal Digital Assistance ^ PDA) and Transponder (Set-topBox, STB). NAND flash memory is a flash memory for data storage purposes. It is usually used as a storage medium for storing and storing large amounts of data, such as portable memory cards (SDMemoryCard, c〇mpactFlashCard, Mem〇iy). Stkk, etc.). When the flash memory performs Write, Erase, and Read operations, it can move through the charge on the CGUPling. 'In turn, the floating gate can determine the threshold of the lower transistor 5 200949536 according to the axis of the charge. In other words, when the negative electron is injected into the floating gate, the storage state of the floating gate will change from 1 to 0; and when the negative electron is removed from the floating gate, the storage state of the floating gate will change from 0 to 1 °. Please refer to FIG. 1 , which is a schematic diagram of a prior art NAND flash memory. The NAND flash memory 100 is internally composed of a plurality of blocks (bi〇ck) 12. Each block 12 includes a plurality of pages 14, each of which can be divided into a data storage area 141 and a spare area 142. The data capacity of the data storage area M1 can be a single byte. Used to store usage data, spare area © M2 is used to store Error Correction Code (ECC). Unlike the NOR type flash memory, the NAND type (4) reading and writing unit material------------------------------------------------------------------------------------- However, the flash memory itself cannot directly change the data (update_in place) in place, that is, if the data is to be written again to the already written data position, the erase operation must be performed first. Moreover, the NAND side record writer unit is a page, and the age unit is light. Therefore, when a write request is issued to the wafer, an entire block 12 must be erased before the data can be written to the page _ 14 of the block. Moreover, in general, the time required for the block 12 erase operation is approximately - one page μ write action time _~2 times. If an erased unit is larger than the written unit, it means that if the block erase is to be executed, the effective range of the desired area must be moved to other blocks before it can be performed. 8 Due to the characteristics of the above-mentioned memory, it is highly desirable to be able to effectively manage the management system of (4). Traditionally, the current slot memory system designed by flash memory for reading media has such file systems as FFS, Brain and Chat. These slots are more efficient than the 200949536, but can only be used to manage storage media built with flash memory. Another method is to use an FTL (Flash Translation Layer) middle layer to simulate flash memory as a block device, such as a hard disk drive. Therefore, in the upper layer of the FTL, a general file system such as FAT32 or EXT3 or the like can be used to issue a read/write request to the lower layer (sect〇r), and access the flash memory content via the FTL. Before data access to NAND Flash, FTL contains a logical-physical address comparison table LUT 'used to record logical block address <Logical Block Address, LBA> converted to physical block address (Physical Block Address, PBA) Relationship, the logical block address is the block address that the system requires to access the data, and the physical block address is the block position actually corresponding to the logical block address in the flash memory. site. See Figure 2, which is an example of storing logical and physical addresses. Suppose each block has n pages of data. When the upper file system requires reading the data of the logical address 1, the physical address of the logical address 1 is determined by the logical-physical address comparison table I6 (block 0-page 1), so the system obtains the physical bit. The information in the address (block 0-page 1) is returned. If the upper file system requires updating the contents of logical address 3, since the direct write is not allowed, the action of the system is to write the physical address (block 0-page 0) to (block 0-page 2) ( Block 2 - page 0) to (block 2 - page 2), then write the update data to (block 2 - page 3), and the physical address (block 0 - page 4) to (block 0-page η-1) Write (block 2 - page 4) to (block 2 - page η-1), then mark the data of the physical address (block 0) as invalid, and finally compare the address The corresponding information of logical address 3 in Table 16 is changed from (Β0-Ρ3) to (Β2-Ρ3), so the next time you want to access the data of logical address 3, it will correspond to the physical address (block 2-page 3) Access data. Please refer to FIG. 3, which is a schematic diagram of the prior art comparison table 16 and NAND flash memory storage. The memory available for the program in the chip is limited, and it is impossible to record all the block addresses of the full (four) fine flash memory at one time. That is to say, the comparison table ^ must dynamically establish or update the contents of the comparison table 16 along with the requirements of the material access of the project system. For the table, μ will reserve - the first record '_ 22 to record the block address of the NAND_memory q, because the NAND flash memory _ζ〇_ is usually used to store the FAT of the audit system. Places, and the broadcast system often needs access to the table in order to access the building. Therefore, in order to improve the performance of the comparison table 16, the block address of the stored money is first recorded in the first memory space 22 of the comparison table π. Thus, the comparison table 16 is not often reconstructed for FAT. If the address requested by the file system for accessing the data has been recorded in the second memory space 24 by the current comparison table 16, the target (4) comparison table LUT does not need to be reconstructed. If the next-secondary system uses the NAND flash memory address that is not recorded by the current LUT, the structure system will use the block address of the data required by the building system as the center point. A total of about 1 block range is scanned down to scan the Redundant area of these blocks to create a comparison table lut, and the information about the block address of the new block is recorded in the second memory of the wire 16 Space 24. Since the information required to establish the "update" table 16 is generally stored in the redundant area of the flashing body, the action of establishing the "update" table 16 is executed, and the range is required. The redundant domain of all the blocks in the block is miscellaneous. This is necessary but it is not efficient. Therefore, if the time for scanning the read comparison table 16 can be improved, the access efficiency of the flash memory system can be greatly improved. SUMMARY OF THE INVENTION 8 200949536 In view of this, the present invention provides a management system and method for a NAND flash memory, using a long-term (4) <Lea moveentlyUsed, LRu> (four) is a first-in first-out (four) 1 heart pass 'peng) The strategy approach speeds up the scanning of the look-up table to improve the problems of the prior art. Φ
本發明之-目的係提供—種快閃記憶體管理系統，其包含快閃計憶 體、複數個對照表、複數個計數器以及判斷單元。該快閃記憶體包含複數 個記憶叢集’每-記憶叢集包含至少—區塊。每—龍表 記憶叢集，触轉換成—_統存取 之邏輯區塊位址的關係。每一計數器對應於其令之—對照表用來計算一 數器所計算之存取次數’更新該複數個對照表以及所對應之該複數個纪憶 叢集。 ^ 依據本發明上述之實施例，該觸單元侧來控制更新存取次數最少 的計數器所誠的_表以及該龍表麟應之織叢集。驗閃記憶體 係一 NAND快閃記憶體。 依據本發明之h㈣倾供—種,_記憶理魏，其包含其包 含快閃計憶體、複數個對照表、暫存器以及判斷單元。該快閃記憶體包: 複數個記憶叢集’每-記憶叢集包含至少—區塊。每—對照表對應於其中 之-記憶錢，絲記__記倾之實艇齡轉換成-權案系統 存取之邏龍塊位址關係。該暫存器絲記錄該複數倾照表;該判斷 單元用來«賴數倾縣__轉_轉，錢絲數個對昭 9 200949536 ^ 表以及所對應之該複數個記憶叢集。 . 絲本發明上叙實細，該暫存雜-先進先In First Out , FIFO)暫存_!料元制紐做新最紐贿於魏料出暫存器 對照表以及崎絲騎應之記織集。職閃記㈣係—似如快閃記 憶體。 本發明之又-目_提供—種純記紐存減率之方法，該 快閃記憶體包含複數個記憶叢集，每―記憶叢集包含至少—區塊(祕)，該 ®方法包含下列步驟：（a)產生複數個對照表，每—對絲對應於其中之一記 憶叢集’絲記錄該快閃記鍾之實體區塊位址轉換成—稽㈣統存取之 邏輯區塊位址的關係；（b)計算一預設時間内每一對照表的存取次數；以及 ⑷依據縣-f值麵計算啸較數’更聽複油雜細及所對應 之該複數個記憶叢集。 依據本發明上叙實施例，步驟⑷包含域存取次數最少的計數器所 對應的對照表以及該對照表所對應之記憶叢集。該快閃記憶體係一 ναν〇 ® 快閃記憶體。 本發明之再一目的係提供一種加快一快閃記憶體存取效率之方法，該 快閃記憶體包含複數個記憶叢集，每一記憶叢集包含至少一區塊(Ik)，該 方法包含下列步驟：⑷產生複數個對照表，每一對照表對應於其中之一記 憶叢集，用來記錄該快閃記憶體之實體區塊位址轉換成一槽案系統存取之 邏輯區塊位址的關係；（b)提供一先進先出(FirstInFirst〇ut FiF〇)暫存器以 記錄該複數瓣Μ ;从(e)輯該概_絲贿賊辆先出暫存 200949536 ' ㈣料，摘最先浦存練歧先㈣存im«以及騎照表所對 • 應之記憶叢集。 依據本發明上述之實劇，該快敝憶體係—NAND _記憶體。 為讓本發明之上述内容能更明顯易懂，下文特舉較佳實施例，並配合所 附圖式’作詳細說明如下。 【實施方式】 絲Μ 4 K，第4圖係本發明之第—實關之快閃記鐘管理系統 © 10之功能方塊圖。快閃記憶體管理系、统10包含判斷單元⑼、計數單元 130、轉換單元Μ〇以及快閃記舰16〇。在本實施例中，快閃記憶體16〇 可為NAND快閃§己憶體，其内部的每一個區塊(B1〇ck)均由64個頁办职） 所組成，每-個頁為2K位元組(b㈣或是犯位元㈣大小。轉換單元 140包含複數個邏輯-實體位址對照表LUT，為便於說明，本實施例中轉換 單70包含8個對照表LUT1_LUT8，實際上對照表的健可視設計需要調 整。每-對照表LUT1-LUT8分別對應於快閃記憶體16〇其中之一記憶叢集 β (partition) ’时紀錄該對應記憶叢集的實體區塊位址(ph㈣d B1〇ck A—ss，PBA)和檔案系統所判讀的邏輯區塊位址 lba)的轉換關係。舉例來說，對照表LUT1對應於記憶叢集2〇3，對照表 LUT3對應於記憶叢集2(u、對照表敗6對應於記憶叢集2〇2。轉換單元 H0的貝料谷量可麟照表LUT的個數或是對照表lut的所對應的每一記 憶叢集的大小調整之。計數單元⑽包含複數個計數器c〇unt，每一計數 器C〇unT1-C〇unT8分卿應於其中之—對照表luti_lut8，用來計算 11 200949536 一預設時間内對應之對照表的存取次數。判斷單元120係一儲存於記憶體 . 之軟體程式碼。 清一同參閱第4圖以及第5圖，第5圖係第4圖之快閃記憶體管理系 統10之運作方法流程圖。當棺案系統15〇下達一指令欲存取快閃記憶體160 之記憶叢集時(步驟502)，判斷單元120會先判斷該欲存取的記憶叢集是否 有對應的對照表LUT(步驟504)。如果有，則複數個對照表會依據檔案系統 150的指令内的邏輯區塊位址’找出快閃記憶體160内的實體區塊位址，並 ® 存取之(步驟506)。舉例來說，檔案系統150欲存取記憶叢集201的某一區 塊的資料’因為對照表LUT3對應儲存記憶叢集201的區塊資料，所以對 照表LUT3會通知檔案系統150該指定區塊對應於快閃記憶體16〇的記憶 叢集201的實體區塊位址。此時，對照表LUT3對應的計數器c〇UNT3計 數值的累計次數會加K步驟508)，以表示對照表LUT3已被存取一次。同 樣地’當檔案系統150欲存取記憶叢集202的某一區塊的資料，則對照表 LUT6會通知檔案系統150該指定區塊對應於快閃記憶體160的記憶叢集 202的實體區塊位址。此時，對照表LUT6對應的計數器COUNT6計數值 的累計次數會加1，以表示對照表LUT6已被存取一次(步驟508)。 如果檔案系統150欲存取記憶叢集204的某一區塊的資料’但是記憶 叢集204因為先前並沒有被存取的機會，所以轉換單元14〇内也沒有任何 對照表有紀錄其實體區塊位址與邏輯區塊位址的關係。因此判斷單元120 會判斷依據複數個計數器COUNT1-COUNT8在一預設時段内所計算之次 數(步驟510)，決定要更新哪一個對照表以及所對應的記憶叢集。舉例來說， 12 200949536 若判斷單元120偵測到計數器COUNT1的計數值最小(步驟51〇)，表示在該 . 預設時段内，記憶叢集203被存取的次數最少，因此該判斷單元12〇就會 控制更新對照表LUT1，使得對照表LUT1重新紀錄記憶叢集2〇4的實體區 塊位址與邏輯區塊位址的對照關係(步驟512)。之後，就會將轉換單元14〇 内的所有計數器COUNT1-COUNT8全部歸零(步驟514)。 請參閱第6圖’第6圖係本發明之第二實施例之快閃記憶體管理系統 20之功能方塊圖。管理系統20包含判斷單元22〇、先進先出暫存器23〇、 ©轉換單元140以及快閃記憶體16〇。在本實施例中，快閃記憶體⑽可為一 NAND快閃記憶體，其内部的每一個區塊(B1〇ck)均由M個頁办㈣所組 成，每一個頁為2K位元組(bytes)或是512位元(bits)大小。轉換單元24〇 包含複數個邏輯-實體位址對照表LUT，為便於說明，本實施例中轉換單元 包含8個對照表LUT1-LUT8，實際上對照表的健可視設計需要調整。每 -對照表LUT1-LUT8分別對應於快閃記憶體10〇其中之一記憶叢集 (partition)，用來紀錄該對應記愧叢集的實體區塊位址㈣_恤也 Address ’ PBA)和;ff案系統所判讀的邏輯區塊位址B1〇ck歲咖， LBA)的轉換關係。舉例來說’對照表luti對應於記憶叢集2⑹對照表 LUT3對應於記憶叢集2〇卜對照表lut0對應於記憶叢集2〇2。轉換單元 24〇的:貝料谷里可視對照表LUT的個數或是對照表lut的所對應的每一記 隱叢集的大小調整之。判斷單元22()係_儲存於記憶體之軟體程式碼。 '^同參閱第6 ®以及第7圖’第7關第6圖之快閃記憶體管理系 ..充2〇之運作方法流程圖。當檔案系统⑼下達一指令欲存取快閃記憶體_ 13 200949536 ’ 之3己憶叢集時(步驟702) ’判斷單元22〇會先判斷該欲存取的記憶叢集是否 . 有對應的對照表LUT(步驟7〇4)。如果有，則複數個對照表會依據檔案系統 15〇的指令内的邏輯區塊位址，找出快閃記憶體160内的實體區塊位址(步 驟506)。舉例來說，擋案系統15〇欲存取記憶叢集2〇1的某一區塊的資料， 因為對照表LUT3對應儲存記憶叢集2〇1的區塊資料，所以對照表luT3 會通知檔案系統150該指定區塊對應於快閃記憶體16〇的記憶叢集2〇1的 實體區塊位址，並存取之(步驟706)。此時，對照表LUT3會儲存於先進先 ❹出暫存器230(步驟)。同樣地，當樓案系、统15〇欲存取記憶叢集2〇2的 某一區塊的資料，則對照表LUT6會通知檔案系統15〇該指定區塊對應於 快閃s己憶體160的記憶叢集202的實體區塊位址。此時，對照表LUT6會 儲存於先進先出暫存器230(步驟7〇8)。如果接下來，檔案系統15〇又在一 -人存取s己憶叢集201的某一區塊的資料，此時，對照表LUT3儲存於先進 先出暫存器230的次序就會晚於對照表LUT6(步驟7〇8)。 如果檔案系統150欲存取記憶叢集204的某一區塊的資料，但是記憶 叢集204因為先前並沒有被存取的機會，所以轉換單元14〇内也沒有任何 對照表有紀錄其實體區塊位址與邏輯區塊位址的關係。因此判斷單元22〇 找出會最先被儲存於先進先出暫存器230的對照表以及該對照表所對應之 記憶叢集(步驟710)並更新之。舉例來說，承上所述之例，若先進先出暫存 器230最先被儲存的是對照表LUT6，且先進先出暫存器23〇已被存滿因 此該判斷單S 22〇就會控制更新對照表LUT6，使得對照表LUT6重新紀錄 5己憶叢集204的實體區塊位址與邏輯區塊位址的對照關係(步驟612)〇 14 200949536 她於先_吻—崎，W—賴她對應於較大但 連月的早z隐叢集，一但檔案系統⑽欲存取的區塊並不在該單一 記憶叢集内，則掃晦更新軍—對找表的時間會比較長。但是本實施例將單 -對照表分成複數做小的触表，每—對照表⑴侃⑽都分別對應至 快閃5己憶體160内的一獨立却培f隹 幻獨立德叢集。也就是說，如果遇到先前並未存取 過記憶叢鱗，因為每-對絲較小，所崎描更贿應該位存取過記憶 Φ 叢集的對照表的時間較短，再搭配計數器紀錄最少被存取的對照表的機制 或是暫存於先進先出暫存器的機制，本實施例更新對照表的時間將可大幅 減少，故可加快存取快閃記憶體的效率。 练。以上所述，雖然本發明已較佳實施例揭露如上，然其並非用以限 定本發明，任何熟習此項技藝者，在不脫離本發明之精神和範圍内，當可 作各種更動與潤飾，因此本發明德護範㈣視後社”專概圍所界 定者為準。 【圖式簡單說明】 第1圖係先前技術之NAND快閃記憶體之示意圖。 第2圖係儲存邏輯位址與實體位址之一範例。 第3圖係先前技術之對照表與NAND快閃記憶體存取之示意圖。 第4圖係本發明之第一實施例之快閃記憶體管理系統之功能方塊圖。 第5圖係第4圖之快閃記憶體管理系統之運作方法流程圖。 第6圖係本發明之第二實施例之快閃記憶體管理系統之功能方塊圖。 15 200949536 第7圖係第6圖之快閃記憶體管理系統之運作方法流程圖。 【主要元件符號說明】 10、20 快閃記憶體管理系統 12 區塊 14 頁 16 對照表 22 第一儲存空間 24 第二儲存空間 100、160快閃記憶體 141 資料儲存區 142 備用區 120、220 判斷單元 130 計數單元 140 轉換單元 150 檔案系統 201-204 記憶叢集 230 先進先出暫存器 COUNT 1-COUNT8 計數器 LUT1-LUT8 對照表 16SUMMARY OF THE INVENTION The object of the present invention is to provide a flash memory management system comprising a flash memory, a plurality of look-up tables, a plurality of counters, and a determining unit. The flash memory contains a plurality of memory clusters. Each memory cluster contains at least a block. Each-long-table memory cluster is transformed into the relationship of the logical block address of the -_ access. Each counter corresponds to its order - the look-up table is used to calculate the number of accesses counted by the counter' to update the plurality of look-up tables and the corresponding plurality of memory sets. According to the above embodiment of the present invention, the touch unit side controls the counter of the counter with the least number of updated access times and the woven cluster of the dragon. The flash memory is a NAND flash memory. According to the present invention, the h (four) dumping species, the memory memory, includes a flash memory, a plurality of look-up tables, a register, and a judging unit. The flash memory pack: a plurality of memory clusters 'per-memory clusters containing at least—blocks. Each-control table corresponds to the memory of the memory, and the __ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The register wire records the complex tilting table; the determining unit is used for the «Lai number dumping county __ turn_turn, the Qiansi number pair Zhao 9 200949536 ^ table and the corresponding plurality of memory clusters. The invention of the invention is described in detail, the temporary storage of the first-in-first-in-first-in, first-in, first-out, FIFO, temporary storage, and the vacancy of the vacancies. Record the collection. Job flash (4) is like a flash memory. The method of the present invention provides a method for purely storing credits, the flash memory comprising a plurality of memory clusters, each of the memory clusters comprising at least a block (secret), the method comprising the following steps: (a) generating a plurality of comparison tables, each of which corresponds to one of the memory clusters, and records the relationship between the physical block address of the flashing clock and the logical block address of the (four) system access; (b) calculating the number of accesses to each of the comparison tables within a predetermined time period; and (4) calculating the whistling number based on the county-f value surface to listen to the repetitive oil miscellaneous sum and the corresponding plurality of memory clusters. In accordance with an embodiment of the present invention, step (4) includes a lookup table corresponding to the counter with the least number of domain accesses and a memory cluster corresponding to the lookup table. The flash memory system is a ναν〇 ® flash memory. Still another object of the present invention is to provide a method for speeding up a flash memory access efficiency, the flash memory comprising a plurality of memory clusters, each memory cluster comprising at least one block (Ik), the method comprising the following steps (4) generating a plurality of comparison tables, each of the comparison tables corresponding to one of the memory clusters for recording a relationship of the physical block address of the flash memory into a logical block address of a slot system access; (b) Provide a first-in-first-out (FirstInFirst〇 Fi Fi Fi Fi Fi Fi Fi Fi Fi Fi Fi Fi Fi Fi Fi Fi Fi Fi Fi Fi Fi Custody first (four) save im « and riding the watch on the pair of memory should be. According to the above-mentioned real drama of the present invention, the fast memory system - NAND_Memory. In order to make the above description of the present invention more comprehensible, the preferred embodiments are described below, and are described in detail below with reference to the accompanying drawings. [Embodiment] Silk thread 4 K, Fig. 4 is a functional block diagram of the flash clock management system of the present invention. The flash memory management system 10 includes a judging unit (9), a counting unit 130, a converting unit Μ〇, and a flashing ship 16〇. In this embodiment, the flash memory 16〇 can be a NAND flash memory, and each of the internal blocks (B1〇ck) is composed of 64 pages, each page is The 2K byte (b (4) or the spoof (4) size. The conversion unit 140 includes a plurality of logical-entity address comparison tables LUT. For convenience of description, the conversion unit 70 in the embodiment includes 8 comparison tables LUT1_LUT8, in fact, the comparison The visual and visual design of the table needs to be adjusted. Each of the comparison tables LUT1-LUT8 corresponds to the memory block of the flash memory 16〇, and the physical block address of the corresponding memory cluster is recorded (ph(4)d B1〇 The conversion relationship between ck A-ss, PBA) and the logical block address lba) read by the file system. For example, the comparison table LUT1 corresponds to the memory cluster 2〇3, the comparison table LUT3 corresponds to the memory cluster 2 (u, the comparison table defeat 6 corresponds to the memory cluster 2〇2. The conversion unit H0 of the shell material valley can be seen The number of LUTs or the size of each memory cluster corresponding to the comparison table lut is adjusted. The counting unit (10) includes a plurality of counters c〇unt, and each counter C〇unT1-C〇unT8 is in which the The comparison table luti_lut8 is used to calculate the access times of the corresponding comparison table in a preset time of 11 200949536. The determining unit 120 is a software program code stored in the memory. See Figure 4 and Figure 5 together. 5 is a flow chart of the operation method of the flash memory management system 10 of FIG. 4. When the file system 15A issues an instruction to access the memory cluster of the flash memory 160 (step 502), the determining unit 120 First, it is determined whether the memory cluster to be accessed has a corresponding lookup table LUT (step 504). If there is, the plurality of lookup tables will find the flash memory according to the logical block address in the instruction of the file system 150. Physical block address within 160, and® For example, the file system 150 wants to access the data of a certain block of the memory cluster 201. Because the comparison table LUT3 corresponds to the block data of the storage memory cluster 201, the comparison table LUT3 notifies the file system. The designated block corresponds to the physical block address of the memory cluster 201 of the flash memory 16〇. At this time, the cumulative number of counters corresponding to the counter c〇UNT3 corresponding to the table LUT3 is added with K step 508) to indicate The comparison table LUT3 has been accessed once. Similarly, when the file system 150 wants to access the data of a certain block of the memory cluster 202, the look-up table LUT6 notifies the file system 150 that the specified block corresponds to the physical block of the memory cluster 202 of the flash memory 160. site. At this time, the cumulative number of counts of the counter COUNT6 corresponding to the table LUT6 is incremented by one to indicate that the lookup table LUT6 has been accessed once (step 508). If the file system 150 wants to access the data of a certain block of the memory cluster 204, but the memory cluster 204 has not been accessed before, there is no comparison table in the conversion unit 14 to record its physical block position. The relationship between the address and the logical block address. Therefore, the judging unit 120 judges the number of times calculated based on the plurality of counters COUNT1-COUNT8 in a predetermined period of time (step 510), and decides which of the lookup tables and the corresponding memory cluster to update. For example, 12 200949536, if the determining unit 120 detects that the count value of the counter COUNT1 is the smallest (step 51〇), it indicates that the memory cluster 203 is accessed the least number of times during the preset time period, so the determining unit 12〇 The update lookup table LUT1 is controlled such that the lookup table LUT1 re-records the relationship between the physical chunk address of the memory cluster 2〇4 and the logical chunk address (step 512). Thereafter, all of the counters COUNT1-COUNT8 in the conversion unit 14A are all zeroed (step 514). Please refer to Fig. 6', which is a functional block diagram of the flash memory management system 20 of the second embodiment of the present invention. The management system 20 includes a judging unit 22, a first in first out register 23, an EPS unit 140, and a flash memory 16A. In this embodiment, the flash memory (10) can be a NAND flash memory, and each of the internal blocks (B1〇ck) is composed of M pages (four), each page being a 2K byte. (bytes) or 512 bits (bits) size. The conversion unit 24A includes a plurality of logical-entity address comparison tables LUT. For convenience of description, the conversion unit in the embodiment includes eight comparison tables LUT1-LUT8, and the health visual design of the comparison table needs to be adjusted. Each of the comparison tables LUT1-LUT8 corresponds to one of the memory blocks of the flash memory 10, respectively, for recording the physical block address of the corresponding record cluster (4) _ shirt also Address 'PBA) and; ff The conversion relationship of the logical block address B1〇ck aged coffee, LBA) read by the case system. For example, the comparison table luti corresponds to the memory cluster 2 (6) comparison table LUT3 corresponds to the memory cluster 2, and the comparison table lut0 corresponds to the memory cluster 2〇2. The conversion unit 24〇: the number of visual comparison table LUTs in the grain valley or the size of each hidden cluster corresponding to the comparison table lut. The determining unit 22() is a software code stored in the memory. '^ See also the 6® and 7th diagrams, 7th, 6th, and 6th, the flash memory management system. When the file system (9) issues an instruction to access the flash memory _ 13 200949536 '3 recalled cluster (step 702) 'the judgment unit 22 〇 first determines whether the memory cluster to be accessed is. There is a corresponding comparison table LUT (step 7〇4). If so, the plurality of lookup tables will find the physical block address in the flash memory 160 based on the logical block address within the file system 15' (step 506). For example, the file system 15 wants to access the data of a certain block of the memory cluster 2〇1, because the comparison table LUT3 corresponds to the block data storing the memory cluster 2〇1, so the comparison table luT3 notifies the file system 150. The designated block corresponds to the physical block address of the memory cluster 2〇1 of the flash memory 16〇 and is accessed (step 706). At this time, the comparison table LUT3 is stored in the advanced first-out buffer 230 (step). Similarly, when the building system and the system 15 want to access the data of a certain block of the memory cluster 2〇2, the comparison table LUT6 notifies the file system 15 that the designated block corresponds to the flash s. The physical block address of the memory cluster 202. At this time, the lookup table LUT6 is stored in the FIFO register 230 (steps 7〇8). If, in the following, the file system 15 accesses the data of a certain block of the cluster 201 in one-person, at this time, the order of the comparison table LUT3 stored in the FIFO register 230 is later than the comparison. Table LUT6 (steps 7〇8). If the file system 150 wants to access the data of a certain block of the memory cluster 204, but the memory cluster 204 has not been previously accessed, there is no comparison table in the conversion unit 14 to record its physical block position. The relationship between the address and the logical block address. Therefore, the judging unit 22 找出 finds the lookup table which is first stored in the FIFO register 230 and the memory cluster corresponding to the lookup table (step 710) and updates it. For example, in the above example, if the FIFO register 230 is first stored in the lookup table LUT6, and the FIFO register 23 is already full, the judgment list S 22〇 The update comparison table LUT6 is controlled so that the comparison table LUT6 re-records the relationship between the physical block address and the logical block address of the 5th recall cluster 204 (step 612) 〇14 200949536 She is in the first_kiss-saki, W- She relies on a large but continuous monthly z-hidden cluster. Once the file system (10) wants to access the block is not in the single memory cluster, then the broom will update the army - it will take a long time to find the table. However, in this embodiment, the single-control table is divided into a plurality of small touch tables, and each of the comparison tables (1) 侃 (10) corresponds to an independent but 隹 独立 独立 独立 独立 德 。 。 。. That is to say, if you encounter a memory cluster scale that has not been accessed before, because each pair of filaments is small, the time that you should be able to access the memory Φ cluster is shorter, and then match the counter record. The mechanism of the least-accessed look-up table or the mechanism temporarily stored in the FIFO register, the time for updating the look-up table in this embodiment can be greatly reduced, thereby speeding up the access to the flash memory. practice. The above description of the preferred embodiments of the present invention is not intended to limit the present invention, and various modifications and refinements can be made without departing from the spirit and scope of the invention. Therefore, the invention is based on the definition of the NAND flash memory of the prior art. The second figure is the storage logic address and An example of a physical address. Fig. 3 is a schematic diagram of a prior art comparison table and NAND flash memory access. Fig. 4 is a functional block diagram of a flash memory management system of the first embodiment of the present invention. Fig. 5 is a flow chart showing the operation method of the flash memory management system of Fig. 4. Fig. 6 is a functional block diagram of the flash memory management system of the second embodiment of the present invention. 15 200949536 Fig. 7 Figure 6 Flow chart of the operation method of the flash memory management system. [Main component symbol description] 10, 20 Flash memory management system 12 Block 14 Page 16 Comparison table 22 First storage space 24 Second storage space 100, 160 fast Memory data store 141 120, 220 142 spare area determining unit 130 converts the counting unit 140 and memory unit 150 201-204 cluster file system 230 registers FIFO counter COUNT 1-COUNT8 table LUT1-LUT8 16