、發明說明： 【發明所屬之技術領域】 本發明有關一種閘控橋式整流器，特別是一種具浪湧電流限制器 之閘控橋式整流器，其可限制浪湧電流且提高整流效率。 【先前技術】 習知的二極體橋式整流器（diode bridge rectifiers)使用四整流二 極體（rectification diodes)將交流輸入電壓整流成直流輸出電壓；習 知的浪湧電流限制器（inrush current limiters )常使用一熱敏電阻 (thermistor)以限制浪湧電流。儘管簡單的結構與便宜的價格，整流 二極體之順向電壓降（forward voltage drop )使二極體橋式整流器在大 電流應用中遭受高導通損失（conduction loss);熱敏電阻之負溫度係 數（negative temperature coefficient)使熱敏電阻在高溫下幾乎喪失浪 湧電流限制器的功能。 【發明内容】 為解決上述問題’本發明揭示如何以閘控橋式整流器 (gate-C〇mr〇Ued bridge rectifiers)，其具有較低之順向電壓降，取代二 極體橋式整流器。另外，此閘控橋式整流器亦與一浪湧電流限制器集 成，其與溫度無關，以限制浪湧電流至一安全值。 *本發明所揭示之具浪湧電流限制器之閘控橋式整流器包含—第一 交=輸入端L、一第二交流輸入端N、一第一直流輸出端B+、_第二 直流輸出端b.、-第-固定電壓源端Veei、—第m壓源端v的、 -浪消電流限制器、二正極性偵測器、二負極性偵測器、二正極性驅 動電路、二負極性驅動電路、二無本體二極體的閘控電晶體（可為但 1378632 不受限於—無本體二極體的絕緣閘雙極電晶體IGBT)與二有本體二極 • 體的閘控電晶體（可為但不受限於-N通道金氧半場效電晶體 NMOS)。 二固+ 定電麼源，其由外部電路提供，分別連接至％,與&並且 參考至B與Β·;該浪;勇電流關器具有-第-輸人u二輸入端 . 與一輸出端，其分別連接至L、Ν與;該四極性债測器具有一第一 • 輸人端與—第二輸人端’其分別連接至L與Ν ;該四極性驅動電路具 1第一輪入端、一第二輸入端與一輸出端，其分別連接至、 B/8與該_控電晶體之輸人端；該四驗電晶體具有—輸入端、一 9 第一輸出端與一第二輸出端，其分別連接至該四極性驅動電路之輸出 知L/N與B /B。該四閘控電晶體之閘極位於該輸入端；該四閉控電 晶體之通道/衣體二極體（若有）位於該第一與第二輸出端之間。 於起動階段，該二固定電壓源尚未被提供予該四極性驅動電路；該 四閘控電晶體之通道尚未被形成；浪消電流僅能流㈣㈣電流限制 器與該二有本體二極體的閘控電晶體之本體二極體且被該浪消電流限 制器限制至一安全值。於穩態操作，該二固定電壓源已被提供予該四 極性驅動電路’該四閘控電晶體之通道可被形成；該四極性偵測器伯 測交流輸入電壓之極性且以耦合（可為但不受限於光耦合、磁耦合等） 泰 信號分別控制該四極性驅動電路；該四極性驅動電路依據耦合信號之 狀癌分別驅動該四閘控電晶體以旁通該浪湧電流限制器並履行橋式整 流之功能。此具浪湧電流限制器之閘控橋式整流器，其可以離散零件 (discrete components)或積體電路 〇ntegratedcircuits)實現，不僅可 限制浪湧電流而且可提高整流效率。本發明之上述及其他特色和優 點經由下列關於較佳具體實施例與對應圖式的詳細描述將被更加 清楚地瞭解。 【實施方式】 圖1顯示依據本發明之具浪湧電流限制器之閘控橋式整流器的方 塊圖，其包含一第一交流輸入端L、一第二交流輸入端N、一第一直 6 流輸^ B+、—第二直流輸出端B.、-第-固定電顧端Vccl、-第 -固/^電觀端Vcc2、-㈣電流限制器％、—第__正極性伽器 第一正極性偵測器4〇2、一第一負極性偵測器4的一第二負 極性債測器4G4、-第—正極性驅動電路2()、—第二正極性驅系電路 26 一第負極性驅動電路24、一第二負極性驅動電路22、一第一I 極體的閘控電晶體1〇、—第二有本體二極體的閘控電晶體％、、 ΓΪ 一有本體二極體的閘控電晶體14、-第二無本體二極體的閘控電 固+定㈣源，其由外部電路提供，分別連接至Vd與L並且 :考至B+與Β·;該浪渴電流限制器5〇具有一第一輸入端、一第二輸入 端/、輸出端’其分別連接至L、N|^B+;該四極性偵測器4〇卜、 4〇3與404具有-第一輸入端與一第二輸入端，其分別連接至l與n ; ^極性驅動電路2G、22、24與％具有—第—輸人端、—第二輸入 ’、輸出4 ’其为別連接至Vcci/Vcc2、Β+/Β·與該四閉控電晶體川、 1山2、Η與16之輸入端；該四閘控電晶體1〇、12、14與16具有一輸入 端第-輸出端與-第二輸出端’其分別連接至該四極性驅動電路 2〇、22、24與26之該輸出端、L/N與BVB、該四開控電晶體1〇、12、 14與16之閉極位於該輸入端且該四閘控電晶體i〇、i2、14與16之通 道/本體二極體（若有）位於該第一與第二輸出端之間。 於起動階段，該二固定電壓源尚未被提供予該四極性驅動電路 20、22、24與26 ;該四閘控電晶體10、12、14與16之 成；^電流僅能流經該浪渴電流限制器5〇與該二有本體二極體的間 =電阳體14與16之本體二極體且被該㈣電流限制器％限制至一安 於穩態操作’該―固疋電壓源已被提供予該四極性驅動電路2〇、 2、24與26;該四閘控電晶體1〇、12、14與16之通道可被形成；該 403與404偵測交流輸人電紅極性且以麵 ^可為但不受紐絲合、磁齡等）信號分馳繼四極性驅動 電路20、26、24與22 ;該四極性驅動電路2〇、26、24與22依據麵合 k號之狀態分別驅動該四閘控電晶體10、16、14與12以旁通該浪湧 電流限制器50並履行橋式整流之功能。 該二無本體二極體的閘控電晶體10與12可為但不受限於一無 本體二極體的絕緣閘雙極電晶體（Insulated Gate Bip〇iar Transist〇r， T)其閘極、集極與射極分別充當輸入端、第一與第二輸出端；該 一有本體二極體的閘控電晶體14與16可為但不受限於一 Ν通道金 氧半場效電晶體（N Channel Metal Oxide Semiconductor Field 別feet Transistor ’ NMOS)，其閘極、及極與源極分別充當輸入端、 ，一與第二輸出端。上述具浪湧電流限制器之閘控橋式整流器以 早相（Single-Phase)整流電路說明’其亦可被推廣至兩相 (two-phase)或二相（如從响脱）整流電路。 為便於說明下文，假設正半週意指[之電位高於N之電位 基半週μ札L·之電位低於N之電位。圖2顯示依據本發明之 浪渴電流限制器50的-具體實施例的電路圖，其包含一第一二極 體D卜-第二二極體〇2與一第一限流電阻R7 (可為但不受限於一定 值電阻）。該第-二極體D1的陽極、該第二二極體D2的 =且R7的輸出端分別充當該浪湧電流限制器 第: :二第二輸入端與該輸出端，其分別連接至 J二 ==與第二二極體喻的陰一第丄 20、Γ固定電壓源尚未被提供予該四極™^ 二該第—二極體di受交流輸入電壓順 月匕/n忑弟一極體D卜該第一限 的間控電晶體16之本體二極體。#起=第二有本體二極體 二極體D2受交流輸人糖_導 ^負半^間’該第二 電壓逆偏喊止：㈣電細&軸^第=極_受交流輸入 第——極體D2 '該第一限流電 阻R7與該第一有本體二極體的閘控電晶體14之本體二極體。於正或 負半週期間，浪汤電流可被該第一限流電阻R7限制至一安全值。 依據對應祕，圖丨巾之該四極性偵卿、該四極性驅動電路與 該四閉控電晶體可被劃分為下列四個整流模組：第一正極性整流模= 囊括第正極性偵測器4〇1、第一正極性驅動電路與第一無本體二 極體的閘控電晶體1〇;第二正極性整流模組囊括第二正極性偵測器 4〇2、第二正極性驅動電路26與第二有本體二極體的閘控電晶體16 ; 第負極丨生整流模組囊括第一負極性偵測器403、第一負極性驅動電路 24與第-有本體二極體的閉控電晶體14 :第二負極性ί流模組= -負極性偵測器404、第二負極性驅動電路22與第二無本體二極體的 閘控電晶體12。為簡化下舰明，本文僅聚焦於第—正極性整流模組。 其餘二整流模組可由第一正極性整流模組類推。 圖3顯示依據本發明之第一正極性整流模組的方塊圖，其包含一 第一父流輸入端L、一第二交流輸入端Ν、一第一直流輸出端Β+、一 第一固疋電壓源端Vcc丨、一第一正極性偵測器4〇1、一第一正極性驅動 電路20與一第-無本體二極體的閘控電晶體1〇。該第一正極性偵測器 401具有一第一輸入端與一第二輸入端，其分別連接至l與N;該第一 正極性驅動電路20具有一第一輸入端、一第二輸入端與一輸出端，其 分別連接至Vccl、B+與該第一無本體二極體的閘控電晶體1〇之該輸入 端；該第一無本體二極體的閘控電晶體1〇具有一輸入端、一第一輸出 端與一第二輸出端，其分別連接至該第一正極性驅動電路20之該輸出 端、L與B+。該第一無本體二極體的閘控電晶體1〇之閘極位於該輸入 端且該第一無本體二極體的閘控電晶體丨〇之通道位於該第一與第二輸 出端之間。 於穩態操作，跨於Vccl與B+之第一固定電壓源已被提供予該第一 正極性驅動電路20 ;該第一無本體二極體的閘控電晶體1〇之通道可被 形成；該第一正極性偵測器401偵測交流輸入電壓之極性且以耦合（可 為但不受限於光箱合、磁耦合等）信號控制該第一正極性驅動電路2〇 ; 路2{)依_合信號之狀態驅動該第-無本體二極 動番開控電日日體1G。於正半週綱，搞合信號存在，·該第 一正極性驅 路2〇開啟該第-無本體二極體的閘控電晶體1〇之通道。於負半 4間，輕合信號不存在’·該第—正極性驅動電路20關閉該第一無本 萌一極體的閘控電晶體10之通道。 圖4A顯示依據本發明之第—正極性整流模组的第一具體實施 ^電路圖’其包含一第一交流輸入端L、-第二交流輸入端N、-奶直流輸出端B+、一第一固定電壓源端I、一第一正極性侧器 第一正極性驅動電路20與一第一無本體二極體閘控電晶體1〇。 复該第-無衣體二極體閘控電晶體1〇採用一絕緣閘雙極電晶體， 八具有-閘極(G)、-集極(〇與一射極⑹。絕緣閘雙極電晶體Q3之該 閘極(G)、集極(C)與射極⑹分別充當該第一無本體二極關控電晶體 2〇之該輸入端、該第一輸出端與該第二輸出端，其分別連接至該第一 正極性驅動電路1〇之該輸出端、交流輸入端L與直流輸出端B+。因絕 緣閘雙極電晶體Q3之開啟或關閉取決於閘極⑹與射極(e)m之相對電 位差，故第一固定電壓源，其由外部電路提供，必須連接至Yd並且參 考至絕緣閘雙極電晶體Q3之射極(亦即直流輸出端B+) 不論直流 輸出端B+之電位為何。 該第一正極性偵測器401包含一第二限流電阻Ri^與一光耦合器 (optocoupler)中之一光二極體（optodi〇de) mA，其中第二限流電阻 RL之輸入端與光二極體U1A之陰極分別充當該第一正極性偵測器4〇1 之該第一與第二輸入端，其分別連接至兩交流輸入端1^與]^;第二限流 電阻RL之輸出端連接至光二極體U1A之陽極。 該第一正極性偵測器401偵測交流輸入電壓之極性且以光耦合信號 控制該第一正極性驅動電路20。於正半週期間，光二極體U1A受交流 輸入電壓順偏而導通；線電流可流經光二極體U1A ;光二極體U1A受 線電流激勵而發光。於負半週期間，光二極體U1A受交流輸入電壓逆 1378632 偏而截止；線電流無法流經光二極體U1A :光 激勵而不發光》 該第-正極性驅動電路2G包含—濾波電容器α、—光齡器中之 晶體（〇pt〇transistor) U1B與一第一電阻Ri，其中光電晶體_ 丁 Ί電阻R1之輸出端分別充當該第一正極性凝動電路2〇之該 -與第二輸入端，其分別連接至VM1與直流輸出端B+;光二極體U1A 之射極連接嫌流電阻I之輸人端絲t該帛—正讎鱗電路如 ^玄輸出端；滤波電容器C1之正極與負極分別連接至Vccl與直流輸出BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a gate-controlled bridge rectifier, and more particularly to a gate-controlled bridge rectifier having a surge current limiter that limits surge current and improves rectification efficiency. [Prior Art] Conventional diode rectifiers use four rectifying diodes to rectify an AC input voltage into a DC output voltage; conventional inrush current limiters A thermistor is often used to limit the inrush current. Despite the simple structure and the inexpensive price, the forward voltage drop of the rectifier diode causes the diode bridge rectifier to suffer high conduction loss in high current applications; the negative temperature of the thermistor The negative temperature coefficient causes the thermistor to almost lose the function of the inrush current limiter at high temperatures. SUMMARY OF THE INVENTION To solve the above problems, the present invention discloses how to replace a diode bridge rectifier with a gate-C〇mr〇Ued bridge rectifiers having a lower forward voltage drop. In addition, the gated bridge rectifier is also integrated with an inrush current limiter that is temperature independent to limit the inrush current to a safe value. * The gated bridge rectifier with surge current limiter disclosed in the present invention comprises - first intersection = input terminal L, a second AC input terminal N, a first DC output terminal B+, and a second DC output Terminal b., - first fixed voltage source end Veei, - mth voltage source end v, - wave current limiting device, two positive polarity detector, two negative polarity detector, two positive polarity driving circuit, two Negative drive circuit, gateless transistor with no body diode (can be 136832 is not limited to – insulated gate bipolar transistor IGBT without body diode) and gate with two body diodes Control transistor (may be but not limited to -N channel MOS half-effect transistor NMOS). Two solid + fixed power source, which is provided by an external circuit, respectively connected to %, & and reference to B and Β·; the wave; the brave current switch has a -first-input u input. The output terminals are respectively connected to L, Ν and ; the four polarity debt detector has a first input end and a second input end respectively connected to L and Ν; the four polarity drive circuit 1 is first a wheel input end, a second input end and an output end respectively connected to the B/8 and the input end of the _ control transistor; the four electro-optic crystals have an input end, a 9 first output end and A second output terminal is respectively connected to the outputs of the four-polarity driving circuit, L/N and B/B. The gate of the four gated transistor is located at the input; the channel/body diode (if any) of the four closed control transistor is located between the first and second outputs. In the starting phase, the two fixed voltage sources have not been supplied to the four-polarity driving circuit; the channel of the four-gate transistor has not been formed; the wave-off current can only flow (4) (4) the current limiter and the two body diodes The body diode of the gated transistor is limited by the wave current limiter to a safe value. In steady state operation, the two fixed voltage sources have been supplied to the four-polarity driving circuit. The channel of the four-gate transistor can be formed; the four-polarity detector measures the polarity of the AC input voltage and is coupled ( For the sake of, but not limited to, optical coupling, magnetic coupling, etc., the Thai signal separately controls the four-polarity driving circuit; the four-polarity driving circuit drives the four-gate controlled transistor to bypass the inrush current limit according to the cancer signal of the coupled signal And perform the function of bridge rectification. The gated bridge rectifier with inrush current limiter can be implemented by discrete components or integrated circuits (sntegrated circuits), which not only limits the inrush current but also improves the rectification efficiency. The above and other features and advantages of the present invention will become more apparent from the detailed description of the preferred embodiments illustrated herein [Embodiment] FIG. 1 is a block diagram showing a gate-controlled bridge rectifier with a surge current limiter according to the present invention, comprising a first AC input terminal L, a second AC input terminal N, and a first straight 6 Streaming ^ B+, - second DC output terminal B., - first fixed power terminal Vccl, - first solid / ^ electrical terminal Vcc2, - (four) current limiter %, - __ positive galvanic A positive polarity detector 4〇2, a second negative polarity detector 4G4 of the first negative polarity detector 4, a first positive polarity driving circuit 2(), and a second positive polarity driving circuit 26 a first negative polarity driving circuit 24, a second negative polarity driving circuit 22, a first I-electrode gate-controlled transistor 1 —, a second body-connected gate-controlled transistor %, ΓΪ The gate-controlled transistor 14 of the body diode, the gate-controlled electro-solid + fixed (four) source of the second bodyless diode, which is provided by an external circuit, respectively connected to Vd and L and: to B+ and Β·; The surge current limiter 5 has a first input terminal, a second input terminal, and an output terminal 'connected to L, N|^B+ respectively; the four polarity detectors 4, 4, and 3 40 4 has a first input terminal and a second input terminal, which are respectively connected to l and n; ^ polarity drive circuits 2G, 22, 24 and % have a - first input terminal, a second input ', an output 4' It is connected to the input terminals of Vcci/Vcc2, Β+/Β· and the four closed control transistors, 1 mountain 2, Η and 16; the four gate control transistors 1〇, 12, 14 and 16 have one The input first output terminal and the second output terminal ' are respectively connected to the output terminals of the four polarity drive circuits 2 〇, 22, 24 and 26, L/N and BVB, the four open control transistors 1 〇, The closed poles of 12, 14 and 16 are located at the input and the channel/body diodes (if any) of the four gated transistors i〇, i2, 14 and 16 are located between the first and second output terminals. In the starting phase, the two fixed voltage sources have not been supplied to the four-polarity driving circuits 20, 22, 24 and 26; the four gate-controlled transistors 10, 12, 14 and 16 are formed; ^ current can only flow through the wave The thirst current limiter 5 〇 and the two body diodes are between the body diodes 14 and 16 and are limited by the (4) current limiter % to a steady state operation 'the solid voltage The source has been supplied to the four-polarity driving circuits 2〇, 2, 24 and 26; the channels of the four-gate transistor transistors 1, 12, 14 and 16 can be formed; the 403 and 404 detect the AC input power red The polarity and the surface can be but not affected by the neon, the magnetic age, etc., and the signal is divided by the four-polarity driving circuits 20, 26, 24 and 22; the four-polarity driving circuits 2, 26, 24 and 22 are in accordance with the surface The state of the k-number drives the four-gate controlled transistors 10, 16, 14 and 12, respectively, to bypass the inrush current limiter 50 and perform the function of bridge rectification. The gateless transistors 10 and 12 of the two bodyless diodes may be, but are not limited to, an insulated gate bipolar transistor (T) having no body diode. The collector and the emitter respectively serve as an input terminal, the first and second output terminals; the gated transistors 14 and 16 having the body diode may be, but are not limited to, a channel of a gold oxide half field effect transistor (N Channel Metal Oxide Semiconductor Field 别feet Transistor ' NMOS), its gate, and the pole and source respectively serve as an input, a first and a second output. The above-described gate-controlled bridge rectifier with inrush current limiter is described as a single-phase rectifier circuit, which can also be extended to a two-phase or two-phase (e.g., from a reverberation) rectifier circuit. For convenience of explanation, it is assumed that the positive half-week means that [the potential of the potential is higher than the potential of N. The potential of the half-cycle of the base is lower than the potential of N. 2 shows a circuit diagram of a specific embodiment of a surge current limiter 50 according to the present invention, comprising a first diode D-second diode 〇2 and a first current limiting resistor R7 (may be But not limited to a certain value of resistance). The anode of the first diode D1, the output of the second diode D2 and the output of R7 serve as the surge current limiter: respectively: the second input terminal and the output terminal are respectively connected to J Two == and the second two-pole body of the Yin-Yi 丄20, Γ fixed voltage source has not been provided to the quadrupole TM ^ two of the second-dipole di received AC input voltage 顺月匕 / n忑弟一极The body D is the body diode of the first limited inter-controlled transistor 16. #起=Second with body diode diode D2 by AC input sugar _ conduction ^ negative half ^ between the second voltage reverse bias: (four) electric fine & axis ^ the first pole _ subject to AC input The first pole current resistor D2 is the first current limiting resistor R7 and the body diode of the first gated transistor 14 having the body diode. During the positive or negative half cycle, the wave current can be limited to a safe value by the first current limiting resistor R7. According to the corresponding secret, the four-polarity detection, the four-polarity driving circuit and the four-closed control transistor can be divided into the following four rectifier modules: the first positive polarity rectification mode = the first positive polarity detection The first positive polarity driving circuit and the first gateless transistor without the body diode 1〇; the second positive polarity rectifying module includes the second positive polarity detector 4〇2, the second positive polarity The driving circuit 26 and the second gate transistor 16 having a body diode; the first negative polarity rectifier module includes a first negative polarity detector 403, a first negative polarity driving circuit 24 and a first body-connected body diode The closed control transistor 14: the second negative polarity ί flow module = - the negative polarity detector 404, the second negative polarity drive circuit 22 and the second gateless transistor 12 without the body diode. In order to simplify Xia Mingming, this paper only focuses on the first-positive rectifier module. The other two rectifier modules can be analogized by the first positive rectifier module. 3 is a block diagram of a first positive polarity rectifying module according to the present invention, including a first parent current input terminal L, a second AC input terminal Ν, a first DC output terminal Β+, and a first The solid voltage source terminal Vcc丨, a first positive polarity detector 4〇1, a first positive polarity driving circuit 20 and a first-no body diode gate transistor 1〇. The first positive polarity detector 401 has a first input end and a second input end, which are respectively connected to 1 and N. The first positive polarity driving circuit 20 has a first input end and a second input end. And an output end, which is respectively connected to the input end of the Vccl, B+ and the gateless transistor 1〇 of the first bodyless diode; the first gateless transistor 1无 without the body diode has a The input end, a first output end and a second output end are respectively connected to the output ends of the first positive polarity driving circuit 20, L and B+. The gate of the first gateless transistor of the first bodyless diode is located at the input end, and the channel of the gate transistor of the first bodyless diode is located at the first and second outputs between. In steady state operation, a first fixed voltage source across Vccl and B+ has been supplied to the first positive polarity driving circuit 20; a channel of the first gateless transistor of the bodyless body diode can be formed; The first positive polarity detector 401 detects the polarity of the AC input voltage and controls the first positive polarity driving circuit 2 by coupling (but not limited to optical box coupling, magnetic coupling, etc.); The first-in-one body is driven according to the state of the signal, and the electric body 1G is controlled. In the case of Yu Zheng Ban Zhou, the coincidence signal exists, and the first positive polarity drive 2 turns on the channel of the gate-controlled transistor of the first-no body diode. In the negative half, the light-synchronization signal does not exist. The first positive-polarity driving circuit 20 closes the channel of the first gateless transistor 10 of the first non-primary body. 4A shows a first embodiment of a positive polarity rectifying module according to the present invention. The circuit diagram includes a first AC input terminal L, a second AC input terminal N, a milk DC output terminal B+, and a first The fixed voltage source terminal I, a first positive polarity side first positive driving circuit 20 and a first bodyless diode gated transistor 1 are. The first-no-body diode gate-controlled transistor 1〇 uses an insulated gate bipolar transistor, and has a gate (G) and a collector (〇 and an emitter (6). Insulated gate bipolar The gate (G), the collector (C) and the emitter (6) of the crystal Q3 respectively serve as the input end of the first bodyless two-pole controlled transistor 2, the first output end and the second output end Connected to the output terminal of the first positive polarity driving circuit 1 , the AC input terminal L and the DC output terminal B+ respectively. The opening or closing of the insulating gate bipolar transistor Q3 depends on the gate (6) and the emitter ( e) the relative potential difference of m, so the first fixed voltage source, which is provided by an external circuit, must be connected to Yd and referenced to the emitter of the insulated gate bipolar transistor Q3 (ie DC output B+) regardless of the DC output terminal B+ The first positive polarity detector 401 includes a second current limiting resistor Ri^ and an optocoupler optodi〇 mA, wherein the second current limiting resistor RL The input end and the cathode of the photodiode U1A serve as the first and second input ends of the first positive polarity detector 4〇1, respectively Connected to the two AC input terminals 1 and ^; the output of the second current limiting resistor RL is connected to the anode of the photodiode U1A. The first positive polarity detector 401 detects the polarity of the AC input voltage and is illuminated by light. The coupling signal controls the first positive polarity driving circuit 20. During the positive half cycle, the photodiode U1A is turned on by the AC input voltage; the line current can flow through the photodiode U1A; the photodiode U1A is excited by the line current. Luminescence. During the negative half cycle, the photodiode U1A is turned off by the AC input voltage inverse 1378632; the line current cannot flow through the photodiode U1A: the light is excited without emitting light. The first positive polarity driving circuit 2G includes a filter capacitor α — 晶体 晶体 晶体 晶体 U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U The second input end is respectively connected to the VM1 and the DC output terminal B+; the emitter of the photodiode U1A is connected to the input end of the sinusoidal resistor I. The 帛-positive scale circuit such as the ^Xuan output terminal; the filter capacitor C1 The positive and negative electrodes are connected to Vccl and Stream output
曰該第一正極性驅動電路20依據光耦合信號之狀態驅動絕緣閘雙極 電b曰體Q3 〇於正半週躺，光電晶體U1B受光耗合信驗勵而開啟； 驅動電流可流經第-電阻此絕緣閘雙極電晶體印受驅動電壓驅動而 開啟。於負半週期間’光電晶體U1B未受光耗合信號激勵而關閉丨驅 動電流無法流經第-電阻R1;絕緣酸極電晶則3未受驅動電壓驅動 而關閉。第一 The first positive polarity driving circuit 20 drives the insulating gate bipolar electric b body Q3 according to the state of the optical coupling signal, and lies in the positive half cycle, and the photoelectric crystal U1B is activated by the light absorption combined signal excitation; the driving current can flow through the first - Resistor This insulated gate bipolar transistor is driven by the drive voltage to turn on. During the negative half cycle, the photo-electric crystal U1B is not excited by the light-availability signal to turn off the 丨 drive current cannot flow through the first-resistance R1; the insulating acid-electrode crystal 3 is not driven by the drive voltage and is turned off.
•極體U1A未受線電流 須強調本發明中之該第一正極性偵測器401與該第一正極性驅動電 路20間之輕合可為但不受限於光耦合、磁耦合等。為簡化說明，依據 本發明之所有具體實施例以光搞合實現。該第一正極性偵測器401中 之該光二極體（optodiode) U1A與該第一正極性驅動電路2〇中之該光 電晶體（optotransistor) U1B分別充當光發射器（optotransmitter)與光 接收器（optoreceiver )。 圖4B顯示依據本發明之第一正極性整流模組的第二具體實施 例的電路圖。相較於圖4A，圖4B引進一圖騰柱電路（t〇tem_p〇le circuit) 60至其驅動電路20。該圖騰柱電路60包含一 NPN雙極電晶 體Q4與一 PNP雙極電晶體Q5，其各具有一基極(B)、一射極⑹與一 集極(C)。NPN雙極電晶體Q4與PNP雙極電晶體Q5的基極(B)皆連接 至U1B的射極(E); NPN雙極電晶體Q4與PNP雙極電晶體Q5的射極 11 1378632 (E)皆連接至絕緣閘雙極電晶體Q3的閘極(G) ; NPN雙極電晶體Q4的 • 集極(C)與PNP雙極電晶體Q5的集極(〇分別連接至U1B的集極(〇與 絕緣閘雙極電晶體Q3的射極(E)。 圖4C顯示依據本發明之第一正極性整流模組的第三具體實施 例的電路圖。相較於圖4A，圖4C引進一開關電路70至其驅動電 路20。該開關電路70包含一臨界開關（threshold switch) U4、一 PNP • 雙極電晶體Q5、一第二電阻R2、一第三電阻R3與一第四電阻R4。 該臨界開關U4以一可規劃穩壓器（programmable regulator )實現且具· 有一參考端(R)、一正極(A)、一負極(K)與一臨界電壓（threshold voltage ) • K。當，K與A間之通道關閉。當〜咖匕，κ與A間之 通道開啟。 圖4D顯示依據本發明之第一正極性整流模組的第四具體實施 例的電路圖。相較於圖4A，圖4D引進一開關電路80至其驅動電路 20。該開關電路80包含一臨界開關（即npn雙極電晶體Q4)、一 PNP 雙極電晶體Q5、一第二電阻R2、一第三電阻R3、一第四電阻R4與 一第五電阻R5。該臨界開關以一 NPN雙極電晶體q4實現且具有一基 極(B)、一射極(E)、一集極(〇與一臨界電壓匕<125F。 • 圖4A、4B、4C與4D之電路結構與動作原理已詳細揭露於本 案發明人之前發明專利申請案中華民國申請號97119575 ;此處 不再贅述。然而，須強調圖4A、4B、4C與4D可以離散零件或 積體電路實現。 圖5顯示依據本發明之具浪湧電流限制器之閘控橋式整流器的 一具體實施例的電路圖，其中四光二極體U1A、U2A、U3A與U4A 分別對應於四光電晶體U1B、U2B、U3B與U4B ;四極性偵測器可以 兩種方式實現.（1)各自具有一限流電阻Rl與一光二極體串聯，如 圖1所示，（2)四光二極體先並聯再與—限流電阻串聯，如圖5 所示；四極性驅動電路20、22、24與26採用圖4D之電路結構； 12 1378632 二無本體二極體的閘控電晶體10與12皆採用一絕緣閘雙極電晶體 Q3 ;二有本體二極體的閘控電晶體14與16皆採用一 n通道金氧半場 效電電晶體Q6。一般而言’圖5中之該四極性驅動電路2〇、22、24 與26可採用圖4A、4B、4C或4D之任一電路結構。 於起動階段，該二固定電壓源尚未被提供予該四極性驅動電路2〇、 22、24與26 ;該四閘控電晶體1〇、12、14與16之通道尚未被形成； 浪'/勇電流僅能流經該浪>勇電流限制器50與該二有本體二極體的閘控電 晶體14與16之本體二極體且被該浪湧電流限制器5〇限制至一安全值。 於穩態操作，該二固定電壓源已被提供予該四極性驅動電路2〇、 22、24與26，該四閘控電晶體1〇、12、14與16之通道可被形成；該 四光二極體U1A、mA、U3A與WA偵啦錄人電壓之雛且以光 .鶴合信號分別控制該四極性驅動電路2〇、26、24與22，其依據光輕合 信號之狀態分別驅動該四閘控電晶體1〇、16、14與12 ^旁通該浪; 電流限制器50並履行橋式整流之功能。 以上所述之實施例僅係為說明本發明之技術思想及特點，其 在使熟習此徽藝之人士㈣_本發明之魄麟財施，去 以之限林發明之柄麵，即大驗本發明賴故精神所^ 等變化或修飾，仍應涵蓋在本發明之專利範圍内。 巧 13 1378632 【圖式簡單說明】 =1顯不依據本發w之具浪職流限制器之閘控橋式整流器的方塊 圖0 圖2顯不依據本發明之浪消電流限制器5Q的—$體實施例的電 路圖。 圖3顯示罐本㈣之第—正極性整缝_方塊圖。 圖4A顯示依據本發明之第一正極性整流模組的第一具體實施 例的電路圖。 圖4B顯示依據本發明之第一正極性整流模組的第二具體實施 例的電路圖。 圖4C顯示依據本發明之第一正極性整流模組的第三具體實施例 的電路圖。 圖4D顯示依據本發明之第一正極性整流模組的第四具體實施例 的電路圖。 圖5顯示依據本發明之具浪湧電流限制器之閘控橋式整流器的 一具體實施例的電路圖。 【主要元件符號說明】 10、12 無本體二極體的閘控電晶體 14、16 有本體二極體的閘控電晶體 20 > 26 正極性驅動電路 22、24 負極性驅動電路 50 浪湧電流限制器 401、402 (正)極性偵測器 403、404 (負)極性偵測器 14 1378632The pole body U1A is not subjected to the line current. It should be emphasized that the light combination between the first positive polarity detector 401 and the first positive polarity driving circuit 20 in the present invention may be, but is not limited to, optical coupling, magnetic coupling, and the like. To simplify the description, all of the specific embodiments in accordance with the present invention are implemented in light. The optodiode U1A in the first positive polarity detector 401 and the optotransistor U1B in the first positive polarity driving circuit 2 are respectively used as an optical transmitter and an optical receiver. (optoreceiver). Fig. 4B is a circuit diagram showing a second embodiment of the first positive polarity rectifying module in accordance with the present invention. In contrast to FIG. 4A, FIG. 4B introduces a totem pole circuit 60 to its drive circuit 20. The totem pole circuit 60 includes an NPN bipolar transistor Q4 and a PNP bipolar transistor Q5 each having a base (B), an emitter (6) and a collector (C). The base (B) of NPN bipolar transistor Q4 and PNP bipolar transistor Q5 are connected to the emitter (E) of U1B; the emitter of NPN bipolar transistor Q4 and PNP bipolar transistor Q5 11 1378632 (E ) are connected to the gate (G) of the insulated gate bipolar transistor Q3; the collector of the NPN bipolar transistor Q4 (C) and the collector of the PNP bipolar transistor Q5 (〇 are connected to the collector of U1B, respectively) (〇) and the emitter (E) of the insulating gate bipolar transistor Q3. Fig. 4C is a circuit diagram showing a third embodiment of the first positive polarity rectifying module according to the present invention. Compared with Fig. 4A, Fig. 4C introduces a The switch circuit 70 includes a threshold switch U4, a PNP, a bipolar transistor Q5, a second resistor R2, a third resistor R3 and a fourth resistor R4. The critical switch U4 is implemented as a programmable regulator and has a reference terminal (R), a positive terminal (A), a negative electrode (K) and a threshold voltage (K). The channel between K and A is closed. When the channel is opened, the channel between κ and A is turned on. Figure 4D shows the fourth of the first positive rectifier module according to the present invention. FIG. 4D shows a switching circuit 80 to its driving circuit 20. The switching circuit 80 includes a critical switch (ie, npn bipolar transistor Q4) and a PNP bipolar transistor Q5. a second resistor R2, a third resistor R3, a fourth resistor R4 and a fifth resistor R5. The critical switch is implemented by an NPN bipolar transistor q4 and has a base (B) and an emitter ( E), a collector pole (〇 and a threshold voltage 匕 < 125F. • The circuit structure and operation principle of Figures 4A, 4B, 4C and 4D have been disclosed in detail in the invention patent application of the inventor of the present invention, Republic of China application number 97119575; 4A, 4B, 4C, and 4D can be implemented in discrete parts or integrated circuits. Figure 5 shows a specific implementation of a gated bridge rectifier with a surge current limiter in accordance with the present invention. The circuit diagram of the example, wherein the four photodiodes U1A, U2A, U3A and U4A correspond to the four photoelectric crystals U1B, U2B, U3B and U4B respectively; the four polarity detectors can be realized in two ways. (1) Each has a current limiting resistor Rl is connected in series with a photodiode, as shown in Figure 1, (2) four The diodes are connected in parallel and then connected in series with the current limiting resistor, as shown in Figure 5; the four-polarity driving circuits 20, 22, 24 and 26 use the circuit structure of Figure 4D; 12 1378632 Two gated transistors without body diodes Both 10 and 12 use an insulated gate bipolar transistor Q3; two gated transistors 14 and 16 with body diodes use an n-channel gold oxide half field effect transistor Q6. In general, the four-polarity driving circuits 2, 22, 24, and 26 in Fig. 5 can employ any of the circuit configurations of Figs. 4A, 4B, 4C, or 4D. In the starting phase, the two fixed voltage sources have not been supplied to the four-polarity driving circuits 2〇, 22, 24 and 26; the channels of the four gate-controlled transistors 1〇, 12, 14 and 16 have not yet been formed; The brave current can only flow through the wave> the permanent current limiter 50 and the body diodes of the gate transistors 27 and 16 having the body diodes and are limited by the inrush current limiter 5 to a safe value. In steady state operation, the two fixed voltage sources have been supplied to the four polarity driving circuits 2〇, 22, 24 and 26, and the channels of the four gated transistors 1〇, 12, 14 and 16 can be formed; The light diodes U1A, mA, U3A and WA detect the recording voltage and control the four-polarity driving circuits 2〇, 26, 24 and 22 respectively by the light and the Hehe signal, which are respectively driven according to the state of the light-lighting signal. The four gate control transistors 1〇, 16, 14 and 12^ bypass the wave; the current limiter 50 performs the function of bridge rectification. The embodiments described above are only for explaining the technical idea and characteristics of the present invention, and the person who is familiar with the art of the art (4) _ the Kirin Fortune of the present invention is limited to the handle of the invention, that is, the test Variations or modifications of the spirit of the present invention should still be covered by the scope of the present invention. Qiao 13 1378632 [Simple description of the diagram] =1 shows the block diagram of the gate-controlled bridge rectifier with the wave current limiter according to the present invention. Figure 2 shows the wave-free current limiter 5Q according to the invention. Circuit diagram of the body embodiment. Figure 3 shows the first - positive full seam _ block diagram of the can (4). Figure 4A is a circuit diagram showing a first embodiment of a first positive polarity rectifying module in accordance with the present invention. Fig. 4B is a circuit diagram showing a second embodiment of the first positive polarity rectifying module in accordance with the present invention. Fig. 4C is a circuit diagram showing a third embodiment of the first positive polarity rectifying module in accordance with the present invention. Fig. 4D is a circuit diagram showing a fourth embodiment of the first positive polarity rectifying module in accordance with the present invention. Figure 5 is a circuit diagram showing a specific embodiment of a gated bridge rectifier with a surge current limiter in accordance with the present invention. [Description of main component symbols] 10, 12 gated transistors without body diodes 14, 16 gated transistors with body diodes 20 > 26 positive polarity drive circuits 22, 24 negative polarity drive circuit 50 surge Current limiter 401, 402 (positive) polarity detector 403, 404 (negative) polarity detector 14 1378632
60 圖騰柱電路 70 開關電路 80 開關電路 D1 ' D2 二極體 R1、R2、R3、R4、R5 電阻 RL ' R7 限流電阻 Q3 絕緣閘雙極電晶體 Q4、Q5 雙極電晶體 Q6 N通道金氧半場效電晶體 U1A、U2A、U3A、U4A 光二極體 U1B、U2B、U3B、U4B 光電晶體 U4 臨界開關 B+、B· 直流輸出端 L、N 交流輸入端 Cl 濾波電容器 Vcci、Vcc2 固定電壓源端 G 閘極 S 源極 D 汲極 B 基極 E 射極 C 集極 R 參考端 A 正極 K 負極 1560 Totem pole circuit 70 Switch circuit 80 Switch circuit D1 ' D2 Diode R1, R2, R3, R4, R5 Resistor RL ' R7 Current limiting resistor Q3 Insulated gate bipolar transistor Q4, Q5 Bipolar transistor Q6 N channel gold Oxygen half-field effect transistor U1A, U2A, U3A, U4A Photodiode U1B, U2B, U3B, U4B Photoelectric crystal U4 Critical switch B+, B· DC output terminal L, N AC input terminal Cl Filter capacitor Vcci, Vcc2 Fixed voltage source terminal G gate S source D drain B base E emitter C collector R reference terminal A positive terminal K negative electrode 15