101年7月20日修正替換頁 I378563 九、發明說明： 相關申請的交叉引用_本申凊是2007年9月11日提交的、共同申請 的美國專利申請No. 11/900, 616、名稱為POWER MOS DEVICE的部分繼 續申請，也是2005年2月11日提交的、美國專利申請No. 11/056, 3仙 (現在的專利號為7, 285, 822)、名稱為POWER MOS DEVICE的繼續申請， 出於所有目的，將上述兩個文獻在此引入。 【發明所屬之技術領域】 本發明係有關一種金屬氧化物半導體（M0S)元件及其製造方法。 【先前技術】 功率M0S元件通常在電子電路中使用。取決於應用，可能期待不同 的元件特性。一個範例應用是DC_DC轉換器，其包括一個功率M〇s元件 作為同步整流器（也稱為低端FET)，和另一個功率M0S元件作為栌制 =關（也稱為.高端FET)。低端FET通常要求較小的導通電阻，以^庐 f較好的功率開關效率。高端m通常要求較小的閑極電容，以 = 迷開關和良好性能。 X、、 晶體的導通電阻（L)值通常與通道長度⑴成正比，與每單 性能和/穿電，反比° #選擇L的值時’應當考慮 面積的單2 f以及可以通過減小單元尺寸來增大每單位 單位面積的單穿現象，通道長度Lit常受到限制。每 本體區良由於製造技術以及由於需要使單元的源極區和 容也增大。嘴著通道長度和單元密度的增大，問極電 用（諸如，同牛紋、,\，的損耗’較低的元件電容是優選的。在某些應 導致效率她_的電荷似賴二極_正轉降也會 值得期待的β°二口素一起便限制了DM0S功率元件的性能。 於當前可達的DMGS轉元件的導财阻和閘極電容能夠低 用的是，開發出勺叢和功率消耗都會改善。還可能有 率元件。 的I程，該製程能夠可靠地製造出改進的DM0S功 5 1378563 101年7月20日修正替換頁 【發明内容】 -- 為此’本發明提供了一種半導體元件及其製造方法，得以有效改善 功率開關的可靠性和功率消耗。 “本發明提供-種形成縣導體基底上的半導體元件，包括：汲極； 覆盍所述沒極的遙晶層；以及主動區，包括：本體，所述本體置於所述 蟲晶層中’並具有本體頂表面；源極，所述源極截入在所述本體中，並 從所述本體頂表面延伸至所述本體中；閘極溝槽，所述閘極溝槽延伸至 所述遙晶層中所述麻置於所述閘極溝槽中；主動區接觸溝槽， 所述主動區接觸溝槽通過所述源極和所述本體延伸至所述汲極中；以及 主動區接觸電極’所述主動區接觸電極置於所述主動區接觸溝槽内，其 中所述主動區接觸電極和所述沒極形成蕭特基二極體；以及蕭特基能障 控制層，所述蕭特基能障控制層置於與所述主動區接觸溝槽鄰近的所述 在另-方面中’本發明提供—種製造半導體元件的方法，包括：在 覆蓋半導縣底的Μ層中形成·賴；在所關極溝射沉積間極 材料，形成本體；形成源極；形成主動區接觸溝槽，所述主動區接觸 2通過所述源極和所述本觀伸至所述汲財；沉積蕭特基能障控制 層，以及在所述主動區接觸溝槽内佈置接觸電極。 底下藉由具體實施例配合所附的圖式詳加說明，當更容易瞭解本發 明之目的、技術内容、特點及其所達成之功效。 χ 【貫施方式】 不兔則以用多種方式實現，包括實現為製程、裝置、系統 、電腦可讀媒介，諸如，電腦可讀存儲媒介，或者電腦網路，其^ 秋式指令被輕親結轉通信鏈結發送）。在本制書+，這些 或者本發明可峨_任何其伽彡式，都可_為技術。被描述^ ‘ ^置為執彳了任務的元件”（諸域顧或者記㈣）既包括通用元 為在給定時間執行任務）也包括專用元件（其被製造以執 任務）。通常，在本發·_，所公_製程步驟的順序可以 本發明的-個或多個實施例的具體描述在以下與示出了本發明 6 1378563 101年7月2〇曰修正替換頁 理的附® -起提供。雖然。结合這制實施娜述了 — ίί ΐ發明的範圍僅由申請專利範圍來蚊，並財 毛月涵现了夕種替代方式、改進以及等效物。在以下描 節本發明的全面理解。這些細節是處於範例的“二 者·ϋί據權利要求來實現’而無需這些具體細節的 紐料访力女’了，月楚的目的’在涉及本發明的技術領域中公知的技 術材枓亚〉又有砰細描述，以避免本發明被不必要地混淆。 對金屬氧錄半導體⑽）耕及錢造進行贿。出於 目的’在本綱書巾詳細討論Ν通道元件，其成 通道元件。 A第圖示出了若干雙擴散金屬氧化物半導體（DM〇s)元件 施例。S 1A圖是_s元件的實施例的橫截面視圖。在此範例中元件 =〇包括沒極’其形成在N+型半雜基底1〇3的背面。沒極區延伸到覆 盍了基底103的、Μ—型半導體的蠢晶（印υ層1〇4中。在為晶戶1〇4 中铜出閘極溝槽（諸如m、113和115)。_氧化物層12^成在 閘極溝槽内。閘極m、133和135分別佈置在間極溝槽⑴、ιΐ3和 115内，並且通過氧化物層而與磊晶層絕緣。閘極是由諸如多晶矽 jpoly)的導電材料製成的，而氧化物層是由諸如熱氧化物的絕緣^料 製^的。具體地’閘極溝槽1U位於端接區（terminati〇nregi〇n)中， 該端接區佈置有用來連接至閘極接觸金屬的閘極流道（职忮πηηπ) 131。出於該目的，與主動閘極溝槽113和115相比，閘極流道溝槽ιη 可以更寬且更深。進一步地，閘極流道溝槽1U和其相鄰的主動溝&(在 此情況下為溝槽113)之間的間距可以比主動閘極溝槽113和115之間 的間距大。 源極區150a-150d分別嵌入本體區l40a-140d中。源極區從本體的 頂表面向下延伸到本體本身中。儘管本體區沿著所有閘極溝槽的側部被 植入，但疋源極區僅僅在鄰近主動閘極溝槽處被植入，而不在閘極流道 溝槽處被植入。在所示實施例中，諸如丨33的閘極具有閘極頂表面，該 7 】〇】年7月20日修正替換百 閘極頂表面基本上在叙有祕的賴的頂表面之' 保證了閘極和源極的重疊，從而允許源極區比呈有凹陷 :生己置 ，區淺，並且這樣的配置增大了元件的效率和性能。閘極多 在源極-本體接面之上延伸的量可以針對不同實施例而改變。 tr體顧7本艇㈣A面战伸，喊從ii 在操作期間，汲極區和本體區一起作為二極體的作用，稱 _ 極體。介電材料層⑽被佈置於閘極的上面，以便將閘極與源極 接觸絕緣。介電洲在祕的頂上以及在本體區和祕區的頂上了 絕緣區，諸如施-驗。適當的介電材料包括熱氧化物 '低溫^化 (LTO)、硼磷矽玻璃（bpsg)等。 大量的接騎槽112a-112b形成在祕區和本體區附近的主動間 極溝槽之間。這些溝槽浦為主祕躺溝槽，因為這麟槽鄰近元件 的主動區（由源極區和本體區形成的）。例如，接觸溝槽U2a延伸通過 源極和本體，形成了鄰近溝槽的源極區15〇a_15〇b和本體區 140a-140b。相反，形成在閘極流道131頂上的溝槽117並不位於主動 區附近，因此’溝槽117 *是主動區接觸溝槽。溝槽117被稱為閘極接 觸溝槽或者閘極流道溝槽，因為連接至閘極信號的金屬層172a沉積在 溝槽内。通過溝槽111、113和115之間在第三維度（未示出）中的互 連’將閘極信號饋送給有源閘極133和135。金屬層172a與金屬層172b 分離’金屬層172b通過接觸溝槽ii2a-i 12b連接至源極區和本體區， 以提供電源。在所示範例中，主動區接觸溝槽和閘極接觸溝槽具有基本 上相同的深度。 元件100具有主動區接觸溝槽112a-ii2b，它們都比本體淺。此配 置k供了良好的擊穿性能、更低的電阻和更低的茂漏電流。另外，由於 主動接觸溝槽和閘極接觸溝槽是使用一步製程形成的，由此它們具有相 同的深度’所以具有比本體淺的主動接觸溝槽可以避免閘極接觸溝槽穿 過諸如131的閘極流道。 在所示範例中，FET通道沿著源極/本體接面和本體/汲極接面之間 .1378563 101年7月20曰修正替換頁 的主動區閘極溝槽側壁形成。在具有短通道區的元彳-- 極之間電壓的增大，空乏區擴大，並且可能最终到達源極接面。這種現 象，稱為擊穿’限制了通道可被縮短的程度。在某些實施例中，為了避 免擊穿，利用Ρ型材料來對諸如沿著主動區接觸溝槽壁的區域 170a-170d的區域進行重摻雜以形成ρ型區。ρ+型區避免了空乏區侵佔 源極區。這樣，這些植入有時稱為抗擊穿植入或者避免擊穿植入。在某 些實施例中，為了實現聲稱的抗擊穿效果，p+區盡可能地離通道區近和 /或如製造對準能力和P+側壁摻雜滲透控制所允許的那樣近。在某些實 施例中，溝槽接觸和溝槽之間的不對準通過對接觸進行自行射準爽^ 化，以及將溝槽接觸盡可能置於接近溝槽之間的中心處。這些结構上的 增強允許通道被縮短，使得通道每單位面積中的淨電荷適當地低於在理 想的未受保護結構巾避免擊穿所需的最小電荷。除了改善本體接觸電阻 外，抗擊穿植人喊得構建非常淺溝槽的短通道元件成為可能。在所示 實施例中’接聯槽112a-mb比本體區丨術-應淺，並且不會在本 體區中-直延伸。元件的導通電阻RdsDn和閘極電容被減小。 :在接觸溝槽112a-l 12b和閘極溝槽！ ！7中佈置導電材料以形成接觸 電極。在主祕由於擊穿植人沿著接觸溝槽的嫩設置，而不沿著 接觸溝槽的底部設置’所以_電極與N_汲涵购目翻。接觸電極 極區ΓΪ形成了蕭特基二極體（與本體二極體並行）。蕭特基二極 n了本體—鋪正向壓降並將存_储最小化，使得瞻et更 σ政率。能夠同時形成到㈣極的蕭特基接觸和到ρ+本體和Ν+源極的 =的歐姆接觸的-種金屬被用來形成電極施_勵。諸如欽⑺）、 某此t二(Ρ匕鎮⑺或者任何其他適當的金屬都可以使用。在 中，至屬層172由紹（Α1)或者由Ti/TiN/A1 4層製成。 大，、漏電流域特基能障高度有關。隨著能障高度的增 區、，蓋及正向餅也獻。在咐範财，過在主動 ^ !：〇：：：；： 在此範财， 9 1378563 101年7月20曰修正替換頁 ^比較淺並且是低劑量的；因此，完全被耗盡而與^壓無關。肅特基能 障控制層用來㈣蕭特基能障高度，從而允許對誠電流進行更好的控 制，以及改進蕭特基二極體的反向恢復特性。以下描述形成蕭特基能障 控制層的細節。 “第jB圖是DMOS元件的另-實施例的橫截面視圖。元件！ 〇2也包括 ^特基能障控制層19〇a-i9〇b ’位於主動區接觸溝槽的底部周圍。在此 範例中，閘極接觸溝槽117的深度與主動區接觸溝槽U2a_112b的深度 不同。主動區接觸溝槽比本體區l4〇a_14〇d深，並且主動區接觸溝槽延 伸超過了本體區。由於主動接觸溝槽較深，所以主動接觸溝槽為沿著側 壁製作^姆接觸提供了更化域’並且帶來了更好的非箝位元感應開關 (UIS)旎力。而且，通過使閘極接觸溝槽比主動接觸溝槽淺，閘極接 觸溝槽將不太可能在磁彳製程期間穿透問極流道多晶⑦，而這對於具有 相對淺的閘極多晶石夕的元件（諸如，使用這樣製程製造的元件，即，該 製程，導關極多晶料會在本體的頂表面之上延伸）是有用的。 第1C圖疋DMOS元件的另-實施例。在此範例中，閘極接觸溝槽 117和主動區接觸溝槽ica-iub具有不同的深度。另外，每個主動區 接觸溝槽的深度並不-致，因為溝槽深度在平行於基底表面的方向上會 雙化。如以下更詳細所述，主動區接觸溝槽是使用兩步製程形成的，導 致第-接綱口（例如，12Ga-12Gb)比第二接觸開σ(例如，n9a_119b). 寬。主動區接觸溝槽的輪廓形狀允許更大的歐姆接觸區域並且通過抗擊 穿植入170a-170d更好的避免擊穿，並且改進了元件的_能力。香農 植入沿著第二接觸開口的㈣和底部分佈，形成了㈣基能障控 190a-190b。 第1D-1F圖示出了整合低植入本體二極體的DM〇s元件的實施例。 疋件106、108和110具有比本體區'淺的主動區接觸溝槽。在某些實施 例中厚度約為G.G卜0. 的本财將主祕刺的絲餘晶層分 開，形成了本體/汲極接面之下的低植入二極體。薄體層的厚度和摻雜 水準（該薄體層位於主動區接觸溝槽和汲極之間）被調整，以使得在反 向偏壓中，此薄體層幾乎完全耗盡’而在正向偏壓巾，薄體層不會耗盡。 1378563 101年7月20日修正替換頁 由於載子已經極大減少，所以整合低植入二極體的元LFTMT1WnF 相比於常規的本體二極體提供了性能上的改進。在適當控_體看的情 況下，低植入本體二極體可以提供與蕭特基二極體相當的性能，帶來的 優勢，於於可以省去蕭縣能雜制層的形成*帶來的簡化製程。 产$ 2圖是示出了降壓型（buck)轉換器電路範例的示意圖。在此 =中，所示電路删使用了高端FET元件2〇1和低端m元件2〇卜 南端兀件201包括電晶n 202和本體二極體2〇4。低端元件2〇7可以使 第1A-1F圖中示出的100、1〇2或者1〇4的元件來實現。元件2〇7 已括电晶體208、本體二極體210和蕭特基二極體212 器電容㈣6和電阻器218。在正常操作期間，元件則被^ 、1Γ攸ί入源傳^到負載。這會引起電流在電感器中上升。當元件 1 jo止日守，電感器電流仍然流動，並轉換方向至元件207的本體二 2m、在短暫的延遲後，控制電路使元件207導通，其導通電晶體 r道幅度地降低沿著元件咐及極—源極端子的正向壓 有蕭特基一極體212的情況下，本體二極體傳導損耗以及移除 Γϋΐ的本體二極體210中存儲的電荷帶來的損耗可能較大。然而， τ： Αΐ一極體212構建在元件207中’並且如果蕭特基二極體具有 f塾降，傳導損耗會極大減小。由於沿著蕭特基二極體的低的正 存i二i體?ΐ體的接面壓降’所以在蕭特基二極體傳導時，沒有 …包何，入，進一步改善了二極體恢復所涉及的損失。 +牌t圖疋不出了用於财職元件的製程的實施例的流程圖。在 將⑴’在覆盖半導體基底的蟲晶層中形成開極溝槽。在步驟304， 沉積於_溝槽中。在步驟識和咖，形成本體和源極。 -二Ϊ 〇，形成接觸溝槽。如下面更詳細所述，在某些實施例中，在 V驟中形成主動區接觸溝槽和閘極區溝槽；在某些實施例中，溝槽 於驟中形成’以獲得不同的深度。在步驟312，將接觸電極佈置 ’槽内。製長300及其步驟可以修改，以產生MOS it件的不同實 轭例二諸如第1A-1F圖中示出的1〇2_11()。 ' 第4A-4U圖是凡件的橫截面視圖，詳細示出了用於製造元件的 I378563 ----—— ϊ〇1年7月20日修正替換頁 ί°在此範例#，N型基底（即，其上生長有 被用作元件的沒極。 在N ίΙϋΓ出了閉極的形成。在第4A圖令，通過沉積或熱氧化， 在Μ基底棚上形成二氧化石夕（祕）層402。在各種實施例令 化石=厚度在麵-3_Α的細。其他厚度也可以朗 =決於期待的閘極高度而進行調整。將光阻層4 = 頂上，並且使用溝槽罩幕來圖案化。 倾化物層的 硬罩㈣下了用於德刻的祕 將fiis— 4+’異向性祕财，留下了諸如42G的溝槽。 =Γ=Γ溝射。之後形成在溝槽情閘極具有基本上與基底 Θ心二曰直塞的側面。在第4D圖中’對⑽2硬罩幕410進行一定量的 溝槽齡概祕刻步驟之後基本上與硬罩幕的邊保 ί留施例中使用的罩幕材料，因為使用Si〇2硬罩幕的^刻 ^ 幕的部相互鮮的姆直的溝槽壁。如果合適，也可以使 I、他材料。傳統上用於硬罩幕钱刻的某些且 使</ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; Part of POWER MOS DEVICE continues to apply, and is a continuation application filed on February 11, 2005, US Patent Application No. 11/056, 3 sen (current patent number 7, 285, 822), name POWER MOS DEVICE The above two documents are hereby incorporated for all purposes. TECHNICAL FIELD OF THE INVENTION The present invention relates to a metal oxide semiconductor (MOS) device and a method of fabricating the same. [Prior Art] Power MOS components are commonly used in electronic circuits. Depending on the application, different component characteristics may be expected. An example application is a DC_DC converter that includes a power M〇s component as a synchronous rectifier (also known as a low-side FET) and another power M0S component as a clamp = off (also known as a high-side FET). Low-side FETs typically require a small on-resistance to better power switching efficiency. High-end m usually requires a smaller idler capacitor to = switch and good performance. X,, the on-resistance (L) value of the crystal is usually proportional to the channel length (1), and the ratio of each single performance and / penetration, inverse ratio ° # select the value of L 'should take into account the area of the single 2 f and can be reduced by the unit Size to increase the single wear per unit area, the channel length Lit is often limited. Each body area is also increased due to manufacturing techniques and due to the need to increase the source area of the cell. The length of the channel and the increase of the cell density, it is preferred to use the lower component capacitance (such as the same as the cow's, \, loss). In some cases, the charge that should cause efficiency is like The pole_turning down is also worth looking forward to. The β° singularity together limits the performance of the DM0S power components. The current DMGS conversion components can be used with low power dissipation and gate capacitance. Both the plex and the power consumption will be improved. There may also be a rate component. The I process, which can reliably produce improved DMOS work. 5 1378563 July 20, 2011 Revision Replacement Page [Invention] - For this invention A semiconductor component and a method of fabricating the same are provided to effectively improve reliability and power consumption of a power switch. The present invention provides a semiconductor component formed on a conductor substrate of a county, including: a drain electrode; a seed layer; and an active region, comprising: a body disposed in the seed layer and having a body top surface; a source, the source being trapped in the body, and from the body top Surface extending to the present a gate trench, the gate trench extending into the remote layer, the hemp being placed in the gate trench; the active region contacting the trench, the active region contact trench passing through a source and the body extending into the drain; and an active region contact electrode, the active region contact electrode being disposed within the active region contact trench, wherein the active region contact electrode and the dummy electrode are formed a Schottky diode; and a Schottky barrier control layer, the Schottky barrier layer being placed adjacent to the active region contact trench in the other aspect - the invention provides A method of manufacturing a semiconductor device, comprising: forming a germanium layer in a germanium layer covering a bottom of a semiconducting county; depositing an interpolar material in the gate trench to form a body; forming a source; forming an active region contact trench, the active The region contact 2 extends through the source and the body to the 汲 ;; deposits a Schottky barrier control layer, and arranges contact electrodes in the active region contact trench. The attached drawings are explained in detail to make it easier to understand the present invention. The purpose, technical content, characteristics and effects achieved. χ [Comprehensive approach] Rabbits are implemented in a variety of ways, including as a process, device, system, computer readable medium, such as a computer readable storage medium. , or the computer network, its ^ autumn command is sent by the light-knot to the communication link). In this book +, these or the invention can be _ any of its gamma, can be _ for the technology. Described ^ ' ^ is set to the component of the task' (the domain or remember (4)) both include the general element to perform the task at a given time) also includes a dedicated component (which is manufactured to perform the task). In general, the order of the steps of the present invention may be described in detail below with respect to the present invention, and the present invention is shown in the following paragraphs. Attached ® - available. although. In combination with this system, the scope of the invention is only the scope of the patent application, and the alternatives, improvements and equivalents are presented. A full understanding of the invention is set forth below. These details are in the example of "both of them are implemented according to the claims" without the need for these specific details. The purpose of the month is to know the technical materials known in the technical field related to the present invention. 〉 There is a detailed description to avoid unnecessarily obscuring the present invention. Bribes and money making for metal oxide semiconductors (10). For the purpose of this article, the channel elements are discussed in detail in this booklet. Figure A shows a number of double diffused metal oxide semiconductor (DM 〇 s) component embodiments. The S 1A diagram is a cross-sectional view of an embodiment of the _s element. In this example, the component = 没 includes a immersed ' Formed on the back surface of the N+ type semi-hybrid substrate 1〇3. The non-polar region extends to the doped crystal of the Μ-type semiconductor overlying the substrate 103 (in the enamel layer 1〇4. In the case of the crystal 〇1〇4 copper Out gate trenches (such as m, 113, and 115). The oxide layer 12 is formed in the gate trenches. The gates m, 133, and 135 are disposed in the interpole trenches (1), ι 3, and 115, respectively, and Insulating the epitaxial layer through an oxide layer. The gate is made of a conductive material such as polysilicon And the oxide layer is made of an insulating material such as a thermal oxide. Specifically, the gate trench 1U is located in a termination region (terminati〇nregi〇n), the termination region is arranged to be connected to The gate contacts the gate channel of the metal (忮πηηπ) 131. For this purpose, the gate runner trench ιη can be wider and deeper than the active gate trenches 113 and 115. Further, the gate The spacing between the pole runner trench 1U and its adjacent active trench & (in this case, trench 113) may be greater than the spacing between the active gate trenches 113 and 115. Source region 150a- 150d are respectively embedded in the body regions l40a-140d. The source regions extend downward from the top surface of the body into the body itself. Although the body regions are implanted along the sides of all the gate trenches, the source regions are only Implanted adjacent to the active gate trench without being implanted at the gate runner trench. In the illustrated embodiment, the gate such as 丨33 has a gate top surface, which is July 7 On the 20th, the replacement of the top surface of the hundred gates is basically on the top surface of the secret, which ensures the overlap of the gate and the source. The allowable source region ratio is recessed: the lifetime is shallow, and the configuration increases the efficiency and performance of the component. The amount of gate extension over the source-body junction can be for different embodiments. And change. tr body care 7 boat (four) A face warfare, shouting from ii during operation, the bungee zone and the body zone together function as a diode, called _ polar body. The dielectric material layer (10) is placed at the gate The upper part is to insulate the gate from the source contact. The dielectric is on the top of the secret and on the top of the body and the secret area, such as application. Suitable dielectric materials include thermal oxide 'low temperature ^ LTO, bismuth bismuth glass (bpsg), etc. A large number of landing grooves 112a-112b are formed between the active interpole trenches near the secret zone and the body region. These trenches are the main sag trenches because the slabs are adjacent to the active regions of the components (formed by the source and body regions). For example, the contact trench U2a extends through the source and body to form a source region 15a- 15b and a body region 140a-140b adjacent to the trench. In contrast, the trench 117 formed on top of the gate runner 131 is not located near the active region, so the 'trench 117* is the active region contact trench. The trench 117 is referred to as a gate contact trench or a gate runner trench because the metal layer 172a connected to the gate signal is deposited within the trench. The gate signal is fed to the active gates 133 and 135 through an interconnection ' between the trenches 111, 113 and 115 in a third dimension (not shown). The metal layer 172a is separated from the metal layer 172b. The metal layer 172b is connected to the source region and the body region through the contact trenches ii2a-i 12b to provide power. In the illustrated example, the active region contact trench and the gate contact trench have substantially the same depth. Element 100 has active zone contact trenches 112a-ii2b that are both shallower than the body. This configuration k provides good breakdown performance, lower resistance and lower leakage current. In addition, since the active contact trench and the gate contact trench are formed using a one-step process, whereby they have the same depth 'so having an active contact trench shallower than the body can prevent the gate contact trench from passing through, for example, 131 Gate runner. In the example shown, the FET channel is formed between the source/body junction and the body/drain junction. 13785563 July 20, 2010 Correction replacement page active region gate trench sidewall formation. In the case of an increase in voltage between the meta-poles with short channel regions, the depletion region expands and may eventually reach the source junction. This phenomenon, called breakdown, limits the extent to which the channel can be shortened. In some embodiments, to avoid breakdown, a smear-type material is used to heavily dope regions such as regions 170a-170d along the active region contact trench walls to form p-type regions. The ρ+ type region avoids the encroachment of the source region. As such, these implants are sometimes referred to as anti-puncture implants or to avoid puncture implants. In some embodiments, to achieve the claimed anti-breakdown effect, the p+ region is as close as possible to the channel region and/or as close as allowed by the fabrication alignment capability and P+ sidewall doping control. In some embodiments, the misalignment between the trench contacts and the trenches is achieved by self-aligning the contacts and placing the trench contacts as close as possible to the center between the trenches. These structural enhancements allow the channel to be shortened such that the net charge per unit area of the channel is suitably lower than the minimum charge required to avoid breakdown in the ideal unprotected structural towel. In addition to improving the body contact resistance, it is possible to resist the breakdown of short channel components that create very shallow trenches. In the illustrated embodiment, the landing groove 112a-mb should be shallower than the body region and will not extend straight in the body region. The on-resistance RdsDn and gate capacitance of the device are reduced. : in contact with trenches 112a-l 12b and gate trenches! ! A conductive material is disposed in 7 to form a contact electrode. In the main secret, because of the tender setting of the implanted person along the contact groove, and not along the bottom of the contact groove, the _electrode and the N_汲 han are turned over. The contact electrode pole region forms a Schottky diode (parallel to the body diode). The Schottky II pole has the ontology—the forward pressure drop and the minimization of the deposits, making the trend more σ. A kind of metal capable of simultaneously forming a Schottky contact to the (four) pole and an ohmic contact to the ρ+ body and the Ν+source = is used to form the electrode. Such as Qin (7)), some of this t (Ρ匕 (7) or any other suitable metal can be used. In the middle layer, the 172 layer is made of Shao (Α1) or Ti/TiN/A1 4 layers. The leakage current domain is highly dependent on the height of the energy barrier. With the increase of the energy barrier height, the cover and the forward cake are also offered. In the Fan Fancai, the active ^!:〇:::;: In this fan, 9 1378563 July 20th, 2011 Correction replacement page ^ is relatively shallow and low dose; therefore, it is completely depleted and has nothing to do with compression. The Supreme energy barrier control layer is used to (4) the Schottky barrier height, thus Allows better control of the honest current and improves the reverse recovery characteristics of the Schottky diode. The following description details the formation of the Schottky barrier control layer. "JB is a further embodiment of the DMOS device. Cross-sectional view. Element! 〇2 also includes a special barrier control layer 19〇a-i9〇b' located around the bottom of the active contact trench. In this example, the depth and active of the gate contact trench 117 The depth of the area contact trench U2a_112b is different. The active area contact trench is deeper than the body area l4〇a_14〇d, and the main The active contact trench extends beyond the body region. Since the active contact trench is deeper, the active contact trench provides a better domain along the sidewall and provides better non-clamping sensing. The switch (UIS) is too strong. Moreover, by making the gate contact trench shallower than the active contact trench, the gate contact trench will be less likely to penetrate the transistor 3 during the magnetization process, and this is true for An element having a relatively shallow gate polycrystalline spine (such as an element fabricated using such a process, i.e., the process, the conductive polycrystalline material will extend over the top surface of the body) is useful. Another embodiment of the 疋DMOS device. In this example, the gate contact trench 117 and the active region contact trench ica-iub have different depths. In addition, the depth of each active region contact trench is not uniform. Because the trench depth is doubled in a direction parallel to the surface of the substrate. As described in more detail below, the active region contact trench is formed using a two-step process resulting in a first-junction (eg, 12Ga-12Gb) ratio. The second contact opens σ (for example, n9a_119b). Width. Main The contoured shape of the zone contact trench allows for a larger ohmic contact area and better avoids breakdown by the puncture resistant implants 170a-170d, and improves the component's ability. Shannon implants along the second contact opening (4) And the bottom distribution, forming (4) base energy barriers 190a-190b. The 1D-1F diagram shows an embodiment of a DM〇s element incorporating a low implant body diode. The elements 106, 108, and 110 have a specific body The shallow 'active region contact trenches. In some embodiments, the thickness of the GG is 0. The main layer of the main secret thorn is separated, forming a low implant under the body/drain junction. Into the diode. The thickness of the thin layer and the doping level (between the active layer contact trench and the drain) are adjusted so that in the reverse bias, the thin layer is almost completely depleted' In a forward biased towel, the thin layer is not depleted. 1378563 Revised replacement page July 20, 2011 Since the carrier has been greatly reduced, the integration of the low implanted diode LFMMT1WnF provides a performance improvement over conventional body diodes. Under the condition of proper control, the low implanted body diode can provide the performance comparable to that of the Schottky diode, and the advantages brought about it can save the formation of the Xiaoxian energy miscellaneous layer. The simplified process. The $2 diagram is a schematic diagram showing an example of a buck converter circuit. In this =, the circuit shown uses the high-side FET element 2〇1 and the low-side m element 2〇. The south-end element 201 includes an electro-crystal n 202 and a body diode 2〇4. The low-end element 2〇7 can be realized by the elements of 100, 1〇2 or 1〇4 shown in Figs. 1A-1F. Element 2〇7 includes transistor 208, body diode 210 and Schottky diode 212 capacitor (4) 6 and resistor 218. During normal operation, the component is transferred to the load by ^, 1Γ攸. This causes current to rise in the inductor. When the component 1 is stopped, the inductor current still flows, and the direction is switched to the body 2 of the element 207 for 2 m. After a short delay, the control circuit turns on the component 207, and the conduction transistor crystal is ramped down along the component. In the case where the forward voltage of the 咐 and the pole-source terminal has the Schottky diode 212, the loss of the bulk diode and the loss of the charge stored in the body diode 210 from which the ruthenium is removed may be large. . However, τ: Αΐ one pole 212 is built in element 207' and if the Schottky diode has f塾 drop, the conduction loss is greatly reduced. Because of the low pressure of the singularity of the scorpion of the singularity of the singularity of the singularity of the singularity of the singularity of the singularity of the singularity of the singularity of the singularity The loss involved in recovery. The + card t diagram does not show a flow chart of an embodiment of a process for a financial component. An open trench is formed in (1)' in the mycelium layer covering the semiconductor substrate. At step 304, it is deposited in a trench. In the steps to identify and coffee, form the body and source. - Two turns 〇, forming contact grooves. As described in more detail below, in some embodiments, active region contact trenches and gate region trenches are formed in V-curves; in some embodiments, trenches are formed in the bumps to achieve different depths. . At step 312, the contact electrodes are disposed in the slots. The length 300 and its steps can be modified to produce different conjugate examples of MOS it pieces such as 1 〇 2_11() shown in Figures 1A-1F. 'Fig. 4A-4U is a cross-sectional view of the piece, detailing the I378563 used to manufacture the component ----- 7 July 20th revised replacement page ί° in this example #, N type The base (i.e., the growth of the electrode used as the element is formed. The formation of the closed pole is formed in N ί. In the 4th AA, the formation of the dioxide on the base of the raft is formed by deposition or thermal oxidation. Layer 402. In various embodiments, the fossil = thickness is in the thickness of the surface -3 Α. Other thicknesses can also be adjusted according to the expected gate height. The photoresist layer 4 = top, and a trench mask is used. To pattern. The hard cover of the pour layer (4) is used to secrete the fiis-4 + ' anisotropic secrets for the German engraving, leaving a groove such as 42G. =Γ=Γ沟射. The trench gate has a side that is substantially parallel to the base of the substrate. In Figure 4D, the '10' 2 hard mask 410 is subjected to a certain amount of trench ageing steps followed by a hard mask. Bian Bao ί retains the mask material used in the application, because the surface of the screen of the Si〇2 hard mask is fresh and straight. Appropriate, it is also possible I, other materials traditionally used for hard mask and to make some money carved
Si3队’會留下帶有曲率的侧後 的材枓’遠如 極而言欠佳。 讀壁’讀於在下述步驟中形成閘 施例ΐ弟、===向/t地侧基底以將溝槽的底部圓化。在某此實 :用。為了給生長問極介電材料提供光滑的表面' 2 ^30。然後’通過濕侧製 在=中 在溝槽中熱生長的層432作為介電材料。則θ在弟4G圖中， 在第4H圖中，沉積多晶矽44〇以 石=摻雜以獲取適當的間極電阻。在某些實施“ϋ位了，多晶 日日石夕層時進行摻雜。在某些實施例中，在沉 位）沉積多 ”圖中，對Si〇2頂上的多晶石夕層進 ^ 丁摻雜。在 錢點上，閘極的絲面444相對於Si〇== 成的間極。 陷的，然而，取決於硬罩幕層41〇的 、 =仍然是凹 石夕的71爲/mr 4- ^ 子又’間極的頂表面444可以t於 頂層碰。在某些實施例中，在多晶相姓刻中不使用罩 12The Si3 team's will leave the material behind the curvature with a curvature that is far less good. The read wall' is read in the following steps to form a gate, a === to the /t ground side substrate to round the bottom of the trench. In a certain case: use. In order to provide a smooth surface for the growth of the dielectric material '2 ^ 30. Layer 432, which is thermally grown in the trench by wet side, is then used as a dielectric material. Then θ is in the 4G diagram. In the 4H diagram, the polysilicon 矽44〇 is deposited with stone=doping to obtain the appropriate interpole resistance. In some implementations, "doping, polycrystalline day, day doping, doping. In some embodiments, in the sinking" deposition multiple" figure, on the top of the Si〇2 polycrystalline stone layer ^ Ding doping. At the money point, the surface 444 of the gate is relative to the interpole of Si〇==. The trapped, however, depends on the hard mask layer 41 =, = 71 is still a concave eve 71 / mr 4- ^ sub- and the inter-pole top surface 444 can be touched on the top layer. In some embodiments, the cover is not used in the polycrystalline phase.
/OJOJ 些實施例中，y·夕日A 1〇】年7月20曰修正替換頁 使用幹_來鎌鮮幕。力"7、SiG2硬轉。在某些實施例中， 多晶石夕間極在基底表面（並中；;=;^^時_製程停止，從而使 他值也可以使用。在這約細A-2_A。其 :^表面上提供了期待量的閘極延 件而簡化。例如，在羊此杏針對錢具有凹陷的閘極多晶石夕的元 非常薄的s1〇2硬罩幕，在形成溝槽期間使用光阻罩幕或者 延伸。 α此所乡晶料會姆表面上 墓圖示出了源極和本體的形成。在第4κ ®中，使用本體罩 2 If面上對光阻層45G進行圖案化。未遮蔽的區域植入有本體i 想阻播物伽的情況下執行本體植入，從而 了連續的本體區。在第礼圖中 ^ 曰/成 (b〇dydrive) 在某些實酬中’用來植人本體換雜物 的月匕里、，.勺在30〜600keV之間’劑量約在5el2_4el3離子心2 _祕本體深度約在(U—2.4_之間。通過改變因數，包括植入倉:/OJOJ In some embodiments, y· 夕日 A 1〇] July 20th 曰 correction replacement page Use dry _ to smash the fresh screen. Force " 7, SiG2 hard turn. In some embodiments, the polycrystalline spine is at the surface of the substrate (and in; ;;; ^ ^ when the process stops, so that his value can also be used. In this about A-2_A. Its: ^ surface The simplification of the expected amount of gate extension is provided. For example, in the sheep, this apricot has a very thin s1〇2 hard mask with a depressed gate polycrystalline stone, and a photoresist is used during the formation of the trench. The mask or the extension. The tomb diagram on the surface of the crystal material shows the formation of the source and the body. In the 4K, the photoresist layer 45G is patterned using the body cover 2 If. The shaded area is implanted with the ontology i to perform the ontology implantation in the case of blocking the gamma, thus forming a continuous body region. In the figure of the ceremony, ^ 曰 / 成 (b〇dydrive) is used in some remunerations To implant the human body to change the debris of the moon, the spoon is between 30~600keV' dose is about 5el2_4el3 ion core 2 _ secret body depth is about (U-2.4_. By changing the factor, including implantation warehouse:
===散溫度’可以獲得不同的深度。在擴散製程期間，形成T 在第4M圖中，使用源極罩幕對光阻層似進行圖案化。在所 施例中’源極罩幕464不會阻擋主動溝槽之間的任何區域。 例中’源極罩幕464也對主動溝槽之間的中央區域（未示出）進行阻貝幹。 將源極摻雜物植入未遮蔽區域働。在此範例中，坤離子渗入未遮蔽田區 域=的石夕，以形成N+型源極。在某些實施例中’用於植入源極推雜物的 能量約在HMGGkeV之間，劑量約在lel5_lel6離子心2之間，以及 得到的源極深度約在〇· 05-0. 5Μ之間。可以通過改變因數，諸如播雜 1378563 101年7月20曰修正替換頁 程也可 旎里和劑置，來實現進一步的深度減小。適當的話n伹八裂程也可 以使用。在第4N圖中，移除光阻，並且加熱晶圓以通過源極驅動製程 來對植入的源極摻雜物進行熱擴散^在源極驅動後，將介電（例如) 層465佈置於元件的頂表面上，並且可選地，在某些實施 緻密化。 I、 第—40-4T圖示出了接觸溝槽的形成以及沿著接觸溝槽 入:在第40圖中，光阻層472沉積在介電層上，並且使用接觸罩幕來 圖案化。執行第-接觸触刻來形成溝槽備和47〇 第一接，溝槽的深度在0.2-2、m之間。 早-貝關中 在第4P1I中，移除絲層’彻植人的離子來 =on _離子。植人能量約為胸祕。在某 5 ί； ί 'Ϊ15 4〇-1〇〇keV ^ A =:。二肌和似形成料防止層。植人傾角約在J之 間。在弟4Q圖中，對植入物進行熱擴散。 又（ 4R @中’進行第二接觸银刻。由於敍刻製程不會影塑 要額外的罩幕。在某些實施例中，溝槽曰的^产曰辦 大了 0.2-G.5M。將擊穿防止層舰穿，沿著溝槽壁 = 物474a-474b。在第4S圖中，使用龅Λ卞/ 穿植入 基能障控制層桃。在某些實施例;蕭特 中，肅特基能障控制層約為0 nl_n n(; r 一 隹杲些貝鈀例 調整===?:;=== 研磨以及後端金叙積 4絲完成製造_加步驟，諸如晶圓 -1378563 101年7月20日修正替換頁 可以使用選擇性的餘。例如，為了製造第—— 106-110，對第4K ® t示㈣本體植人f程進行修改，獻在主動區令 沒有本體阻擋物。本體摻雜物被直接植入'覆蓋暴露的區域以及在閉極 之間形成連續的本體區。在接職刻期間，將溝槽姓刻到比本體區底呷 淺的深度，使本體層低於接觸賴。選擇性地，可崎絲接觸溝样僅 娜穿過本體，以暴露外延沒極區，隨後是利用良好控制的能量和^雜 物的附加本體摻雜植入來穿過接觸溝槽側壁和底部形成薄的本體層^ 在某些實施例中，為了形成蕭特基能障控制層，通過化 : (CVD)來沉積諸如SiGe的窄能隙材料’以在蟲晶層的頂表面上^ 層。在某些實施例中’窄能隙材料層的厚度在從100A到1000A的範圍 内。例如，在某些實施例中使用200A的富石夕SiGe層。在某些實 富石夕SiGe層包括臟的Si和2_ Ge。在某些實施例中，利用 雜物以2el7-2e18/Cm3的濃度來對窄能隙材料層進行原位捧雜 夕 在窄能隙層之上沉積低溫減物層’紐對絲溫肢物層 ίϊίΐ罩幕^娜溝槽乾侧到蟲晶層中。在乾姓刻製程期間，硬 罩幕保沒下面的窄能隙層的部分。 第5Α-6Β ®承出了製造步驟的附加可選實施例。例如 行擊牙防止層擴散（參見第4Q圖）。使用第二接觸罩幕來 · 進行圖案化，以阻擋閘極溝槽504。在第5β圖中第_ 7 02 大主動區接觸溝槽5_罙度。然後移除光阻，並以類 =^=曾 圖式㈣縣能障控繼進行植人。包括金屬沉積和^ =附加元成步驟仍然實施（參見第4U圖）。所得到狀件類似於1 圖所不的70件1〇2 ’其中閘極溝槽具有與主動區接觸溝槽不同 通對第二接觸溝槽蚀刻的單獨的罩幕，以實現不 極‘ 和主動區接觸溝槽的深度，可以使閘極溝槽接觸制得 =冓槽 ^對於祕刻期間擊穿閘極多晶石夕的擔心。這樣，通常使用該外= 晶矽的實施例。 工之仲的閘極多 第6A圖也進行了擊穿防止層擴散（參見第4Q圖）。使用第二接觸===Dispersion temperature' can be obtained at different depths. During the diffusion process, T is formed. In Figure 4M, the photoresist layer is patterned using a source mask. In the illustrated embodiment, the source shield 464 does not block any areas between the active trenches. In the example, the source shield 464 also blocks the central region (not shown) between the active trenches. The source dopant is implanted into the unmasked region 働. In this example, the Kun ion penetrates into the unshaded field = Shi Xi to form an N+ source. In some embodiments, the energy used to implant the source dopant is between about HMGGkeV, the dose is between the lol5_lel6 ion core 2, and the resulting source depth is about 〇·05-0. between. Further depth reduction can be achieved by changing the factor, such as the miscellaneous 1378563, July 20th, 2011, and the replacement page can also be used to achieve further depth reduction. If appropriate, the 伹 伹 裂 也 can also be used. In FIG. 4N, the photoresist is removed and the wafer is heated to thermally diffuse the implanted source dopant by a source drive process. After the source is driven, a dielectric (eg) layer 465 is placed. On the top surface of the component, and optionally, densification is performed in some implementations. I. No. 40-4T shows the formation of the contact trench and the entry along the contact trench: In Fig. 40, the photoresist layer 472 is deposited on the dielectric layer and patterned using a contact mask. The first contact etch is performed to form a trench and a 47 〇 first junction, the trench having a depth between 0.2 and 2 m. Early-Bei Guanzhong In the 4P1I, the silk layer was removed and the ions of the human were added =on_ion. The energy of implanting is about the chest. In a 5 ί; ί 'Ϊ15 4〇-1〇〇keV ^ A =:. The second muscle and the like formation prevent layer. The inclination of the implant is about between J. In the 4Q diagram, the implant is thermally diffused. In addition, (4R @中' performs the second contact silver engraving. Since the engraving process does not affect the additional mask, in some embodiments, the grooved crucible is 0.2-G.5M. The breakdown prevention layer is worn through the trench walls = objects 474a-474b. In Figure 4S, the ruthenium/perforation implants are used to control the layer peach. In some embodiments; Schott, The Sut-based energy barrier control layer is about 0 nl_n n (; r a few palladium-like adjustments ===?:;=== grinding and back-end gold-splitting 4 wires to complete the manufacturing_addition steps, such as wafers -1378563 The replacement page can be used to modify the replacement page on July 20, 101. For example, in order to manufacture the first - 106-110, the 4K ® t (4) ontology is modified, and the active zone is not provided. Body barrier. The bulk dopant is implanted directly into the area covered by the exposure and forms a continuous body region between the closed poles. During the pick-up period, the groove name is engraved to a depth shallower than the bottom of the body region. The body layer is made lower than the contact. Alternatively, the channel can be contacted with the channel to pass through the body to expose the epitaxial region, followed by the use of well controlled energy. And additional body doping implants to form a thin body layer through the sidewalls and bottom of the contact trenches. In some embodiments, to form a Schottky barrier control layer, pass: (CVD) A narrow gap material such as SiGe is deposited to layer on the top surface of the mycelium layer. In some embodiments, the thickness of the 'narrow gap material layer is in the range from 100 A to 1000 A. For example, in some implementations A 200A-rich SiGe layer is used in the example. In some solid-rich SiGe layers, dirty Si and 2_Ge are included. In some embodiments, the narrow energy can be used at a concentration of 2el7-2e18/cm3 using impurities. The layer of the gap material is placed in the in-situ nucleus layer to deposit a low-temperature subtractive layer on the narrow energy gap layer. The new pair of filaments and the temperature of the limb layer ϊ ΐ ΐ ^ ^ 娜 娜 娜 娜 娜 娜 娜 娜 娜 娜 娜 娜 娜 娜 娜 娜 娜 娜 娜 娜 娜The hard mask preserves the portion of the narrow gap layer below. Section 5-6Α introduces additional alternative embodiments of the manufacturing steps, such as the rowing prevention layer diffusion (see Figure 4Q). Using the second contact The mask is patterned to block the gate trench 504. In the 5th figure, the _ 7 02 large active region contact trench 5_ Then remove the photoresist and carry out the implantation with the class = ^ = former figure (4) county energy barrier control, including metal deposition and ^ = additional elementary steps are still implemented (see Figure 4U). The piece is similar to the 70 pieces of 1〇2 in the figure 1. The gate trench has a separate mask that is etched from the active contact contact trench to the second contact trench to achieve the contact between the pole and the active region. The depth of the trench can make the gate trench contact to make a contact with the trench. This is a common example of the use of the outer = crystal germanium. The breakdown of the barrier layer is also performed in the gate 6A (see Figure 4Q). Use the second contact
1J/0J0J 除光阻，並且更深的、更窄的溝槽部分608。移 ic圖所示的】G3 省圖_餘步驟，得到的祕類似於第 中使，這纽柯邮某些實施例 用本斤改進乂可以在形成間極（第4G圖）之後且在使 ^ /拉罩幕（圖4K)之前進行。遍及磊晶層，沉積且有盥石曰厗 Γ姆在軸主本離人之前= 極性的改變。人絲5周紅晶層輪廓，而不會導縣晶層中 是在可以在沉積香農植人（第4S圖）之後、但 區接^溝_ 二^進πι層輪廓調驗人被植入到主動 些有與^層相反的極性。在某 被用來植入。該植 1二的;^ 擊穿電壓。 層輪廊而不改變蟲晶層極性，並且增強了 在盆戶ΓίίΓ進可以在沉積香農植入（圖⑹之後、但是 的爾植入以形成P=;2。？^ 為晶層中，並且盘本體=、表i型島902位於接觸溝槽之下的N型 第10圖巾所飞£斷開連接。年動的？型島也增強了擊穿電壓。 在進行香農植入(7:=二形，溝槽(第40圖)之後且 生高雷塥釦铲柄认船# H 進仃。由於尖銳的角會積累電荷、產 減少電“累並改；^使溝槽底部的角職-1嶋圓化以 儘官出於清楚的理解這一目的，在某些細節中描述了前述實施例， 101年7月20日修正替換頁 但是本發明並不限於所提供的細節。可以存在可選“:規太癸 明。所公開的實施例僅是範例的說明而不是限^的的方仏現本發 【圖式簡單說明】 ，1A-1F圖示出了若干雙擴散金屬氧化物半導體(霞)元件的實施例。 第2圖疋示出了降㈣㈤⑻轉換器電路範綱示意圖。 第3圖是示出了用於構造DMOs元件的製程的實施例的流程圖。 第4A-4U圖是具體示出了用於製造M〇s元件的範例製程的元件橫截面視 圖0 第5A-6B圖示出了製造步驟的附加可選實施例。 第7-10圖示出了製程的選擇性改進，其中這些改進在某些實施例中使 用以進一步增強元件性能。 【主要元件符號琢明】 100元件 103基底 104磊晶層 11卜113、115、117閘極溝槽 112a-112b接觸溝槽 119a-119b第二接觸開口 120a-120b第一接觸開口 121閘極氧化物層 131、133、135 閘極 131閘極流道 133、135主動閘極 140a-140d本體區 150a-150d源極區 160介電材料層 160a-160c絕緣區 170a-170d 區域 172a_172b金屬層 1378563 101年7月20日修正替換頁 180a-180b 電極 190a-190b蕭特基能障控制層 102、106、108、110 元件 200電路 201高端FET元件 202電晶體 204本體二極體 207低端FET元件 208電晶體 210本體二極體 212蕭特基二極體 214電感器 216電容器 218電阻器 400 N型基底 402 Si〇2層 404光阻層 410 Si〇2硬罩幕 420溝槽 430犧牲層 432 Si〇2層 432 440多晶矽 442閘極 444閘極的頂表面 446矽的頂層 448 Si〇2的頂表面448 450光阻層 460a-460d本體區 462氧化物層 1378563 101年7月20曰修正替換頁 464光阻層 465介電層 466未掩蔽區域 468、470 溝槽 472光阻層 474a-474b抗擊穿注入物 478金屬層 480純化層 490元件 502光阻層 504閘極溝槽 506接觸溝槽 602光阻層 604閘極溝槽 606接觸溝槽 608溝槽部分 702全面性注入 902 P型島 1002a-1002b 角1J/0J0J except for the photoresist, and a deeper, narrower trench portion 608. Move the ic diagram to show the G3 province map _ remaining steps, the secret is similar to the middle ambassador, this embodiment of the Nucor mail can be improved after the formation of the interpole (figure 4G) and ^ / Pull the mask (Figure 4K) before proceeding. Throughout the epitaxial layer, there is deposition and there is a change in polarity before the axis is left. The 5th week of the red silk layer contour of the human silk, and will not be deposited in the county layer after the deposition of Shannon implants (Fig. 4S), but the area is connected to the _ 二Actively have the opposite polarity to the layer. In some is used for implantation. The plant 1 2; ^ breakdown voltage. The layer of the porch does not change the polarity of the worm layer, and enhances the potting in the pot. It can be deposited in the deposited Shannon (Fig. 6), but implanted to form P=;2. And the disk body =, the i-type island 902 is located under the contact groove, the N-type 10th towel flies away. The annual-type island also enhances the breakdown voltage. 7:= Dimorphism, groove (Fig. 40) and the height of the Thunderbolt shovel handles the ship #H 仃. Because the sharp corners will accumulate charge, the production will reduce the electricity and “reinforce the change; ^ make the bottom of the groove The above-mentioned embodiment has been described in some detail for a clear understanding of this purpose, and the replacement page is amended on July 20, 101. However, the invention is not limited to the details provided. There may be optional ": the rules are too clear. The disclosed embodiments are merely illustrative of the examples, and are not intended to limit the scope of the present invention. [1A-1F diagram shows several double diffusions. An embodiment of a metal oxide semiconductor (Xia) device. Fig. 2 is a schematic diagram showing a descending (four) (5) (8) converter circuit. Fig. 3 is a view A flow chart of an embodiment of a process for constructing a DMOs element. 4A-4U is a cross-sectional view of an element specifically illustrating an exemplary process for fabricating an M〇s element. FIG. 5A-6B illustrates a manufacturing step. Additional Alternative Embodiments. Figures 7-10 illustrate alternative improvements in the process wherein these improvements are used in certain embodiments to further enhance component performance. [Main Component Symbols] 100 Components 103 Base 104 Lei Crystal layer 11 113, 115, 117 gate trenches 112a-112b contact trenches 119a-119b second contact opening 120a-120b first contact opening 121 gate oxide layer 131, 133, 135 gate 131 gate current Channels 133, 135 active gates 140a-140d body regions 150a-150d source regions 160 dielectric material layers 160a-160c insulating regions 170a-170d regions 172a-172b metal layers 1378563 July 20, revised address replacement page 180a-180b electrodes 190a -190b Schottky barrier control layer 102, 106, 108, 110 component 200 circuit 201 high-side FET component 202 transistor 204 body diode 207 low-side FET component 208 transistor 210 body diode 212 Schottky diode Body 214 inductor 216 capacitor 218 resistor 400 N-type substrate 402 Si〇2 layer 404 photoresist layer 410 Si〇2 hard mask 420 trench 430 sacrificial layer 432 Si〇2 layer 432 440 polysilicon 442 gate 444 gate top surface 446 矽 top layer 448 Si〇 2 top surface 448 450 photoresist layer 460a-460d body region 462 oxide layer 1378563 101 July 20 曰 modified replacement page 464 photoresist layer 465 dielectric layer 466 unmasked region 468, 470 trench 472 photoresist layer 474a - 474b anti-breakdown implant 478 metal layer 480 purification layer 490 element 502 photoresist layer 504 gate trench 506 contact trench 602 photoresist layer 604 gate trench 606 contact trench 608 trench portion 702 comprehensive implantation 902 P Island 1002a-1002b angle