1376991 0707004 26461 twf.doc/p 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種線路板的製造方法，且特別是有 關於一種可以減少製程步驟以及降低製程困難度的一種線 路板的製造方法。 【先前技術】 近年來，隨著電子技術的曰新月異，高科技電子產業 • 的相繼問世，使得更人性化、功能更佳的電子產品不斷地 推陳出新，並朝向輕、薄、短、小的趨勢設計。在這些電 子產品内通常會配置具有導電線路的線路板。 4 · 對於一般熟知的線路板製程來說，作為導線的圖案化 • I體層是絲成於載板上，而絲連接各層圖案化導體層 • 的導體孔柱（conductive via)是在壓合介電層與載板之後 才形成’因此導致了製程步輝增加而提高了生產成本，且 由於製程步驟繁雜而產生製程良率（yidd)不佳的問題。 • 此外，由於在一般的製程中，導體孔柱的形成方法是 先在覆蓋圖案化導體層的介電層中形成暴露出圖案化導體 層的開口，之後再於開口中填入導體材料。然而，在形成 上述的開口時’往往會因為欲形成的開口的深寬比（aspect ratio)過大而導致開口不易形成。 【發明内容】 4有鑑於此，本發明的目的就是在提供一種線路板的製 迨方法，其可以減少製程步驟。 本心明的另一目的就是在提供一種線路板的製造方 5 1376991 0707004 2646Itwf.doc/p 層的下部中，以及將第二圖案化導體層内埋於介電層的上 部中，且使第一導體孔柱與第二圖案化導體層連接: 依照本發明實施例所述之線路板的製造方法， 第二圖案化導體層的形成方法例如是先於第二載板上妒: 導體材料層。之後，圖案化導體材料層以成為第二圖^化 導體層。 x1376991 0707004 26461 twf.doc/p IX. Description of the Invention: [Technical Field] The present invention relates to a method of manufacturing a circuit board, and more particularly to a circuit capable of reducing a process step and reducing process difficulty The manufacturing method of the board. [Prior Art] In recent years, with the rapid development of electronic technology, the high-tech electronics industry has been launched, making more humanized and functional electronic products continue to evolve, and are light, thin, short and small. Trend design. A circuit board having conductive lines is usually disposed in these electronic products. 4 · For the well-known circuit board process, as a wire patterning, the I body layer is wire-formed on the carrier board, and the wire is connected to each layer of the patterned conductor layer. The conductor via is in the press-fit After the electric layer and the carrier are formed, it results in an increase in the process step and increases the production cost, and the process yield is poor due to the complicated process steps. • In addition, since in a general process, the conductor post is formed by first forming an opening in the dielectric layer covering the patterned conductor layer to expose the patterned conductor layer, and then filling the opening with a conductor material. However, when the above-described opening is formed, the opening tends to be difficult to form because the aspect ratio of the opening to be formed is too large. SUMMARY OF THE INVENTION In view of the above, it is an object of the present invention to provide a method of manufacturing a wiring board which can reduce the number of manufacturing steps. Another object of the present invention is to provide a circuit board in the lower portion of the manufacturing layer 5 1376991 0707004 2646Itwf.doc / p layer, and to embed the second patterned conductor layer in the upper portion of the dielectric layer, and make A conductor hole column is connected to the second patterned conductor layer: According to the method for manufacturing the circuit board according to the embodiment of the invention, the second patterned conductor layer is formed, for example, prior to the second carrier: a layer of the conductor material . Thereafter, the conductor material layer is patterned to become the second conductor layer. x
依照本發明貫施例所述之線路板的製造方法，上迷之 第二圖案化導體層的形成方法例如是先於第二載板上形‘成 圖案化膜層，此圖案化膜層暴露出部分第二載板。然後， 於圖案化膜層所暴露出的第二載板上形成第二圖案化導體 層。之後’移除圖案化膜層。 、According to the method for manufacturing a circuit board according to the embodiment of the present invention, the method for forming the second patterned conductor layer is, for example, forming a patterned film layer on the second carrier, and the patterned film layer is exposed. Part of the second carrier. A second patterned conductor layer is then formed on the second carrier exposed by the patterned film layer. The patterned film layer is then removed. ,
依照本發明實施例所述之線路板的製造方法，上述之 在壓合介電層、第一載板與第二載板之後，還可以 一載板和第二載板。 #According to the method of manufacturing a circuit board according to the embodiment of the present invention, after the dielectric layer, the first carrier, and the second carrier are laminated, a carrier and a second carrier may be further disposed. #
本發明再提出一種線路板的製造方法，此方法是先提 供第一介電層、第二介電層與第三介電層，其中第一介電 層中已形成有線路。然後，於第一載板上形成第—圖案化 導體層與第一導體孔柱，以及於第二載板上形成第二圖案 化導體層與第一導體孔柱。之後，壓合第一介電層、第二 ^電層、第二介電層、第一載板與第二載板，其中第二介 電層位於第一載板與第一介電層之間，而第三介電層位於 第二載板與第一介電層之間，使得-第一圖案化導體層與笫 一導體孔柱内埋於第二介電層中，以及使得第二圖案化導 體層與第二導體孔权内埋於第三介電層 中，且第—導體孔 7 1376991 0707004 2646 ltwf.doc/p 柱與第二導體孔柱分別與線路連接。 依照本發明實施例所述之線路板的製造方法，上述之 第二圖案化導體層與第二導體孔柱的形成方法例如是先於 第二載板上形成導體材料層》然後，圖案化導體材料層， 以形成第二導體孔柱。接著’於第二載板上形成暴露出部 分第二載板的圖案化膜層。而後’於圖案化膜層所暴露出 的第二載板上形成第二圖案化導體層。之後，移除圖案化 膜層。The present invention further provides a method of fabricating a wiring board by first providing a first dielectric layer, a second dielectric layer, and a third dielectric layer, wherein a line has been formed in the first dielectric layer. Then, a first patterned conductor layer and a first conductor via are formed on the first carrier, and a second patterned conductor layer and the first conductor via are formed on the second carrier. Thereafter, the first dielectric layer, the second electrical layer, the second dielectric layer, the first carrier and the second carrier are laminated, wherein the second dielectric layer is located between the first carrier and the first dielectric layer And the third dielectric layer is located between the second carrier and the first dielectric layer such that the first patterned conductor layer and the first conductor pillar are buried in the second dielectric layer, and the second The patterned conductor layer and the second conductor hole are buried in the third dielectric layer, and the first conductor hole 7 1376991 0707004 2646 ltwf.doc/p column and the second conductor hole column are respectively connected to the line. According to the manufacturing method of the circuit board according to the embodiment of the present invention, the method for forming the second patterned conductor layer and the second conductor hole column is, for example, forming a conductor material layer on the second carrier board, and then patterning the conductor. a layer of material to form a second conductor post. A patterned film layer exposing a portion of the second carrier is then formed on the second carrier. A second patterned conductor layer is then formed on the second carrier exposed by the patterned film layer. Thereafter, the patterned film layer is removed.
依照本發明實施例所述之線路板的製造方法，上述在 壓合第一介電層、第二介電層、第三介電層、第一載板與 第二載板之後，還可以移除第一載板和第二載板。 依照本發明實施例所述之線路板的製造方法，上述之 線路的一部分例如位於第一介電層的表面上。According to the method for manufacturing a circuit board according to the embodiment of the present invention, after the first dielectric layer, the second dielectric layer, the third dielectric layer, the first carrier and the second carrier are pressed, the method can also be moved. In addition to the first carrier and the second carrier. According to the method of manufacturing a wiring board according to an embodiment of the present invention, a part of the above-mentioned wiring is located, for example, on the surface of the first dielectric layer.
本發明在壓合載板與介電層之前先於載板上形成圖 案化導體層與導體孔柱，因此在壓合載板與介電層之後， 不需要額外進行導體孔柱製程而達到了減少線 步驟的目的，並降低了生產成本。此外，由於錢合載板 與介電層讀不需要進行導體孔柱製程，因此可以避免在 形成導體孔权的過程中’因欲形成的開寬比過大而 導致製程困難度增加。 為讓本發明之上述特徵和優職更賴易懂 舉實施例’並配合所附圖-式广作詳細說明如下。 【實施方式】 圖1Α至圖1F為依照本發明—實施例所繪示的線路板 1376991 0707004 26461 twf.doc/ρThe invention forms the patterned conductor layer and the conductor hole column on the carrier board before pressing the carrier board and the dielectric layer, so that after the carrier board and the dielectric layer are pressed, no additional conductor hole column process is required. Reduce the purpose of the line step and reduce production costs. In addition, since the carrier plate and the dielectric layer do not need to be subjected to the conductor hole column process, it is possible to avoid an increase in the process difficulty due to an excessive opening ratio formed in the process of forming the conductor hole weight. The above-described features and advantages of the present invention will be described in detail below with reference to the accompanying drawings. 1A to 1F are circuit boards according to an embodiment of the present invention. 1376991 0707004 26461 twf.doc/ρ
之製造流程剖面圖。首先，請參照圖1A，於載板1〇〇上形 成導體材料層（未繪示）。導體材料層例如為金屬層。然 後’將導體材料層圖案化，以於載板1〇〇上形成第一導體 孔柱102。特別一提的是，在本實施例中，導體材料層為 銅層，f此若載板1〇〇的材料同樣為銅時，在形成導體材 料層之^彳先於載板1〇〇上形成-層錄層。然後，將導 體材料層圖案化以形成第_導體孔柱1G2。之後，移除未 被第導體孔；I：主1〇2覆蓋的鎳層。如此一來，在將導體材 料層圖案化的過程中便不會對载板刚造成損害。此外， 上述的鎳層還可以在後續移除載板則時具有防止第 體孔柱102受損的作用。A cross-section of the manufacturing process. First, referring to Fig. 1A, a conductor material layer (not shown) is formed on the carrier board 1''. The layer of conductor material is, for example, a metal layer. The conductor material layer is then patterned to form a first conductor post 102 on the carrier 1 . In particular, in the present embodiment, the conductive material layer is a copper layer, and if the material of the carrier 1 is also copper, the layer of the conductive material is formed on the carrier 1 Forming - layer recording layer. Then, the conductor material layer is patterned to form the first conductor post 1G2. Thereafter, the nickel layer not covered by the first conductor hole; I: main 1 〇 2 is removed. As a result, the carrier plate is not damaged immediately during the patterning of the conductor material layer. In addition, the above-mentioned nickel layer can also prevent the damage of the first column 102 when the carrier is subsequently removed.
然後’請參照® 1B，於載板100上形成暴露出部分 載板⑽的圖案化膜们〇4。在本實施例中，圖案化膜層 104例如為圖案化光阻層，其形成方法例如{先於载板‘ 上形成一層光阻層，然後再進行微影製程，以形成覆蓋 -導體^主102以及部分餘卿的圖案化光阻層。 接著，請參照圖1C，於圖案化臈層1〇4所暴露 載板100上形成第一圖案化導體層108。第一圖案化 層108的材料例如為銅，其形成方法例如為電鑛法。此 在形成第-圖案化導體層觸之前，也可以先於圖案化膜 層104所暴露出的載板100上形成_層锦層。同樣地、 鎳層可以«續移除載板刚.時具有防止^ 層108受損的作用。 寻篮 而後，請參照圖1D，移除圖案化膜層1〇4，使得載板 0707004 2646 ltwf.doc/p 0707004 2646 ltwf.doc/p 102以及作為導線之用的 100上同時形成有第一導體孔柱 第一圖案化導體層108。 電声？ιΓ ΐΐ照圖1E，提供具有上部10與下部12的介 2 110。；|電層110的材料例如為介電樹脂。接著，壓 3 η電層110與載板100，以將第 , t U將第一圖案化導體層108與 弟V體孔柱102内埋於介電層11〇的下部^中。然後， 於介電層110的上部1〇巾形成暴露出部分第一導體孔柱 H的開口 112。開σ 112的形成方法例如是雷射鑽孔或機 械鑽孔。 〜之後，請參照圖1F，於介電層UG的上部1()上形成 第-圖案化導體層114 ’並於開口 112中形成第二導體孔 柱116’其中第二導體孔柱116與第一導體孔柱連接。 第二圖案化導體層114與第二導體孔柱116的形成方法例 如是先於介電層110上形成導體材料層（未繪示），且導 體材料層填滿開口 112以形成第二導體孔柱116。然後， 將位於電層110上的導體材料層圖案化，以形成第二圖 案化導體層114。或者，第二圖案化導體層114與第二導 體孔枉116的形成方法也可以是先於開口 I〗〗中形成第二 導體孔柱116，然後再於介電層11〇上形成第二圖案化導 體層114。 特別一提的是’由於在形成第二導體孔柱116之前， 第一導體孔-枉Γ02已内埋於介電層11〇中，因此位於上層…… 的第二圖案化導體層114不需藉由第二導體孔柱丨16直接 與位於下層的第一圖案化導體層108連接，而是藉由第二 1376991 0707004 26461 twf.doc/p 導體孔柱116以及與第二導體孔柱116連接的第一導體孔 柱102來與下層的第一圖案化導體層1〇8連接。也就是說， 在形成第二導體孔柱116的過程中，不需要形成暴露出第 一圖案化導體層108的開口，而是形成暴露出第一導體孔 柱102的開口，因此可以減少所形成的開口的深度，以避 免因開口的深寬比過大而增加製程困難度。 此外，在上述壓合介電層110與載板1〇〇之後，還可 以選擇性地移除載板100而僅保留内埋於介電層110 ^的 第一導體孔柱102與第一圖案化導體層108。 、 圖2A至圖2B為依照本發明另一實施例所繪示的線路 板之製造流程剖面圖。首先，請參照圖2A，提供具有上部 20與下部22的介電層200。介電層200的材料例如為介電 樹脂。此外，提供第一載板202與第二載板2〇4，並於第 一載板202上形成第一圖案化導體層2〇6與第—導體孔柱 208，以及於第二載灰204上形成第二圖案化導體層21〇。 於第一載板202上形成第一圖案化導體層206與第一導體 孔柱208的方法可與圖1A至圖10所述的方法相同，於此 不另行描述。於第二載板204上形成第二圖案化導體層21〇 的方法例如是先於第二載板204上形成導體材料層，然後 再將導體材料層圖案化，使其成為第二圖案化0導^'層 210。或者，在另一未繪示的實施例中，於第二載板204 上形成第一圖案化導體層210.的方法.也可以是先於第二載_ — 板204上形成圖案化膜層，此圖案化膜層暴露出部分第二 載板204。然後，於圖案化膜層所暴露出的第二載板2〇4 11 1376991 0707004 26461 twf. doc/p 上形成第二圖案化導體層210。之後’移除圖案化膜層。 之後，請參照圖2B，壓合介電層200、第一載板202 與第二載板204，以將第一圖案化導體層2〇6與第一導體 孔柱208内埋於介電層200的下部22中，以及將第二圖案 化導體層210内埋於介電層2〇〇的上部20中，且使第一導 體孔柱208與第二圖案化導體層21〇連接。 特別一提的是，由於在將第一圖案化導體層2〇6形成 於第一載板202上之前，先於第一載板2〇2上形成了第一 導體孔柱208，因此在壓合介電層2〇〇、第一載板2〇2與第 一載板204之後不需另外再進行導體孔枉製程，因此可以 減少線路板的製程步驟。再者，本發明先於第一載板2〇2 上形成第一導體孔柱208，可以避免後續於介電層2〇〇中 製作導體蹄咖欲形成關p的深寬比過大*增加了製 程困難度。 此外’在壓合介電層2〇〇、第一載板2〇2與第二載板 2〇4之後’同樣可以選擇性地移除第一載板2 板204。 執 圖3A至圖3B為依照本發明再一實施例所繪示的線路 ，面圖。首先’請參照圖3A，提供第一介電 層300、弟二介電層則與第三介電層3〇3。第一介 :第第二上電/ 30卜第三介電層303的材料例如為介i 知弟，1電層·300'中已形成有線路314，其中線路314 I包括多層水平的圖案化導體層及多麵直的導體孔柱。 線路3Μ的形成方法為所屬領域中具有通常知識者所熟 12 1376991 0707004 26461twf.doc/p 知，於此不另行描述。此外，提供第一載板302與第二載 板304，並於第一載板302上形成第一圖案化導體層306 與第一導體孔柱308 ’以及於第二載板304上形成第二圖 案化導體層310與弟二導體孔柱312。於第一載板302上 形成第一圖案化導體層306與第一導體孔柱308的方法以 及於第二載板304上形成第二圖案化導體層31〇與第二導 體孔柱312的方法與圖1A至圖1D所述的方法相同，於此 不另行描述。 之後’請參照圖3B，壓合第一介電層300、第二介電 層301、第三介電層303、第一載板302與第二載板304， 其中第二介電層301位於第一載板302與第一介電層300 之間，而第三介電層303位於第二載板304與第一介電層 300之間，使得第一圖案化導體層306與第一導體孔柱3〇8 内埋於第二介電層301中’以及使得第二圖案化導體層310 與第一導體孔柱312内埋於第三介電層303中，且第一導 體孔柱308與第二導體孔柱312分別與線路314連接。此 外，第一介電層300、第二介電層301、第三介電層303 經壓合後統稱為介電層3〇〇a。 特別一提的是，由於在將第一圖案化導體層306形成 於第一載板302上之前先於第一載板302上形成了第一導 體孔柱308，以及在將第二圖案化導體層31〇形成於第二 載板304 JT之前先於第二載板304上形成了第二導體孔枉· 312，因此在壓合第一介電層3〇〇、第二介電層3〇1、第三 介電層303、第一載板302與第二載板304之後不需另外 13 0707004 26461 twf.doc/p 再進仃導體孔柱製程，因此可以減少線路板的製程步驟。 ，者本發明先於載板上形成導體孔柱，可以避免後續於 "電層中製作導體孔柱時目欲形成的開口的深寬比過大而 增加了製程困難度。 一此外，在壓合第一介電層300、第二介電層301、第 一介電層303、第-載板3〇2與第二載板3〇4之後，同樣 可以選擇性地移除第一載板3〇2和第二載板。 ★另外，在本實施例中，如圖3A所示，線路314皆位 於第-介電層300中，而在另-未繪示的實施例中，線路 部分也可以是位於第—介電層的表面上。也 就疋5兒’一部分的線路314可以内埋於第一介電層300中， 而一=分的線路314·露於第一介電層絲面上。 ,紅上所述，本發明在將作為線路之用的圖案化導體層 形成於載板上之前先將形成導體孔柱形成於載板上，使^ =合载板與介電層之前載板上_形成有圖案化導體居 :、導體孔柱，ϋ此祕合與介電層之後，不需要額^ =亍導體孔柱製程，達到了減少線路板的製程 的，並降低了生產成本。 判目 ^於錢合齡與介€層之後不需要進行導體 形避免在形編孔柱的過程中，因欲 成的開口的深寬比過大而增加了製程困難度。 雖然本發明已·以實施例揭露如上_，然其^非 ίίΓ ’任何所屬技術領域中具有通常知識者，在不脫i 二明之精珅和範_，#可作些許之更動與潤飾， 本么明之保護範圍當視後附之申請專利範圍所界定者為 1376991 0707004 26461 twf.doc/p 準。 【圖式簡單說明】 圖1A至圖1F為依照本發明一實施例所繪示的線路板 之製造流程剖面圖。 圖2A至圖2B為依照本發明另一實施例所繪示的線路 板之製造流程剖面圖。 圖3A至圖3B為依照本發明再一實施例所繪示的線路 板之製造流程剖面圖。 【主要元件符號說明】 10、20 :上部 12、22 :下部 100 :載板 102、208、308 :第一導體孔柱 104 :圖案化膜層 108、206、306 :第一圖案化導體層 110、200、300a :介電層 112 :開口 114、210、310 :第二圖案化導體層 116、312 :第二導體孔柱 202、302 :第一載板 204、304 :第二載板 .30_0 :.第一介電層 ___________.....— 301 :第二介電層 303 :第三介電層 314 :線路 15Then, please refer to ® 1B to form a patterned film 〇4 on the carrier 100 that exposes a portion of the carrier (10). In this embodiment, the patterned film layer 104 is, for example, a patterned photoresist layer, and is formed by, for example, forming a photoresist layer on the carrier layer, and then performing a lithography process to form a cap-conductor. 102 and some of Yu Qing's patterned photoresist layer. Next, referring to FIG. 1C, a first patterned conductor layer 108 is formed on the carrier 100 exposed by the patterned germanium layer 1〇4. The material of the first patterned layer 108 is, for example, copper, and the formation method thereof is, for example, an electric ore method. Before the formation of the first patterned conductor layer, the layer may be formed on the carrier 100 exposed by the patterned film layer 104. Similarly, the nickel layer can be used to prevent the damage of the layer 108 when the carrier is removed. After the basket is searched, referring to FIG. 1D, the patterned film layer 1〇4 is removed, so that the carrier board 0707004 2646 ltwf.doc/p 0707004 2646 ltwf.doc/p 102 and the 100 used as the wire are simultaneously formed with the first The conductor post is first patterned conductor layer 108. Acoustic? Referring to Figure 1E, a dielectric 1110 having an upper portion 10 and a lower portion 12 is provided. The material of the electrical layer 110 is, for example, a dielectric resin. Next, the NMOS layer 110 and the carrier 100 are pressed to embed the first patterned conductor layer 108 and the V-body pillar 102 in the lower portion of the dielectric layer 11A. Then, the upper portion 1 of the dielectric layer 110 forms an opening 112 exposing a portion of the first conductor post H. The method of forming the opening σ 112 is, for example, a laser drilling or a mechanical drilling. After that, referring to FIG. 1F, a first patterned conductor layer 114' is formed on the upper portion 1() of the dielectric layer UG, and a second conductor via 116' is formed in the opening 112. The second conductor via 116 and the first conductor A conductor hole column is connected. The second patterned conductive layer 114 and the second conductive via 116 are formed by, for example, forming a conductive material layer (not shown) on the dielectric layer 110, and the conductive material layer fills the opening 112 to form a second conductive via. Column 116. The layer of conductor material on the electrical layer 110 is then patterned to form a second patterned conductor layer 114. Alternatively, the second patterned conductive layer 114 and the second conductive via 116 may be formed by forming a second conductor via 116 before the opening, and then forming a second pattern on the dielectric layer 11 Conductor layer 114. In particular, since the first conductor hole-枉Γ02 is buried in the dielectric layer 11〇 before the second conductor post 116 is formed, the second patterned conductor layer 114 located in the upper layer... does not need to be The first conductor via 丨 16 is directly connected to the first patterned conductor layer 108 located on the lower layer, but is connected to the second conductor via 116 by the second 1 371 991 0707004 26461 twf.doc/p conductor post 116 . The first conductor post 102 is connected to the underlying first patterned conductor layer 1A8. That is, in the process of forming the second conductor via 116, it is not necessary to form an opening exposing the first patterned conductor layer 108, but an opening exposing the first conductor via 102 is formed, thereby reducing formation The depth of the opening is to avoid increasing the difficulty of the process due to the excessive aspect ratio of the opening. In addition, after the pressing of the dielectric layer 110 and the carrier 1 , the carrier 100 can be selectively removed to retain only the first conductor via 102 and the first pattern buried in the dielectric layer 110 ^. Conductor layer 108. 2A-2B are cross-sectional views showing a manufacturing process of a circuit board according to another embodiment of the present invention. First, referring to Figure 2A, a dielectric layer 200 having an upper portion 20 and a lower portion 22 is provided. The material of the dielectric layer 200 is, for example, a dielectric resin. In addition, a first carrier 202 and a second carrier 2〇4 are provided, and a first patterned conductor layer 2〇6 and a first conductor pillar 208 are formed on the first carrier 202, and a second carrier 204 is formed. A second patterned conductor layer 21 is formed thereon. The method of forming the first patterned conductor layer 206 and the first conductor via 208 on the first carrier 202 may be the same as that described in FIGS. 1A-10, and will not be described herein. The method of forming the second patterned conductor layer 21 on the second carrier 204 is, for example, forming a layer of the conductor material on the second carrier 204, and then patterning the layer of the conductor material to make the second pattern 0. Guide layer 210. Alternatively, in another embodiment, not shown, the first patterned conductor layer 210 is formed on the second carrier 204. The patterned layer may be formed on the second carrier 204. The patterned film layer exposes a portion of the second carrier 204. Then, a second patterned conductor layer 210 is formed on the second carrier 2 〇 4 11 1376991 0707004 26461 twf. doc/p exposed by the patterned film layer. The patterned film layer is then removed. Thereafter, referring to FIG. 2B, the dielectric layer 200, the first carrier 202 and the second carrier 204 are laminated to embed the first patterned conductor layer 2〇6 and the first conductor post 208 in the dielectric layer. In the lower portion 22 of the 200, the second patterned conductor layer 210 is buried in the upper portion 20 of the dielectric layer 2, and the first conductor via 208 is connected to the second patterned conductor layer 21A. In particular, since the first conductor post 208 is formed on the first carrier 2〇2 before the first patterned conductor layer 2〇6 is formed on the first carrier 202, the pressure is applied. After the dielectric layer 2〇〇, the first carrier 2〇2 and the first carrier 204, the conductor hole process is not required, so that the process steps of the circuit board can be reduced. Furthermore, the present invention forms the first conductor post 208 on the first carrier 2〇2, so as to avoid the subsequent formation of the conductor hoist in the dielectric layer 2, and the aspect ratio is too large* increased. Process difficulty. Further, the first carrier 2 plate 204 can be selectively removed after pressing the dielectric layer 2, the first carrier 2〇2 and the second carrier 2〇4. 3A to 3B are circuit and plan views according to still another embodiment of the present invention. First, please refer to FIG. 3A to provide a first dielectric layer 300, a second dielectric layer, and a third dielectric layer 3〇3. First, the material of the second power-on/30b third dielectric layer 303 is, for example, a well-known brother, and a circuit 314 has been formed in the first electrical layer 300', wherein the line 314I includes multiple levels of patterning. Conductor layer and multi-sided straight conductor hole column. The method of forming the line 3Μ is known to those of ordinary skill in the art, and is not described here. In addition, a first carrier 302 and a second carrier 304 are provided, and a first patterned conductor layer 306 and a first conductor post 308 ' are formed on the first carrier 302 and a second is formed on the second carrier 304. The patterned conductor layer 310 and the second conductor post 312 are patterned. Method for forming first patterned conductor layer 306 and first conductor via 308 on first carrier 302 and method of forming second patterned conductor layer 31 〇 and second conductor via 312 on second carrier 304 The method is the same as that described in FIGS. 1A to 1D and will not be described here. Then, referring to FIG. 3B, the first dielectric layer 300, the second dielectric layer 301, the third dielectric layer 303, the first carrier 302 and the second carrier 304 are laminated, wherein the second dielectric layer 301 is located. The first carrier 302 is between the first dielectric layer 300 and the third dielectric layer 303 is between the second carrier 304 and the first dielectric layer 300 such that the first patterned conductor layer 306 and the first conductor The via 3 〇 8 is buried in the second dielectric layer 301 ′ and the second patterned conductive layer 310 and the first conductive via 312 are buried in the third dielectric layer 303 , and the first conductive via 308 The second conductor post 312 is connected to the line 314, respectively. In addition, the first dielectric layer 300, the second dielectric layer 301, and the third dielectric layer 303 are collectively referred to as a dielectric layer 3〇〇a after being pressed. In particular, since the first conductor post 308 is formed on the first carrier 302 before the first patterned conductor layer 306 is formed on the first carrier 302, and the second patterned conductor is Before the layer 31 is formed on the second carrier 304 JT, the second conductor hole 312 is formed on the second carrier 304, so that the first dielectric layer 3 and the second dielectric layer 3 are pressed together. 1. The third dielectric layer 303, the first carrier 302 and the second carrier 304 do not need another 13 0707004 26461 twf.doc/p to enter the conductor post process, thereby reducing the process steps of the board. According to the invention, the conductor hole column is formed on the carrier board, which can avoid the excessively large aspect ratio of the opening which is formed when the conductor hole column is formed in the electric layer, and the process difficulty is increased. In addition, after the first dielectric layer 300, the second dielectric layer 301, the first dielectric layer 303, the first carrier 3〇2 and the second carrier 3〇4 are pressed, the same can be selectively moved. In addition to the first carrier 3〇2 and the second carrier. In addition, in this embodiment, as shown in FIG. 3A, the line 314 is located in the first dielectric layer 300, and in another embodiment not shown, the line portion may also be located in the first dielectric layer. on the surface. Also, a portion of the line 314 may be buried in the first dielectric layer 300, and a one-minute line 314 is exposed on the first dielectric layer. According to the present invention, the present invention forms a conductor post on the carrier before forming the patterned conductor layer for the circuit on the carrier, so that the carrier board and the dielectric layer are preceded by the carrier. The upper _ is formed with a patterned conductor: the conductor hole column, and after the secret and the dielectric layer, the method of reducing the number of the conductor hole column is not required, thereby reducing the manufacturing process of the circuit board and reducing the production cost. It is not necessary to carry out the conductor shape after the combination of the money and the layer. In the process of shaping the hole column, the process difficulty is increased because the depth-to-width ratio of the desired opening is too large. Although the present invention has been disclosed above by way of example, it is not ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ The scope of protection of Ming is defined as the number of patent applications attached to the attached patent is 1376991 0707004 26461 twf.doc/p. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A to FIG. 1F are cross-sectional views showing a manufacturing process of a circuit board according to an embodiment of the invention. 2A-2B are cross-sectional views showing a manufacturing process of a circuit board according to another embodiment of the present invention. 3A-3B are cross-sectional views showing a manufacturing process of a circuit board according to still another embodiment of the present invention. [Main component symbol description] 10, 20: upper portion 12, 22: lower portion 100: carrier plates 102, 208, 308: first conductor hole column 104: patterned film layer 108, 206, 306: first patterned conductor layer 110 200, 300a: dielectric layer 112: openings 114, 210, 310: second patterned conductor layers 116, 312: second conductor holes 202, 302: first carrier 204, 304: second carrier. 30_0 :. First dielectric layer ___________..... 301: second dielectric layer 303: third dielectric layer 314: line 15