TWI376695B - - Google Patents

Description

Application No. 9710163⁄4 1〇16 27 Correction Replacement-^---- IX. Description of the Invention: [Technical Field of the Invention] Field of the Invention The present invention relates to a sensation in a memory unit by means of two or more values Data semiconductor memory device, semiconductor control device and semiconductor control method

[Prior Art: J Background of the Invention In recent years, memory devices composed of non-volatile memory such as a USB memory, a flash memory card, and a flash memory have been widely used. Further, in order to increase the capacity of the memory devices, it is known to increase the voltage threshold of each memory cell as shown in FIG. 28, for example, in the case of a 4-value memory cell, A multi-valued technique in which each of the two-bit data of "11", "1", "01", "〇〇", and the like corresponds to a voltage reference value, and a value of three or more is stored in one memory memory unit. Further, the prior art related to the present invention is known as a non-volatile semiconductor memory device and a data memory system which are large-capacity, highly reliable, and fast-acting (for example, refer to Patent Document 1). [Document 1] Japanese Laid-Open Patent Publication No. 2-21-82 [There is a problem to be solved by the present invention. However, a multi-value memory device that achieves a large capacity by multi-value technology has reliability. Low-level problems. In the following, the problem of multi-valued 1376695, application No. 97101636, 101.6.27, correction and replacement technology is explained by using the 29th to the 3rd drawings. Figure 29 shows the 2-value memory memory unit and 4 Value memory memory cell margin Figure 30 shows a diagram showing the relationship between the memory cell distribution and the threshold value of the 2-value type memory cell; and Figure 31 shows the relationship between the memory cell distribution and the threshold value of the 4-value type memory memory. Show.

As shown in Fig. 29, since the binary-type memory cell has sufficient margins for determining the voltage threshold values of "0" and "1", the possibility of data inversion is low, and high reliability can be realized. On the other hand, in the 4-value type memory cell, since it is determined that the voltage threshold values of "00", "01", "10", and "11" do not have sufficient 10 margins, the possibility of data inversion is high, and Low reliability.

Specifically, in the case of the binary-type memory cell as shown in FIG. 30, in the threshold values Ref-1, Ref-2, and Ref-3, Ref-2 is used as the threshold value, and if the voltage is lower than Ref -2, if the voltage is level-0 or level-1, the data is judged as "1"; if the voltage is higher than Ref-2, even if it is level-2 or level-3, the material is judged It is "0". On the other hand, in the case of the 4-value type memory cell as shown in FIG. 31, if the voltage is lower than Ref-Ι, the data is judged as "11"; if the voltage is higher than Ref-Ι and lower than Ref-2 , the data is judged as "10"; if the voltage is higher than Ref-2 and lower than Ref-3, the data is judged as "01"; if the voltage is higher than Ref-3, the data is judged as "00". Therefore, for a 2-value type memory cell, the voltage of 20 is level-0 or level-1, and is not judged to be the same data. For example, a voltage of level -1 is applied to the memory cell of the data written with "11", and the data of the memory cell is judged to be "10" at the time of reading. Further, Ref-2 and Ref-3 as shown in Fig. 30 are diagrams for comparing 4-value type memory cells; in the 2-value type memory cell, only Ref-2 actually exists as a threshold value. 6 1376695 Application No. 97101636 101.6.27 Correction and Replacement As described above, the multi-value type memory device has low reliability in memory having a large capacity. However, since it is desired to increase the capacity of data used by images and images to obtain a memory device of a larger capacity, it is necessary to realize a memory device of high reliability and large capacity. The present invention is directed to solving the above problems, and aims to provide a semiconductor memory device, a control device, and a control method thereof that can store data in two or more values in accordance with management information.

In order to solve the above problems, the semiconductor memory device of the present invention comprises: a plurality of memory cells, which are memory data; and a threshold value determining unit, which is respectively written into the foregoing complex memory according to predetermined management information for managing information of the data. The value of the unit is determined to be two or more values, and the threshold value is determined according to the value determined to be written into the complex memory unit, respectively; and the writing unit is based on the threshold value determined by the threshold value determining unit. The data is written to the aforementioned plural memory unit. Further, the control device of the present invention is a device for controlling a semiconductor memory device composed of a plurality of memory cells capable of memorizing data, and the control device includes: a threshold value determining portion based on information for managing data. Predetermining the management information, determining the value of each of the plurality of memory units to be a value of 2 or more, and determining the threshold according to the value determined to be written into the complex memory unit 20; and the writing unit is based on The threshold value determined by the threshold value determining unit writes the data into the complex memory unit. Moreover, the control method of the present invention is a method for controlling a semiconductor memory device composed of a plurality of memory cells capable of memorizing data, and the control method performs the following steps: a threshold value determining step, which is based on management of funds 7 1376695 In the application No. 97101636, ι〇ι·6·27, the predetermined management information for correcting the information of the replacement materials is to be respectively written into the above-mentioned complex memory unit, and the value is determined to be 2 or more values, and the above-mentioned plural number is written according to the determined decision. The value of the delta memory unit determines the gate weight value: and the writing step is based on the threshold value determined by the threshold value determining step, and the foregoing data is written into the complex fifth memory unit. BRIEF DESCRIPTION OF THE DRAWINGS [Fig. 1] is a diagram showing an information processing apparatus in the first embodiment. Fig. 2 is a view showing the hardware structure of the information processing device in the first embodiment. 10 [Fig. 3] shows a block diagram of the NAND flash memory structure in the implementation type 1. [Fig. 4] is a block diagram showing the control ic structure. [Fig. 5] shows a circuit diagram of a plurality of memory cells constituting a NAND flash array. [Fig. 6] shows the circuit diagram of the sense amplifier/comparator circuit. [Fig. 7] shows the circuit diagram of the sense amplifier/comparator circuit. [Fig. 8] shows the data structure diagram stored in the NAND flash array. [Fig. 9] is a diagram showing the setting table. [Fig. 10] shows the flow of the operation of the file system recognition processing. Fig. 11 is a flow chart showing the operation of the write processing in the embodiment 1. [Fig. 12] shows the flow of the action of the attribute information recognition processing. 8 1376695 _ No. 97101636 application 101.6.27 correction replacement. 5 • Figure. [Fig. 13] is a flowchart showing the operation of the switching process. [Fig. 14] is a flow chart showing the operation of performing the conversion processing when the power is turned on. [Fig. 15] is a flow chart showing the operation of performing the conversion processing at the time of the shutdown. [Fig. 16] is a flowchart showing an operation of performing conversion processing when there is no instruction at a predetermined time. [Fig. 17] is a flowchart showing the operation of the conversion processing. 10 [Fig. 18] is a flow chart showing the operation of the rewriting process. [Fig. 19] A flow chart showing the operation of the subdirectory view processing. [Fig. 20] is a flowchart showing an operation of separately transmitting a 2-valued and multi-valued usage amount. [Fig. 21] is a flow chart showing the operation of converting the 2-value usage amount into the multi-value usage amount and 15 processing to the host. • [Fig. 22] is a flow chart showing the operation of the space capacity calculation processing. [Fig. 23] is a flow chart showing an action of processing a data reply error larger than the space capacity. 20 [Fig. 24] A flow chart showing the operation of the threshold value correction processing. Fig. 25 is a flow chart showing the operation of the write processing in the embodiment 2. [Fig. 26] is a flow chart showing the operation of the write processing in the embodiment 3. 9 1376695 Application No. 97101636 101.6.27 Correction Replacement [FIG. 27] A flow chart showing the operation of the write processing in the embodiment 4. [Fig. 28] shows the bit maps stored in the 2-value type memory unit, the 4-value type memory unit, and the 8-value type memory unit. 5 [Fig. 29] shows a graph showing the margins of the 2-value type memory unit and the 4-value type memory unit. [Fig. 30] is a graphical representation showing the relationship between the distribution of memory cells and the threshold value of a 2-value type memory cell.

[Fig. 31] is a graphical representation showing the relationship between the memory cell distribution of a 4-value type memory cell and the 10-threshold value. C. Embodiment 3 Detailed Description of Preferred Embodiments An embodiment of the present invention will be described with reference to the following drawings. Embodiment 1 15 First, an information processing apparatus of this embodiment will be described with reference to the drawings.

Fig. 1 is a view showing an information processing apparatus of the present embodiment; and Fig. 2 is a view showing a hardware structure of the information processing apparatus in the present embodiment. As shown in Fig. 1, the information processing device 1 of the present embodiment is a personal computer in which a NAND flash memory 10 is mounted as an auxiliary memory device. Further, as shown in Fig. 2, the information processing device 1 includes a memory 14 of the main memory device and a CPU 13 of the central calculation device. Further, the information processing device 1 includes a chip set 11 (Northbridge) capable of high-speed information communication and control between the CPU 13 and the memory 14, and a BIOS 19 for storing programs for controlling the minimum standard input and output of peripheral devices. group. 10 1376695 Application No. 97101636 1〇1_6_27 Correction and replacement In addition to the above, the information processing apparatus 1 also includes a wafer set 12 (South Bridge wafer), which is a low-speed peripheral machine compared to the CPU 13 and the memory 14. Information communication and control; audio board 17 for controlling audio output; USB/PCI interface 18 for connecting USB devices or PCI bus to 5 machines; LAN interface 16 for connection to network boards To communicate with the outside; and NAND flash memory 1 〇. Further, the NAND flash memory 10 includes: a non-volatile NAND flash array 1〇1; and a control IC 20 for controlling the nand flash memory. Further, the information processing device is not limited to a personal computer, and may be, for example, a mobile phone or a PDA that requires a memory device. 10 Next, the NAND flash memory of this embodiment will be described. Fig. 3 is a block diagram showing the construction of the NAND flash memory of this embodiment. The NAND flash memory includes: Nand flash array 1 (complex memory unit, semiconductor memory device), χ_decoder 1 〇 2, γ•decoder 103, sense amplifier/comparator circuit 104 , address register/counter 1〇5, 15 instruction register 106, input output buffer 1〇7, control 1 (: 2〇 (control device, gate value determination unit, detection unit, threshold value) The conversion unit, the door value correction unit, and the writing unit. nand (four) array is a non-volatile memory composed of a plurality of memory units. Further, the X·decoder (10) is used to construct the _ 〇 20 20 The selection of the direction of the plurality of memory cells in the inter-array 101 and the two-dimensional arrangement. Further, the γ-decoding II 103 is used to select the direction of the column of the plurality of memory cells. Further, the sense amplifier/comparator circuit 104 is based on the predetermined The gate pinch value converts the input voltage into digital information. In addition, the address register/counter 105 specifies the address when accessing the NAND flash array 1〇1. Further, 11 1376695 Application No. 97101636 Case 101.6.27 amends the replacement instruction register 106 to maintain In addition, the input/output buffer 107 is used for temporarily memorizing the data in the data processing device as the host and the data in the address input and output process. In addition, the control IC 20 is used to control the NAND fast. Flash memory 1 〇 5 In addition, the instruction register 106 and the control IC 20 receive the command lock performance signal, the address lock performance signal, the chip enable signal, the read performance signal, the write performance signal, and the write protection from the host. The signal is used as the output input control signal 'and the combination of these signals is used as the command. Further, the control IC 20' is used to output the ready, busy, and error signals. 10 Next, the control of the fourth figure shows the control ic structure. The control IC 20 includes a host interface unit 2, a control register 202, a buffer 203, an ECC unit 204, a NAND interface unit 205, a microprocessor 206, a ROM 207, and a RAM 208. Further, the host interface unit 2 (H ' is used to send the host and command 15 and the receiver. Also 'control register 202 is used to maintain various parameters. Also, NAND interface 205 is used to perform NAND flash array 101 and command sending and receiving. Further, buffer 203 is used to temporarily maintain the command and borrowed from NAND flash array 1〇1 by NAND interface unit 205. The field of instructions received by the host interface unit from the host. In addition, the 2〇ECC unit 204' is used to generate ECC when the data is written, and detects the error of the data and corrects it according to the ECC when the data is read. The microprocessor 206 is used to control the control IC 20. As a whole, the ROM 207 is a firmware that stores the microprocessor 206 for processing. Further, the RAM 208 is a memory used by the microprocessor 206. 12 1376695 Application No. 97101636 101.6.27 Amendment 5. 5 Next, the complex memory cells and sense amplifier/comparator circuits that make up the NAND flash array will be described. Figure 5 is a circuit diagram showing a plurality of memory cells constituting a N A N D flash array. Further, Fig. 6 and Fig. 7 show circuit diagrams of the sense amplifier/comparator circuit. As shown in Fig. 5, the NAND flash array 101 applies a positive voltage to the control gate by the bit line and the source line, and then stores the data by electronic storage on the floating gate. Further, since the bit line and the source line are connected in units of a plurality of memory cells, the NAND flash array 101 writes data in units of memory cells composed of a plurality of memory cells. 10 * Also, as shown in Fig. 6, the sense amplifier/comparator circuit 104 connected to the memory unit is configured to compare the voltages of the input gate weights (Ref-1 to Ref-3), and output the result. The sense amplifiers 104a to 104c are configured by a comparator circuit 104d that compares the output results of the sense amplifiers 104a to 104c and converts them into digital data. Moreover, the comparator circuit 104d can switch between the value of 2 or 4 by the MLC signal sent by the control IC 20 15; as shown in FIG. 30, when the MLC signal is not received, the output is "1" when the voltage is lower than Ref-2. "When the voltage is higher than Ref-2, it outputs "0", but the ideal voltage is higher than the voltage of Ref-3 or lower than Ref-Ι. In the case of 2 values, the above is applied. At voltage, the comparator circuit uses Ref-2 as the threshold value to output the data, but it is regarded as memory • 20 unit degradation, and the control IC20 returns an error. Again, as shown in Figure 31, in the comparator loop l〇4d In the case where the MLC signal has been received, the voltage is lower than Ref-Ι and the output is "11"; if the voltage is higher than Ref-1 and lower than Ref-2, the output is "10"; the voltage is higher than Ref-2 and lower than Ref- 3, the output "0 Γ; the voltage is higher than Ref-3, then the output "〇〇". 13 1376695 ___- "" Application No. 97101636 101.6.27 correction replacement and 'as shown in Figure 7, in the sense When the amplifier/comparator circuit 104 receives only the MLC signal, it can also be made to be input in the sense amplifier 104a and the sense amplifier 104c. Next, the structure of the data stored in the NAND flash array will be described. Fig. 8 is a diagram showing the structure of the data stored in the NAND flash array. As shown in Fig. 8, the NAND flash memory The information read and written in 10 is stored in the data field in the form of a fan unit, and stores the redundant data corresponding to the fan type in the lengthy field. Further, the fan type A to D respectively correspond to the foregoing. The sector unit formed by the spare A'~D' of the fan type deletes the 10 materials. In addition, the 'single type spare writes are: LSN (logical sector number) for displaying the corresponding type number; DV (data validity) of the data for validity check; BBI (bad block message table) for displaying the unrecordable data due to deterioration of the memory unit; ECC of the sector error correction symbol (data block) Used error correction code); alternate error correction symbol 15 ECCS (error correction code for alternate clamp); MLC flag (multi-layer memory unit flag) used to display the flag of data stored in 4 values; Display in the fan type The number of times WF (write frequency); and the EJ used to display the fan type that the error is returned from the sense amplifier/comparator circuit 104. The other 'MLC flag is set to γ*Ν, and the γ display saves the fan type with 4 values. , 20 Ν display saves the fan type with 2 values. Also, m is set to 〇 or 】, 〇 shows that there is no problem with the fan type in the fan type; 1 shows that there is a problem with the fan type in the fan type, and the initial state is 0 ^ 'Describe the setting table of the NAND flash array. Figure 9 shows the illustration of the setting table. 14 1376695 Application No. 97101636 101.6.27 Correction Replacement The NAND flash array 1〇1 stores a setting table as shown in Fig. 9. The setting table correspondingly stores the attribute information and the writing mode according to the NAND flash array 101 file system. This write mode is set to SLC (single layer memory cell) stored in binary value or MLC (multilayer memory cell) stored in 4 values. Further, the setting table ’ is only applicable to the case where the material attribute is archived, and the data is stored in the NAND flash array 1〇1 at a value of four.

The other setting table is a file system corresponding to FAT16, but can also be prepared with respect to various file systems. Also, the setting table can be stored in the ROM 207 of the control IC 20. 10 Next, the operation of the NAND flash memory in the present embodiment will be described. In order to identify the attribute information of the data, the microprocessor 206 of the control IC 20 first identifies the file system of the NAND flash array. The second diagram shows a flow chart of the actions of the file system recognition process. First, the microprocessor 206 reads the 5th byte of the partition table (S101), and 15 determines whether the 5th byte is 01h (S102), and the partition table 5th byte is from the NAND flash array 101, in the NAND The interface unit 205 displays information on the type of the file system. In the case where the 5tb byte is not Olh (S102, NO), the microprocessor 206 determines whether the 5th byte is 04h (S103). 2〇 In the case where the 5th byte is not 04h (S103, NO), the microprocessor 206 determines whether the 5th byte is 06h (S104). In the case where the 5th byte is not 06h (S104, NO), the microprocessor 206 determines whether the 5th byte is 07h (S105). In the case where the 5th byte is not 07h (S105, NO), the microprocessor 206 15 1376695 _ 97101636 application 101.6.27 correction replacement determines whether the 5th byte is 〇Ch (S 106). In the case where the 5tb byte is not 〇Ch (S106, NO), the microprocessor 206 ends the processing. On the other hand, in the case where the triad is OCh (S106, YES), the micro 5 processor 206 reads the FAT-based setting table from the NAND flash array 101 as the judgment attribute information. Set the table and store it in RAM (S111).

Further, in the case of the determination in step S105, when the 5 <!* byte is 07h (S105, YES), the microprocessor 206 reads the setting table of 10 NTFS from the NAND flash array 101. As a setting table for judging the attribute information of the file, it is stored in the RAM (S110). Further, in the case of the determination in step S104, in the case where the 5-bit byte is 〇6h (S104, YES), the microprocessor 206 reads from the NAND flash array 1〇1 with FAT16 (32 MB to 2 GB) as a standard. The setting table is used as a setting table for judging the file attribute 15 information, and is stored in the RAM (S109).

Further, in the case of the determination in step S103, when the 5111 byte is 〇4h (S103, YES), the microprocessor 206 reads the setting of FAT16 (~32MB) from the NAND flash array 1〇1. The table 'is used as a setting table for judging file attribute information' and is stored in the RAM (S108). Further, in the judgment of step S102, 5 (|1 byte is 〇卟 (S102, YES), and the microprocessor 206 is NAND flash array (7)! The FAT12 is set as the standard setting table. , as a setting table for judging the property information of the building, and stored in the RAM (S107). By the above action, the microprocessor 206 can recognize the naND flash array 16 1376695 Application No. 97101636 101.6.27 Correction replacement column The file system of 101, and the setting table corresponding to the file system can be set to RAM. In addition, the above file system is one example, and the corresponding control IC 20 can be preset according to the OS and environment stored in the NAND flash memory 10. File system. In this embodiment, the file system of the NAND flash array 1〇1 is set to FAT16 (32MB~2GB).

With the above operation, in the case where the write command for instructing the data write is sent from the host to the NAND flash memory 1A of the appropriate file system, the microprocessor 206 performs the write described below. deal with. Figure 11 shows a flow chart of the actions that are not written into the process. First, the microprocessor 206 receives a write command from the host through the host interface unit 201 (S201), and then refers to the LSN of the sector number (S202), and determines whether the LSN is the number of the display root directory field (S203). When the LSN is the display root directory number (S203, YES), the microprocessor 206 executes attribute information recognition processing (S204, threshold value step) described later, and judges that the attribute information in the setting table is set to The attribute of 4 values, that is, whether or not it is an archive (S205, threshold value decision step). In the case where the attribute information is archived (S205, YES), the microprocessor 206 transmits the data already stored in the input/output buffer 107 to the NAND flash array 101 by the NAND interface unit 205 (S206, The write step 2 further sets the spare MLC flag of the fan-type redundant data that has been written to the NAND flash array 101 to the data to be Y (S207), and stores the directory data already stored in the input wheel-out buffer 107. It is saved in the NAND flash array l〇1 (S2〇8). In addition, in the judgment of step S205, the attribute information is not archived. 17 1376695 ____ 97101636 application 101.6.27 correction replacement (S205, NO) The microprocessor 206 saves the data already stored in the input/output buffer to the NAND flash array 10US211 through the NAND interface unit 205', writes the data to the NAND flash array 101, and writes the data to the NAND flash array 101. The data MLC flag is set to N (S212), and the directory data stored in the input/output buffer 107 is stored in the NAND flash array 101 (S208).

Further, in the determination of step S203, the LSN is not in the case of displaying the number of the directory material field (S203, NO) 'The microprocessor 206 refers to the data stored in the input/output buffer 107 12<!1 The 5th bit of the byte is 10 (S209), and it is judged whether or not the 5th bit of the triad is 1 (S210). In the case where the 5tb bit of the 121|1 byte is 1 (S21, YES), the microprocessor 206 executes attribute information identifying processing (S204) which will be described later. On the other hand, in the case where the 51|1 bit of the 12th mountain block is not 1 (S210, NO), the microprocessor 206 is transmitted through the NAND interface unit 205.

15 data stored in the input and output buffers is stored in NAND at 2 values.

The flash array 101 (S211, writing step) 'sets the data MLC flag that has been written to the NAND flash array 101 to n (S212), and saves the directory data already stored in the input/output buffer 107 in Nand. Flash array 101 (S208). 20 Next, the attribute information recognition processing of the processing of the step S2〇4 in the eleventh embodiment will be described. Fig. 12 is a flowchart showing the operation of the attribute information recognizing processing. In addition, in Fig. 12, the control IC is regarded as an instruction that has received a write and the data is stored in the input/output buffer. First, the microprocessor 2〇6 refers to the 12tb byte (S3〇1) which is stored in the output input buffer ι〇7 18 1376695, No. 97101636, application 101.6.27, and replaces the directory data of the replacement, and judges the 12tb bit. Whether or not the bit of the tuple is 1 (S302). In the case where 1 "bit is not 1 (S302, NO), the microprocessor 206 determines whether the 2nd bit of the 121|> byte is丨(S3〇3) β 5 In the case where the element is not 1 (S303, NO), the microprocessor 206 determines whether the 3rd bit of the 12th byte is "5304". The 3^* bit is not In the case of 1 (S304, NO), the microprocessor 206 determines whether or not the 4th bit of the triad is HS305). In the case where the 4^ bit is not 1 (S305, NO), the microprocessor The 206 system judges 10 breaks and 12, and whether the 5th bit of the triad is "^06". In the case where the 5^ bit is not 1 (S3〇6, n〇), the microprocessor 206 judges whether the 6th bit of the triad is 丨(7)川? ). In the case where the 6^ bit is not 1 (S3〇7, n〇), the microprocessor 206 ends the attribute information recognition processing. On the other hand, in the case where the 6th bit is 1 (S307, YES), the microprocessor 206 regards the attribute information as an archive (S313). Further, in the case of the determination in step S306, when the 5th bit is 1 (S306, YES), the microprocessor 206 regards the attribute information as direct (S312). Further, in the determination of step S305, in the case where the 4th bit is 1 (S305, YES), the microprocessor 206 regards the attribute information as the standard volume (S311). Further, in the case where the 3fd bit is 1 in the judgment of step S304 (S304, YES), the microprocessor 206 regards the attribute information as hidden (S310). Further, in the case of the determination in step S303, when the 2nd bit is 1 (S303, YES), the microprocessor 206 regards the attribute information as the system (S309). 19 1376695 Application No. 97101636 101.6.27 Correction and replacement 'In the case of the judgment of step S302, in the case where the bit is 1 (S302, YES) 'The microprocessor 2〇6 regards the attribute information as only readable. (S308). As described above, by storing the poor material at a value of 2 or 4 based on the attribute information set in advance, it is possible to store, for example, a data requiring high-value data such as system data, and can save the value of 4 values, for example, using The data of the person does not require the information of the reliability, so that high reliability and large capacity can be achieved at the same time. In addition, depending on the importance of the data, the method of saving in stages of 2, 4, and 8 values can be switched. 10 Next, the switching process of reading the data _ 2 value and the 4 value stored in the NAND flash array by 2 or 4 values will be described. Fig. 13 is a flow chart showing the operation of the switching process. First, the host interface unit 2〇1 receives the read command from the host (S4〇i), the microprocessor 206 reads through the NAND interface unit 205, and the reference memory 15 is stored in the NAND flash specified by the read command. The data of the array MLC flag (S402) is used to determine whether the MLC flag value is y (S4 〇 3). In the case where the MLC flag value is Y (S4〇3, YES), the microprocessor 206 transmits the MLC signal to the sense amplifier/comparator circuit 104 through the NAND interface unit 205 (S404). On the other hand, in the case where the MLC flag value is not Y (S403, NO), the microprocessor 206 ends the processing. As described above, the microprocessor 206 is a method of saving the reference MLC flag determination data, and as described in FIGS. 6 and 7, in the case of a 4-value, by transmitting the MLC signal to the sense amplifier / Comparator loop 1 〇 4 to switch 20 1376695 ___ Application No. 97101636 101.6.27 correction replaces 2 and 4 values. Further, the read data is transmitted to the host through the input/output buffer 107. Next, with reference to Fig. 14 to Fig. 19, a description will be given of a conversion process in which data to be written in two values is converted into four values. Figure 14 shows the flow chart when the conversion is performed when the power is turned on. First, the information processing device 1 is powered on, the control IC 20 is reset (S501), and the microprocessor 206 of the control 1C is reset to generate a logical and physical mapping table (S502), and a conversion process (S503) to be described later is executed. ® Figure 15 is a flow chart showing the actions 10 of the conversion process during the downtime. First, the microprocessor 206 reads the status register (S601)' and judges whether or not the display status register is the value of the shutdown status RDY (S602). When the status register is RDY (S602, YES), the microprocessor 206 performs a conversion process (S603) which will be described later. On the other hand, in the case where the status register is not RDY (S602, NO), the φ microprocessor 206 ends the processing. In the present embodiment, the value of the status register can be obtained from the status register of the CPU in the information processing device 1, or can be obtained from the status register of the microprocessor 206. • Fig. 16 shows a flow chart of the actions performed when the conversion is not performed at the predetermined time. First, the microprocessor 206 reads the status register (S7〇1) and determines whether the status register is RDY (S702). In the case where the state register is RDY (S7〇2, YES), the microprocessor 206 starts the timer and stands by for a predetermined time (S7〇3), and judges the state temporary storage 21 1376695, application No. 97101636, 101.6. 27 Whether the corrector is RDY (S704). In the case where the status register is RDY (S704, YES), the microprocessor 206 performs conversion processing (S7〇5). On the other hand, in the case where the status register is not RDY (S704, NO), the microprocessor 206 ends the processing. Further, in the judgment of step S702, in a case where the state register is not RDY (S702, NO), the microprocessor 206 ends the processing.

As shown in Figs. 14 to 15, the microprocessor 206 performs conversion processing with a predetermined condition as a trigger. Fig. 17 is a flow chart showing the operation of the conversion processing in the process of step S603, step 15 of Fig. 15, step S705, and the like in Fig. 14 in Fig. 14. First, the microprocessor 206 reads a 32-bit tuple from the root directory field of the NAND flash array 101 (S801), and judges whether the Ist byte of the read 32-bit tuple is 〇〇h or E5h ( S802). In the case where 1 "byte is 00h or E5h (S802, YES), the microprocessor 206 determines whether the 32-bit read is the end of the root directory field (S803). 32-bit tuple In the case of the end of the root directory field (S803, YES), the microprocessor 206 ends the processing. On the other hand, the 32-bit byte read is not the end of the root directory field (S803, NO). The microprocessor 206 supplements the 32-bit tuple with the current index as a reading index (S807), and then reads the 32-bit tuple from the root directory field (S801). In the judgment of step S802, the Ist bit is determined. In the case where the tuple is not 00h4E5h 22 No. 97101636, the application is corrected in the case of 101.6.27 (S802, NO) 'The microprocessor 206 executes the rewriting process described later (S804), and judges the 5th bit of the 12, 4-tuple. If it is i (S805). When the 5th bit of the 121|1 byte is 1 (S805, YES), the microprocessor 206 executes subdirectory view processing (S806) which will be described later, and judges that the read is performed. Whether the 32-bit tuple is the end of the root directory field (S8〇3). On the other hand, the case where the 51|1 bit of the 12-bit byte is not 1 Next (S805, NO), the microprocessor 206 determines whether the 32-bit block read is the end of the root directory field (S803). Next, the operation of the rewriting process in the above conversion processing will be described. A flowchart showing the operation of the rewriting process. The processing described below corresponds to the step S804 in Fig. 17, and is considered to have been read into the 32-bit tuple from the root directory field. First, the microprocessor 206 is self-contained. 261|1 byte to 27tb byte reference cluster address N (S901) 'Re-read the MLC flag of the data specified by the cluster address N (S902), and determine whether the MLC flag is Y (S903) When the MLC flag is Y (S903, YES), the microprocessor 206 determines whether the cluster address N indicates whether the last cluster is FFF8h or more and FFFFh or less (S904). The cluster address N is FFF8h or more. In the case of FFFFh or less (S904, YES), the microprocessor 206 reads the next cluster address N of the material from the cluster address N (S908), and reads the MLC flag (S902). When the cluster address N is not FFF8h or more and FFFFh or less (S904, NO), the microprocessor 206 ends. In the judgment of step S903, in the case where the MLC is not Y, 1376695, the application No. 97101636, the modification of the 101.6.27 is replaced (S903, NO), and the microprocessor 206 is transmitted through the NAND interface unit 205 from the flash array. The sense amplifier/comparator circuit 1〇4 reads the data, stores the read data in the input/output buffer 107, and writes the data to the NAND flash array 101 with a value of 4 (S906), and then the MLC flag. The flag is set to 5 Y (S907), and it is judged whether the cluster address N indicates whether the last cluster is FFF8h or more and FFFFh or less (S904).

Next, the operation of the subdirectory view processing in the above conversion processing will be described. Fig. 19 is a flow chart showing the operation of the subdirectory view processing. In addition, the following description corresponds to the step S806 in Fig. 17, and it is considered that the 32-bit group has been read from the sub-directory field of the root directory 10 field or the 19th picture. First, the microprocessor 206 refers to the cluster address N (S1001) from the 261|1 byte to the 27th byte, and reads the 32-bit tuple from the sub-directory field specified by the cluster address N (S1002). And determine whether the Ist byte is 〇〇h or E5h(S1003)〇15 in the case of 1" byte is 〇〇h or E5h (S1003, YES), microprocessing

The device 206 determines whether or not the cluster address N is FFF8h or more and FFFFh or less (S1004). When the cluster address N is FFF8h or more and FFFFh or less (S1004, YES), the microprocessor 206 ends the processing. On the other hand, when the cluster address N is not FFF8h or more and FFFFh or less (S1004, NO), the microprocessor 206 reads the next cluster address N of the subdirectory from the cluster address N (S1007), The 32-bit tuple is read from the subdirectory field (S1002). Further, in the determination of step S1003, the Ist byte is not 00h or E5h 24 1376695. In the case of the modification of the application No. 97101636, 101.6.27 (S1003, NO), the microprocessor 206 performs the above-described rewriting process ( S1005), and judges whether 12 or 5th bit of the triad is 1 (S1006). In the case where the 5th bit of the triad is 1 (S1 〇〇6, YES), the microprocessor 206 reads the cluster 5 address N of the next subdirectory from the 26th byte tuple (S1001). ). On the other hand, when the 5th bit of the 12th byte is not 1 (S1006, NO), the microprocessor 206 determines whether or not the cluster address N is FFF8h or more and FFFFh or less (S1004). By the above processing, the NAND flash memory 1 can rewrite the data written with 2 values by 4 values. Further, although the case where the data written in the binary value is rewritten with the 4 value has been described, the data written in the 4 value can be rewritten with the 2 value. Next, the processing of transmitting the usage amount of the NAND flash memory of the present embodiment to the host will be described. Fig. 20 is a flow chart showing the actions of the process of transmitting 2 values and multi-values using 15 quantities, respectively. First, the microprocessor 206 receives the read command from the host through the host interface unit 2〇1 (S1101), and calculates the variable SN of the lsn, calculates the variable s of the fan type saved by the value of 2, and calculates the value of 4 The fan type variable M of the save is set to 0 (S1102), and the 20 MLC flag of the LSNSN (S1103) is read through the NAND interface unit 2〇5, and it is judged whether the MLC flag is y (sh〇4). In the case where the MLC flag is not γ (sn 〇 4, NO), the microprocessor 20 determines whether the MLC flag is n (S1105). In the case where the MLC flag is not N (sii 〇 5, N 〇), the microprocessor 200 adds 1 to the variable SN (S1106), and determines whether the variable value is greater than 25 1376695. No. 97101636, application 101.6.27 Replace the fan maximum value of the NAND flash array 1〇1 (S1107). In the case where the value of the variable SN is larger than the maximum value of the fan type of the NAND flash array 101 (S1107, YES), the microprocessor 206 transmits the value of the variable Μ to the host through the host interface unit 201 (S1108), and then transmits The host interface is 5 yuan 201, and the value of the variable S is sent to the host (S1109). On the other hand, in the case where the value of the variable SN is smaller than the maximum value of the fan type of the NAND flash array 101 (S1107, NO), the microprocessor 206 re-reads the MLC flag of the LSNSN through the NAND interface unit 205 (S1103). ). Further, in the judgment of step S1105, in the case where the MLC flag is N (S1105, YES), the microprocessor 206 adds 1 to the variable S (S1111), and adds 1 to the variable SN (SU06) » again' In the judgment of step S1104, in the case where the MLC flag is Y (S11〇4, YES), the microprocessor 206 adds 1 to the variable ( (S1110), and adds 1 to the variable SN (S1106). 15 As described above, by transmitting the fan type written in two values and the fan type written in four values, the host can calculate the NAND flash memory separately based on the variable Μ, variable S, and fan type information amount. The amount of 2 and 4 values used in the body 1〇. Further, in the NAND flash memory of the present embodiment, the amount of use of two values can be converted into a multi-value usage amount and transmitted to the host. Fig. 21 is a flow chart showing the operation of converting the usage amount of 2 to 20 into a multi-value usage amount and transmitting it to the host. Since steps S1101 to S1111 are the same as those in Fig. 20, the description thereof will be omitted, and steps S1112 to S1114 will be described. In the judgment of step S1107, in the case where the value of the variable SN is larger than the number of sectors of the NAND flash array 101 (S1107, YES), the microprocessor 206 is modified to apply for the modification of the application of 101.627 of the application No. 97101636. The value of the number S is doubled (S1U2), and the value of the variable μ is added to the value of the variable § (S1113), and the value of the variable _^ is transmitted to the host through the host interface unit 2 (S1114). As described above, the amount of use of the four values can be calculated by adding the number of sectors of the data stored in the two values to two times, and adding 5 to the number of sectors in which the data is stored at four values. In addition, by dividing the number of sectors of the data by dividing by 2 by 4 values and adding it to the number of sectors of the tribute stored at 2 values, the amount of use of the 2 values can be calculated. Next, Fig. 22 is a flowchart showing the operation of the display space capacity calculation processing. 10 First, the microprocessor 20 receives the read command from the host through the host interface unit 2〇1 (S1201), and calculates the variable SN of the LSN, the variable V of the calculated data validity, and the variable V of the fan type. The variable E of the display space capacity is set to 0 (S1202), and the data validity of the LSNSN is read through the NAND interface unit 205 (S12〇3), and it is judged whether or not the data validity is 15 (S1204). φ In the case where the data validity is not valid (S1204, NO), the microprocessor 206 adds 1 to the variable SN (S1205), and determines whether the value of the variable SN is greater than the total number of sectors of the NAND flash array 1 〇1. (s丨丨06). • The variable SN is greater than the maximum value of the fan type of the NAND flash array 101.

In the case of -20 (S1206, YES), the value of V can be subtracted from the maximum value of the fan type as the value of E (S1207), and the value of E is divided by 2 (S1208), and the value of E is sent to the host ( S1209). On the other hand, in the case where the value of the variable SN is smaller than the maximum value of the fan type of the NAND flash array 1〇1 (S1206, NO), the microprocessor 206 is again corrected by the application of 101.6.27 of the application No. 97101636. Replace the NAND interface unit 205 to read the data validity of the LSNSN (S1203) 〇 'In the case where the data validity is valid in step S1204 (S1204, YES) 'The microprocessor 206 adds the value of V to the si (si21) 〇), and the value of SN is incremented by 1 (S1205). 5 By the above operation, the NAND flash memory 1〇 can calculate the space capacity when writing to the NAND flash array 1〇1 with 2 values. By using the space capacity at the time of writing with the two values, it is possible to transmit an error to the host when writing information amount data larger than the space capacity when writing data at a value of two. Fig. 23 is a flow chart showing the action of replying error processing for data larger than the space valley $. 10 First, the microprocessor receives the write command (S1301) from the host through the host interface unit 2〇1 and reviews the space capacity (S13〇2), and then substitutes the variable E into the two valleys (S1303) and judges Whether the data sent by the host is greater than the value of E (S1304). In the case where the data transmitted by the host is smaller than the value of E, 15 (S1304, NO), the microprocessor 206 writes data to the NAND flash array 1〇1 through the NAND interface unit 2〇5 (S1305). On the other hand, in the case where the data transmitted by the host is larger than the value of E (S1304, YES), the microprocessor 206 transmits an error to the host through the host interface unit 2〇1 (S1306). 20 By the above actions, the NAND flash memory of the present embodiment can be switched to a value of 2 or 4 depending on the data attribute of the write. Next, the threshold value correction processing will be described. The threshold value correction processing may, for example, set a certain value set to a value of 2 to a value of 4, and in the case where the previously written data is different from the current setting, the application is based on the application No. 97 1376695 No. 97101636 Case 101.6.27 corrects the attributes of the replaced data, the MLC flag and the current setting table, and rewrites the data written with the binary value by 4 values. Fig. 24 is a flow chart showing the operation of the threshold value correction processing. First, the microprocessor 206 receives the correction command (S1701) from the host 5 through the host interface unit 2〇1 and refers to the data written in the NAND flash array 1〇1 (S1702)' and determines whether the data is catalog information ( S1703).

In the case where the data is the directory material (S1703, YES), the microprocessor 206' is the attribute information of the reference material (S1704), and judges that the attribute is the attribute to be written with the value of 4 in the current setting, that is, the judgment Whether it is archived (s 17〇5, 10 threshold conversion steps). In the case where the attribute is not archived (S1705, NO), the microprocessor 2〇6 writes the directory material to the NAND flash array 101 (S1706). On the other hand, in the case where the attribute is categorized (S1705, YES), the microprocessor 206 is the MLC flag of the reference material (S1708, threshold value conversion step 15), and judges whether the MLC flag is set to Y. (S1709, Threshold value conversion step). In the case where the MLC flag is not set to Y (S1709, NO), the microprocessor 206 stores the data that has been written into the NAND flash array 101 in the input/output buffer 107 (S1710), and will be 4 values. The stored data is written into the 20 NAND flash array l〇l (S1711, threshold value conversion step), and then the MLC flag of the written data is set to Y (S 1712) 'and the directory data is written to NAND fast Flash array 1 〇1 (S1706). On the other hand, in the case where the MLC flag is set to Y (S1709, YES), the microprocessor 206 writes the directory data to the NAND flash array 29 1376695. Application No. 97101636 101.6.27 Correction Replacement Column 101 (S1706) ). Further, in the case of the judgment of the step S1703, in the case where the material is not the directory material, the microprocessor 206 writes the data to the NAND flash array 101 with a value of 2 (S1707). 5 As described above, by comparing the attribute with the MLC flag, for example, in the case where the attribute information set to be written in 2 values is changed to the setting and written in 4 values, the data is stored in the value based on the current setting. In the NAND flash array 101. In addition, in Fig. 24, the case of rewriting the binary data by 4 values has been described, but in the case where the writing is also required to be written with 2 values but written with 4 values, it is 10 readings and writing with 4 values. Enter the data and store it in NAND flash array 1 with a value of 2 (Π. Implementation type 2 NAND flash memory of implementation type 1, switching between 2 and 4 values according to attribute information, but this embodiment NAND flash memory is switched between 2 and 4 according to the spatial capacity of the 15 NAND flash array. In addition, the NAND flash memory of this embodiment is constructed in the same manner as the implementation of the 丨2NAND flash memory. The operation differs from the NAND flash memory of the first embodiment. Fig. 25 is a flowchart showing the operation of the write processing in the embodiment 2. In the present embodiment, The capacity of the NAND flash memory is switched to a value of 4 when the binary value is 32 MB and the binary space capacity is 16 MB or less. First, the microprocessor 206 is Receiving a write command (S just) from the host through the host interface unit 2〇1, and then performing the space capacity shown in FIG. Calculate the processing (S1402) 'and determine whether the space capacity is greater than 16 MB (sl4 〇 3, the door broadcast 30 No. 97101636 application UU.6.27 correction replacement value decision step). In the case where the space capacity is greater than 16 MB (S1403, YES), The microprocessor 206 writes the data stored in the input/output buffer 1〇7 into the NAND flash array 101 by a value of 2 (S1404, writing step), and writes the NAND flash array 101 and The alternate MLC flag for the fan-length data of the data is set to N (S1405). On the other hand, in the case where the space capacity is less than 16 MB (S1403, NO), the microprocessor 206 is stored in the input/output buffer. The data in 1〇7 is written to the NAND flash array i〇i (si4〇6, writing step) with 4 values, and will be written to the NAND flash array 1〇1 and is the spare MLC of the sector type redundant data of the data. The flag is set to Y (S1407). By the above operation, the NAND flash memory 10 of the present embodiment can switch between the value of 2 and the value of 4 according to the space capacity, and can be highly trusted in the case where the space capacity is larger than a certain amount. Sexual 2 values are written to the data; in the case where the space capacity is less than a certain amount, the capacity can be large The data stored in the 4 values of the data is written, and the reliability and the large capacity are realized at the same time. Embodiment 3 The NAND flash memory of the implementation type 2 switches between the value 2 and the 4 value according to the space capacity, but the NAND of this embodiment mode The flash memory can switch between the value of 2 and 4 according to the number of writes in the memory unit of the NAND flash array. In addition, the structure of the NAND flash memory of the present embodiment is related to the implementation type 1 and the implementation type. The NAND flash memory of state 2 is the same, and only the action is different. Hereinafter, an operation different from the NAND flash memory of the second embodiment will be described. Fig. 26 is a flow chart showing the operation of the write processing in the embodiment 3. In addition, 丄 376695 No. 97101636, the application of the 101.6.27 correction replaces the present embodiment. In the description, the limit of the number of writes of the NAND flash memory is 4000 times; if the number of writes is less than 2 times , it is written with 4 values. When the number of writes is higher than 2000 times, the value of the write memory unit is switched to 2 values. 5 First, the microprocessor 206 receives a write command from the host through the host interface unit 201 (S1501), and then refers to the WF (S1502) for displaying the write count information as shown in FIG. 8, and determines the number of writes. Whether it is less than 2 times (S1503, threshold value decision step).

In the case where the number of writes is less than 2000 (S1503, YES), the microprocessor 10' writes the data stored in the input/output buffer 107 to the NAND flash array 101 with a value of 4 (S1504, write Step), the standby MLC flag written into the NAND flash array 101 and for the sector type redundant data of the data is set to Y (S1505), and 1 is added to the MF (S1506). On the other hand, in the case where the number of writes exceeds 2000 times 15 (S1503, NO), the microprocessor 206 is stored in the input/output buffer 107.

The data in the data is written to the NAND flash array i〇i (s 1507, write step) with a value of 2, and the standby MLC flag of the fan-type redundant data written to the NAND flash array 101 is set to Y ( S1508) 'Add 1 to the MF (S1506). With the above actions, the NAND flash memory 10, 20 of the present embodiment can switch between the value of 2 and 4 according to the number of writes, and the memory unit with a small number of writes is written with 4 values, and the number of writes is large. The memory unit, that is, the memory unit that continues to deteriorate is written with a high reliability value of 2, so that reliability and large capacity can be simultaneously achieved. Embodiment 4 32 1376695 Application No. 97101636 101.6.27 Correction NAND flash memory of the alternative embodiment 3, switching between 2 and 4 values according to the number of writes; but the NAND flash memory of this embodiment According to the error condition of the NAND flash array memory unit, the values of 2 and 4 are switched. In addition, the structure of the NAND flash memory of this embodiment is the same as that of the NAND flash memory of the implementation type 1, the fifth embodiment 2, and the implementation type 3.

different. Hereinafter, an operation different from that of the NAND flash memory of the third embodiment will be described. Fig. 27 is a flow chart showing the operation of the write processing in the embodiment 4. In addition, the error in this embodiment refers to an error in the sense amplifier/comparator loop during the reading of the above data; the microprocessor 206 receiving the error is a fan type that has received the error. The alternate EI for lengthy data is set to 1. First, the microprocessor 206 writes a command from the host through the host interface unit 201 (S1601), and then refers to the EI for displaying the error status information as shown in FIG. 8 (S1602), and determines whether the EI is 0. (S1603, the threshold value determines 15 steps). In the case where EI is 0 (S1603, YES), the microprocessor 206 writes the data stored in the input/output buffer 107 to the NAND flash array 101 by 4 values (S1604, writing step), and then The alternate MLC flag written to the NAND flash array 101 and the sector-type redundant data for the data is set to Y (S1605). 2. On the other hand, in the case where EI is not defective (S1603, NO), the microprocessor 206 writes the data stored in the input/output buffer 1〇7 to the NAND flash array 1 with a value of 2 〇 1 (S1606, write step), and the standby MLC flag written to the NAND flash array 101 and the fan-shaped redundant data of the data is set to N (S1507). 33 1376695 . . . __ Application No. 97101636 101.6.27 Correction Replacement With the above actions, the NAND flash memory 10 of this embodiment mode writes data by 4 values for a memory unit without errors. The erroneous memory unit, that is, the memory unit that continues to deteriorate is capable of writing data at a value of 2, so that reliability and large capacity can be simultaneously achieved. 5, in the above-described implementation 1, implementation 2, implementation 3, and implementation 4, the microprocessor 206 of the control IC 20 performs the above processing, but may also have the CPU of the information processing apparatus 1 These treatments. At this time, various parameters as a result of the processing can be temporarily stored in the control register 202 of the control j; C2〇. Further, the switching between the two values and the four values is only an example, and may be, for example, two values of 10 and 8 values. Industrial Applicability As described above, by applying to the present invention, data can be stored at a value of 2 or 4 depending on management information. [Simple description of the drawing] 15 [Fig. 1] shows an illustration of the information processing apparatus in the first embodiment. Fig. 2 is a view showing the hardware structure of the information processing device in the first embodiment. [Fig. 3] is a block diagram showing the configuration of the NAND flash memory in the embodiment 1. 20 [Fig. 4] is a block diagram showing the structure of the control 1C. [Fig. 5] shows a circuit diagram of a plurality of memory cells constituting a NAND flash array. [Fig. 6] shows the circuit diagram of the sense amplifier/comparator circuit. [Fig. 7] shows the circuit diagram of the sense amplifier/comparator circuit. 34 1376695 _ Application No. 97101636 101.6.27 Correction Replacement - 5 • [Fig. 8] shows the data structure diagram stored in the NAND flash array. [Fig. 9] is a diagram showing the setting table. [Fig. 10] is a flow chart showing the action of the file system recognition processing. Fig. 11 is a flow chart showing the operation of the write processing in the embodiment 1. [Fig. 12] is a flow chart showing the action of the attribute information recognition processing. 10 [Fig. 13] is a flowchart showing the operation of the switching process. [Fig. 14] is a flow chart showing the operation of performing the conversion processing when the power is turned on. [Fig. 15] is a flow chart showing the operation of performing the conversion processing at the time of the shutdown. 15 • [Fig. 16] is a flowchart showing the operation of the conversion processing when there is no instruction at the predetermined time. [Fig. 17] is a flowchart showing the operation of the conversion processing. [Fig. 18] A flow chart showing the operation of the rewriting process. [Fig. 19] A flow chart showing the operation of the subdirectory view processing. 20 [Fig. 20] is a flowchart showing the operation of separately transmitting 2-valued and multi-valued usage. [Fig. 21] is a flow chart showing the operation of converting the 2-value usage amount into the multi-value usage amount and transmitting it to the host. [Fig. 22] Flow chart showing the operation of the space capacity calculation processing 35 1376695 Application No. 97101636 101.6.27 Correction replacement diagram. [Fig. 23] is a flow chart showing an action of processing a data reply error larger than the space capacity. [Fig. 24] A flow chart showing the operation of the threshold value correction processing. 5 [Fig. 25] is a flow chart showing the operation of the write processing in the embodiment 2. [Fig. 26] is a flow chart showing the operation of the write processing in the embodiment 3.

[Fig. 27] shows a flow chart of the operation of the write processing in the embodiment 4. [Fig. 28] shows the bit maps stored in the 2-value type memory unit, the 4-value type memory unit, and the 8-value type memory unit. [Fig. 29] is a diagram showing the margins of the 2-value type memory unit and the 4-value type memory unit. 15 [Fig. 30] shows the distribution of memory cells of a 2-value memory unit.

An illustration of the relationship between thresholds. [Fig. 31] is a graphical representation showing the relationship between the distribution of memory cells and the threshold value of a 4-value type memory cell. [Description of main component symbols] 1.. Information processing device 16...LAN interface 10.. NAND flash memory 17...audio board 11,12...chipset 18...USB/PCI interface

13.. .CPU 19...BIOS

14.. Memory 20...Control 1C 36 1376695

Application No. 97101636 101.6.27 Correction Replacement 101...Flash Array 206...Microprocessor 102·&X;X Decoder 207...ROM 103···ΥDecoder 208...RAM 104...Sensing Amplifier/comparator loop DV...data validity 104a~l〇4c...sense amplifier BBI...bad block message 104d·..comparator loop ECC...data field error correction code 105...bit Address register/counter ECCS · _ · Error for standby spare 106... Instruction register positive code 107... Round-in buffer EI... Error information 201···Host interface unit LSN... Logic sector number 202... Control register MLC... Multi-layer memory unit flag 203... Buffer RSV... Inversion area 204... ECC unit 205... NAND interface unit WF... Write frequency 37

Claims (1)

1376695 _ No. 97101636 Application 101.6.27 Amendment 10, the scope of application for patents: 1. A semiconductor memory device, comprising: a plurality of memory units, which are memorable data; a threshold value determining unit, which is based on management data The information management 5 records the information to be written into the above-mentioned complex memory unit to determine a value of 2 or more, and determines the threshold according to the determined value of the complex memory unit; and the writing unit The data is written in the complex memory unit based on the threshold value determined by the threshold value determining unit. The semiconductor memory device of claim 1, further comprising a detecting unit that detects the attribute information as the predetermined management information, and the attribute information displays the data attached to the data. Further, the threshold value determining unit determines, based on the attribute information of the data detected by the detecting unit, the value 15 respectively written in the complex memory unit to be a binary value or a multi-value. 3. The semiconductor memory device of claim 2, further comprising a threshold value conversion unit, wherein the memory unit threshold value of the foregoing data is stored in the plurality of memory units and the attribute information according to the data is from the current threshold value When the threshold value determined by the determining unit is inconsistent, the gate 20 threshold conversion unit reads the data that has been written into the complex memory unit, and the threshold value determined by the threshold value determining unit is based on the attribute information according to the data. The above data is rewritten into the aforementioned complex memory unit. 4. The semiconductor memory device of claim 1, wherein the threshold value determining unit separately displays the data by the writing unit according to the display 38 1376695 10 15 Application No. 97101636 101.6.27 Correction Replacement 20 The information on the number of times of writing the plurality of memory cells is used as the predetermined management information, and the values respectively written in the complex memory cells are determined to be two or more values. 5. The semiconductor memory device of claim 1, wherein the threshold value determining unit determines the value of the complex memory unit as the predetermined management information based on the information indicating the spatial capacity of the plurality of memory units. 2 or more values. 6. The semiconductor memory device of claim 1, further comprising a threshold value correcting unit, wherein the threshold value correcting unit stores the memory cell threshold value of the data in the complex memory unit and the threshold value determining unit When the threshold value of the decision is different threshold value, the value written in the memory unit is determined to be a value of 2, and the threshold value is determined according to the value of 2; in addition, when the writing unit writes the data to the memory unit again, The aforementioned data is written into the aforementioned complex memory 7G in advance based on the threshold value determined by the threshold value correction unit. 7. A control device for controlling a semiconductor memory device comprising a plurality of memory cells capable of memorizing data, and comprising: a threshold value determining portion, based on predetermined management information for managing information of the data, The values respectively written into the plurality of memory cells are determined to be two or more values, and the threshold value is determined according to the values of the complex memory cells that have been determined to be determined; and the writing portion is determined by the threshold value determining unit. The threshold of the decision is made by writing the aforementioned information into the aforementioned complex memory unit. 8. The control device of claim 7 of the patent scope further includes a detection unit, 39 1376695 _ 97101636 application 101.6.27 correction replaces the detection unit to detect attribute information as the predetermined management information, and the The attribute information is information indicating the attribute of the data attached to the foregoing data; and the threshold value determining unit determines the value of the complex memory unit to be 2 according to the attribute information of the data detected by the detecting unit. Or multiple values. 9. The control device of claim 8 further includes a threshold value conversion unit, wherein the memory unit threshold value in which the data is stored in the plurality of memory units and the attribute information based on the data are determined by the current threshold value In the case where the threshold value determined by the department is inconsistent, the threshold value is changed to read the data of the plurality of memory units, and the threshold value determined by the threshold value determining unit is based on the attribute information of the data. The foregoing data is again written into the aforementioned complex memory unit. 10. The control device of claim 7, wherein the threshold value determining unit is configured as the predetermined management resource according to the information indicating the number of times the data is written into the first plurality of memory units by the writing unit. The value of the complex memory unit is determined to be 2 or more values. 11. The control device of claim 7, wherein the threshold value determining unit determines, according to the information indicating the spatial capacity of the plurality of memory units, the predetermined management information as 20, and writes the values respectively written into the plurality of memory units to 2 or more values. 12. The control device of claim 7, further comprising a threshold value correcting unit that stores the threshold value of the memory unit of the data in the plurality of memory units and the threshold value determined by the threshold value determining unit 40 1376695 Application No. 97101636 101.6.27 Correction When the threshold value is changed to a different threshold value, the value written to the memory unit is determined to be a value of 2, and the threshold value is determined according to the value of 2; When the data is written again to the memory unit, the data is written in the complex memory unit in accordance with the threshold determined by the threshold value correcting unit. 13. A control method for controlling a semiconductor memory device comprising a plurality of memory cells readable by data, and performing the following steps: 10 threshold threshold determining step, based on predetermined management of information for managing data The information is determined by writing the value of the complex memory unit to a value of 2 or more, and determining the threshold according to the determined value of the complex memory unit: and the writing step is determined according to the threshold value. The threshold value determined by the step is written into the foregoing complex memory unit. 15 14. If the control method of claim 13 is applied, the detecting step is further performed, and the detecting step detects the attribute information as the predetermined management information, and the attribute information displays the data attribute attached to the data. Further, the threshold value determining step determines the value of the complex memory unit to be 2 or more values based on the attribute information of the data detected by the detecting step. 20 15. If the control method of claim 14 is applied, the threshold value conversion step is further performed, wherein the threshold value conversion step is a memory unit threshold value in which the foregoing data is stored in the complex memory unit and an attribute data according to the data is In the case where the threshold value determined by the threshold value determining step is inconsistent, the data that has been written into the foregoing plurality of memory cells is read, and the threshold value is determined according to the attribute information according to the data. Step 41 1376695 Application No. 97101636 101.6.27 Correct the threshold value determined by the replacement, and write the above data to the above complex memory unit again. 16. The control method of claim 13, wherein the threshold value determining step is based on the information indicating the number of times the foregoing data is written into the plurality of memory units by the writing step, as the predetermined management information. The values written in the foregoing complex memory cells are determined to be 2 or more values. 17. The control method of claim 13, wherein the threshold value determining step is based on the information 10 showing the spatial capacity of the plurality of memory units as the predetermined management information, and is respectively written into the value of the plurality of memory units. Decide to 2 or more values. 18. If the control method of claim 13 is applied, the threshold value correction step is further performed, wherein the threshold value correction step is a memory cell threshold value in which the foregoing data is stored in the plurality of memory units and a step 15 is determined by the threshold value. When the threshold value determined is different threshold value, the record will be written The value of the unit is determined to be a value of 2, and the threshold value is determined according to the value of 2; in addition, the writing step is to write the data to the memory unit again, according to the threshold value determined by the threshold value correction step, and the foregoing data is Write the aforementioned complex memory unit. 42 1376695 Application No. 97101636 2012. 6. 27 Correction and replacement Figure 20 1376695 Application No. 97101636 101.6.27 Amendment Replacement 7. Designated representative: (1) The representative representative of the case is: (3) Figure (2) The symbolic symbol of the representative figure is simple: 10.. NAND flash Memory 20.. Control 1C 101.. Flash Array 102..X Decoder 103..Y Decoder 104.. Sense Amplifier/Comparator Circuit 105.. . Address Register/Counter 106... Instruction Register 107.. Input/Output Buffer 8. If there is a chemical formula in this case, please disclose the chemical formula that best shows the characteristics of the invention: