1376082 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種充電控制方法及裝置，特別是指 一種交錯式控制（Interleaved Control)充電方法及裝置。 【先前技術】 目刖可攜帶式電子產品多使用可二次充電的電池，如 鋰離子電池，相較於鎳鎘/鎳氫電池而言，鋰離子電池優點 包括無汙染且使用壽命長、單位重量能量密度大於鎳鎘及 鎳氫電池、工作電壓範圍大能高壓使用、自放電率小 '重 量輕、體積小、工作溫度範圍大、無記憶效應等。 大多數二次電池的充電控制電路係採用類比式設計， 然而’類比元件通常包含比較器及放大器，並透過電阻和 電谷等被動類比零件來設定開關頻率和軟啟動時間等組態 參數’設計上不似數位控制具有彈性，且類比式設計為非 交錯式設計，輸入漣波大，具有使用壽命低且易造成線路 及元件的損失的缺點。 【發明内容】 因此’本發明之目的，即在提供一種交錯式控制充電 方法及裝置。 於是’本發明用於一具有一升壓模組及至少二降壓單 元的充電裝置’該方法包含下述步驟：（a)數位化該升壓模 組的升壓電壓、各該降壓單元的感應電流及感應電壓；（b) 依據數位化的該升壓電壓對該升壓模組進行切換控制；及 (0依據數位化的各該降壓單元的感應電流及感應電壓對各 3 1376082 該降壓單TL進行定電流及/或定電壓控制並交錯式切換控制 各該降壓單元以產生充電電力。 本發明交錯式充電裝置包含一升壓模組、一降壓模組 切換電路、一類比/數位轉換模組及一數位訊號處理器 ，邊升壓模組對一輸入電壓升壓產生一升壓電壓；該降壓 模組具有至少二降壓單元，各降壓單元對該升壓電壓降壓 產生充電電力。 該切換電路耦接該升壓電壓及該降壓模組，受驅動切 換供電給該升壓模組升壓及該降壓模組產生該充電電力。 該類比/數位轉換模組耦接該升壓模組及該降壓模組， 用以數位化該升壓模組的升壓電壓、各該降壓單元的感應 電流及感應電壓。 δ玄數位訊號處理器叙接該類比/數位轉換模組及切換電 路’用以依據數位北的該升壓電壓對該升壓模組進行切換 控制並依據數位化的各該降壓單元的感應電流及各該感應 電壓對各該降壓單元進行定電流及/或定電壓控制並交錯式 切換控制各該降壓單元以產生充電電力。 本發明交錯式控制充電方法及裝置相較於類比式控制 方式採用交錯式的數位化控制方式，設計上較有彈性且能 降低輸入漣波而延長使用壽命並減少線路及元件的損失。 【實施方式】 有關本發明之前述及其他技術内容、特點與功效，在 以下配合參考圖式之較佳實施例的詳細說明中，將可清楚 的呈現。 4 1376082 電路絮槿 如圖1所示’本發明交錯式充電裝置1〇〇的較佳實施 例包含一升壓模組11、一降壓模組12、一切換電路13、一 類比/數位轉換模組14及一數位訊號處理器15。 升壓模組11對一輸入電壓6升壓產生一升壓電壓匕1; 降壓模組12具有至少二降壓單元121、122，各降壓單元 121、122對升壓電壓&降壓產生充電電力。 切換電路13具有三組開關驅動器ι31、132、133，開 關驅動器131耦接升壓電壓U，開關驅動器132、133分別 耦接降壓單元121、122，受數位訊號處理器15的驅動令升 壓模組11產生升壓電壓G及降壓模組12的降壓單元121、 122分別產生充電電力。 類比/數位轉換模組14耗接升壓模組11及降壓模組j 2 ，用以數位化升壓模組11的升壓電壓匕ι、降壓單元121的 感應電流L及感應電壓匕2 ’及降壓單元122的感應電流^及 感應電壓G，並將數位化結果傳送給數位訊號處理器丨5作 判斷處理。 本較佳實施例中，數位訊號處理器15是一可程式化邏 輯閘陣列（FPGA)，具有負責系統時序控制與開關控制時序 的主控制元件、處理回授補償並算出控制力再交由主控制 元件去執行比例積分微分元件（PID)，及用來將輸入的時脈 訊號倍頻的元件等，適於充電控制系統的數位化設計。 數位訊號處理器15耦接類比/數位轉換模組14及切換 電路13，用以依據數位化的升壓電壓&產生脈寬調變訊號 5 1376082 Μ,予開關驅動器131以對於升壓模組11進行切換控制。 另外，數位訊號處理器15並依據數位化的感應電流ζ£2 、心及感應電壓L、匕3產生脈寬調變訊號Μ2、Μ3予開關驅 動器132、133,藉此以交錯式切換驅動對各降壓單元121 、122分別進行定電流及/或定電壓控制。 本較佳實施例之相關規格如表一所示： 表一 電池 充電電壓：4.2±0.05V 1 標準充電電流：540mA 快充電流：2700mA 升 壓 模 組 輸入電壓VS 3.3V 中間電壓ν01 6V 輸入電容Cs 680 中間電容Ci 1000 M F 電感Li 49.5^ Η 二極體Di STPS30L60CT 功率開.關& IRE3205 降 壓 槙 組 中間電壓V01 6V i\ 輸出電壓V〇2 * V〇3 4.2V M 中間電容Q 1000//F 輸出電容c2，c3 470 "H 電感L2 * L3 63 uB. 二極趙1¾ * 1¾ SR260 功率開關S2· S3 IRP3205 切換頻率 100kHz 數位訊號處理器 Altera EPGA Cyclone Π 系列 UG EK2C20F484 壓^6二％組11的作較將輸人電壓[=3.3V升至升壓電 以作為對電降广12的作用將升壓電壓…… 之轸屮锻：’ 21 22的充電電力，且為了降低升壓模組11 壓'連波，數位訊號處理器15利用VHDL·控制器程 式交錯式與動兩個降麼單元121、122。 制益程 >閱圖1及圖2,本發明交錯式充電的控制方法的較佳 】中，數位訊號處理器15的控制原理說明如下：首先 判斷任—雷 目7^ 電池21、22疋否已充飽（步驟3〇1)?本較佳實施例 的電池2卜22的充飽電壓為4.2V，若充飽則結束充電；若 飽則判斷電池21、22的電壓是否大於預定電壓（步驟 302)?在此假設預定電壓為39V’若已大於該預定電壓 3·9ν，則改為「定電壓模式」充電（步驟3〇4);若未達該預 定電壓3.9V，則以「定電流模式」充電（步驟3〇3)，且於充 電過程中持續判斷電池21、22的電壓是否大於預定電壓（步 驟305)?若已大於預定電壓3.9V，改為「定電壓模式」充 電（步驟304)，再於充電過程中判斷電池21、22是否已充飽 (步驟306)?>若充飽則結束充電。 前述「定電流模式」為一開始控制降壓單元121、122 先用一定電流1Α對電池21、22充電，當任一電池21、22 的電壓達到一預定電壓3.9V時，轉成「定電壓模式」以一 定電壓充電將電池21、22充至4.2V ;假設一開始兩電池21 、22均為3.6V，兩電池21、22均會處於「定電流模式」以 1Α進行充電，但由於每顆電池21、22之内阻不同，導致充 電速度不同，所以假設有一電池21電壓達到3.9V時，於本 1376082 發明之控制方式將轉成「定電 而另一電池22若未達3.9V時 以1A充電，最後兩電池21、1376082 VI. Description of the Invention: [Technical Field] The present invention relates to a charging control method and apparatus, and more particularly to an interleaved control charging method and apparatus. [Prior Art] It is seen that portable electronic products use rechargeable batteries, such as lithium-ion batteries. Compared with nickel-cadmium/nickel-hydrogen batteries, lithium-ion batteries have advantages including non-polluting and long service life. The weight energy density is greater than that of nickel-cadmium and nickel-hydrogen batteries, the working voltage range is high, the high-voltage is used, the self-discharge rate is small, the weight is light, the volume is small, the working temperature range is large, and there is no memory effect. The charging control circuit of most secondary batteries is analogous. However, analog components usually include comparators and amplifiers, and configuration parameters such as switching frequency and soft-start time are set through passive analog components such as resistors and electric valleys. The design is not as flexible as digital control, and the analog design is non-interlaced design. The input chopping is large, which has the disadvantages of low service life and easy loss of lines and components. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide an interleaved control charging method and apparatus. Thus, the present invention is applied to a charging device having a boosting module and at least two step-down units. The method includes the following steps: (a) digitizing the boosting voltage of the boosting module, each of the step-down units Inductive current and induced voltage; (b) switching control of the boosting module according to the digitized boosting voltage; and (0 according to the digitized each of the step-down units of the induced current and induced voltage pair 3 1376082 The step-down single TL performs constant current and/or constant voltage control and alternately controls and controls each of the step-down units to generate charging power. The interleaved charging device of the present invention comprises a boosting module, a step-down module switching circuit, A type of analog/digital conversion module and a digital signal processor, the side boosting module generates a boosting voltage for boosting an input voltage; the bucking module has at least two bucking units, and each bucking unit The voltage is stepped down to generate charging power. The switching circuit is coupled to the boosting voltage and the step-down module, and is driven to switch power supply to the boosting module to boost and the buck module to generate the charging power. Digital conversion module coupling The step-up module and the step-down module are configured to digitize the boosting voltage of the boosting module, the induced current and the induced voltage of each of the step-down units. The δ meta-digital signal processor serializes the analog/digital The conversion module and the switching circuit ′ are configured to perform switching control on the boosting module according to the boosting voltage of the digital north, and according to the induced currents of the digitized bucking units and the respective induced voltages, the bucking unit Performing constant current and/or constant voltage control and interleaving switching control each of the step-down units to generate charging power. The interleaved control charging method and device of the present invention adopts an interleaved digital control method compared to the analog control mode, and is designed It is more flexible and can reduce the input chopping to prolong the service life and reduce the loss of the line and components. [Embodiment] The foregoing and other technical contents, features and effects of the present invention are preferably implemented in the following reference drawings. In the detailed description of the examples, it will be clearly shown. 4 1376082 Circuit Flot As shown in FIG. 1 , a preferred embodiment of the interleaved charging device 1 of the present invention comprises a The boosting module 11 , a step-down module 12 , a switching circuit 13 , an analog/digital conversion module 14 and a digital signal processor 15 . The boosting module 11 boosts an input voltage 6 to generate a boost The voltage step ;1; the buck module 12 has at least two buck units 121 and 122, and each buck unit 121, 122 generates charging power for the step-up voltage & step-down. The switching circuit 13 has three sets of switch drivers ι 31, 132, 133, the switch driver 131 is coupled to the boost voltage U, and the switch drivers 132 and 133 are respectively coupled to the buck units 121 and 122. The driving of the digital signal processor 15 causes the boost module 11 to generate the boost voltage G and the buck mode. The step-down units 121 and 122 of the group 12 respectively generate charging power. The analog/digital conversion module 14 consumes the boosting module 11 and the step-down module j 2 for digitizing the boosting voltage of the boosting module 11 The inductive current L and the induced voltage 匕2' of the buck unit 121 and the induced current ^ and the induced voltage G of the buck unit 122 are transmitted to the digital signal processor 丨5 for judging processing. In the preferred embodiment, the digital signal processor 15 is a programmable logic gate array (FPGA) having a main control component responsible for system timing control and switching control timing, processing feedback compensation, and calculating control power. The control component performs a proportional integral derivative component (PID) and a component for multiplying the input clock signal, and is suitable for the digital design of the charging control system. The digital signal processor 15 is coupled to the analog/digital conversion module 14 and the switching circuit 13 for generating a pulse width modulation signal 5 1376082 依据 according to the digitized boost voltage & to the switch driver 131 for the boost module. 11 performs switching control. In addition, the digital signal processor 15 generates a pulse width modulation signal Μ2, Μ3 to the switch driver 132, 133 according to the digitized induced current 22, the heart and the induced voltage L, 匕3, thereby driving the pair in an interleaved manner. Each of the step-down units 121 and 122 performs constant current and/or constant voltage control. The relevant specifications of the preferred embodiment are shown in Table 1: Table 1 Battery Charging Voltage: 4.2±0.05V 1 Standard Charging Current: 540mA Fast Charge Current: 2700mA Boost Module Input Voltage VS 3.3V Intermediate Voltage ν01 6V Input Capacitor Cs 680 Intermediate Capacitor Ci 1000 MF Inductor Li 49.5^ Η Diode Di STPS30L60CT Power On. Off & IRE3205 Buck 槙 Group Intermediate Voltage V01 6V i\ Output Voltage V〇2 * V〇3 4.2VM Intermediate Capacitor Q 1000/ /F Output Capacitor c2,c3 470 "H Inductor L2 * L3 63 uB. Two-pole Zhao 13⁄4 * 13⁄4 SR260 Power Switch S2· S3 IRP3205 Switching Frequency 100kHz Digital Signal Processor Altera EPGA Cyclone Π Series UG EK2C20F484 Pressure ^6 2% Group 11 will increase the input voltage [=3.3V to boost power as a function of the voltage drop of 12, the boost voltage...the charging power of '21 22, and in order to reduce the boost The module 11 is pressed 'continuously, and the digital signal processor 15 uses the VHDL controller to interleave the two units 121 and 122. In the preferred method of the interleaved charging control method of the present invention, the control principle of the digital signal processor 15 is as follows: First, the X-rays 7^ batteries 21, 22 are judged. Is it full (step 3〇1)? The battery 2 of the preferred embodiment has a charging voltage of 4.2V, and if it is full, it ends charging; if it is full, it determines whether the voltage of the batteries 21, 22 is greater than a predetermined voltage. (Step 302)? It is assumed here that the predetermined voltage is 39V', if it is greater than the predetermined voltage 3·9ν, it is changed to "constant voltage mode" charging (step 3〇4); if the predetermined voltage is not reached 3.9V, "Constant current mode" charging (step 3〇3), and continuously determine whether the voltage of the batteries 21, 22 is greater than a predetermined voltage during the charging process (step 305)? If it is greater than the predetermined voltage 3.9V, change to "constant voltage mode" Charging (step 304), and determining whether the batteries 21, 22 are fully charged during the charging process (step 306)? > The "constant current mode" is that the first control step-down units 121, 122 first charge the batteries 21, 22 with a constant current of 1 ,, and when the voltage of any of the batteries 21, 22 reaches a predetermined voltage of 3.9 V, it is converted into a constant voltage. Mode" charges the batteries 21, 22 to 4.2V with a certain voltage; assuming that both batteries 21, 22 are 3.6V at the beginning, both batteries 21, 22 will be in "constant current mode" to charge at 1 ,, but for each The internal resistances of the batteries 21 and 22 are different, resulting in different charging speeds. Therefore, if a battery 21 voltage reaches 3.9V, the control method of the invention of 1374608 will be converted to "setting power and the other battery 22 is less than 3.9V. Charging at 1A, the last two batteries 21,
定電壓模式」以4.2V進行充電， 3*9V時，則繼續處於「定電流模式 丨電池21、22都達3.9V時，就會都處於 進行充電，如此整個充電過程會持 才會停止，且不管兩顆電池處於哪 一種充電杈式，其充電電流岣會處於交錯式控制。 II.實測結炅 圖3及圖4為兩組降壓單元12卜122均操作於「定電 流模式」的各元件波形時序圖。 圖3為升壓模組U的功率開關&之驅動電壓乂㈣、輸 出電壓v01及電感電流1li，此時輸出電壓之直流值 6.16V，電感電流iL]之直流值為3 44A。 … 圖4為降壓模組12之功率開關1及&之驅·動電壓'η f v扣波形及兩相輸出電感電流^及iLS，此時輸出電感^電 极1L2之直流值為丨·〇4Α，輸出電感電流匕3之直流值為 1.04A，且功率開關Sz及1為交錯式驅動。 圖5及圖6為兩組降壓單元121、122操作於不同模式 各元件的波形時序圖。 圖5為升壓模組丨丨的功率開關I之驅動電壓丨、輸 出電壓v01及電感電流iLi，此時輸出電壓v⑴之直流值為 6.17V ’輸入電感電流…之直流值為3 。 圖6為降壓模組12之功率開關82及S3之驅動電壓Vgs2 及Vgs3波形及兩相輸出電感電流iL2及iL3 ’此時第電池22 已到達我們所設定之模式切換電壓3 9V，而轉成「定電壓 8 1376082 模，」，其電感電流lL3之直流值為議A，另—電池以 在疋電流模式」，其電感電流k之直流值為i〇6A。 圖7及圖8為兩組降壓單元121、122均操作於「定電 壓模式」各元件的波形時序圖。 圖7為升壓模組11的功率開關Si之驅動電壓V㈣、輸 出電壓ν01及電感電& iu，此時輸出電壓v⑴《直流值為 6.22V，電感電流iu之直流值為3 i9A。 圖8為降壓模組12之功率開關心及&之驅動電壓、2 及Vgs3波形及兩相輸出電感電流iLZ及iu，此時電感電^ 1l2之直流值為0.973A，電感電流iL3之直流值為〇 946a。 由前述圖3、圖5及圖7可知，其升壓模組u之輸出 電壓VG1介於6.16V至6.22V之間，故可知升壓模組u於 電壓回授控制下可得一穩定的輸出電壓。 由前述圖4、圖6及圖8可知，兩組降壓單元121、 122為交錯式切換控制，且在「定電流模式」時，降壓單元 121、122皆可將充電電流控制於幾乎接近於ία。 UI·有無交錯式控制之電壓漣浊tK _ 圖9為兩組降壓單元121、122於交錯式控制且降壓單 元121、122均操作於「定電流模式」時，輸入電流（或升壓 模組11之輸出電流）/〇1、降壓型轉換器之功率開關h之驅 動電壓vg5l及兩相電感電流Ζ·Ι2及Zi3之波形。 交錯式切換控制之降壓單元121、122的輸入電流^均 方根值計算： 9 1376082 ^Urms - ^/(/pk X-ID)2 + 7〇c2 = y[(2.04-1.08)xV〇2 2 +1.082 «1.1622(A) (1) 圖10為兩組降壓單元121、122於同步（非交錯）式控制 ^降壓單元121、122均操作於「定電流模式」時，輸入電 流(或升壓模組11之輸出電流”。1、降壓型轉換器之功率開 關S2之驅動電壓及兩相電感電流及。之波形。 不具交錯式同步控制之組降壓單元121、122的輸入電 流Μ均方根值計算： = 2x7〇62« 1.5748(A) (2) 由（1)式與（2)式可得知具有交錯式控制之降壓單元I!! ' 122的輸入電流漣波均方根值，確實比沒有交錯式的同步 控制要低，亦即，本發明採用的交錯式控制之電壓漣波較 低，因此可延長升壓轉換之輸出電容的壽命，減少線路及 元件的損失。 IV.結論 綜上所述，本發明交錯式控制充電方法及裝置採用交 錯式的數位化控制方式而具有下述功效，故確實能達成本 發明之目的。 1 ·操作參數格式化：就數位元件而言，是利用資料轉 換器使訊號轉為成數位資料，組態參數的設定由資料記憶 體來負貝，透過數位控制器使設計人員可以在不同情況下 自由選擇最佳處理方式，控制迴路會隨著不同的操作模式 與不同的轉移函數改變去適應不同狀態。 10 雨2.通訊.冑位通訊介面讓主機或系統層級處理器監控 ^•源供應’還可做為可程式功能或其他數位作業進入點， 除了支援程式設定，還可讓系統遠端記錄來監控電路的溫 度/電饥/¾壓等參數’因此可預測故障以增強系統可靠性， 避免系統停機並提供智慧型故障管理功能β 3. 可程式能力··可程式能力可透過軟體修改參數設定 ’不僅推廣以平台為基礎的應用設計方式，也可加快產品 上市時間’產品的差異性不在受限類比控制器的硬體電路 限制，改用數位控制器可以整合原本需由外部零件提供的 眾多功能’ S商只需用較少零件就能完成複雜的設計，降 低生產成本並提高可靠度。 4. 精確性：數位控制器的精確度遠超過類比控制，在 類比控制設計時需考慮元件的容許誤差值，而數位控制器 的參數控制是利用軟體方式，其參數及補償值都是儲存在 。己隐體中，不僅提供精確的控制能力，也能將設計調整更 接近理論上限值以實現更高效能。 5. 成本.電流感測臨界值的容許誤差值會電路常須採 超規格。又„十易造成最大誤差的產生；數位控制則可用軟 體自我校準來消除這些誤差，讓電路不必為了應付最大可 &誤差而採用超規格’這可使電路零件更小、體積更精巧 、成本也更低β 6. 降低輸入漣波：相較於同步控制方式，本發明採用 又錯式控制方式，能降低輸入漣波而延長使用壽命並減少 線路及元件的損失。 1376082 惟以上所述者，僅為本發明之較佳實施例而已，當不 能以此限定本發明實施之範圍，即大凡依本發明申請專利 範圍及發明說明内容所作之簡單的等效變化與修飾，皆仍 屬本發明專利涵蓋之範圍内。 【圖式簡單說明】 圖1是一系統方塊圖，說明本發明交錯式充電裝置的 較佳實施例； 圖2是一流程圖，說明本發明交錯式充電的控制方法 的較佳實施例； 圖3及圖4是波形時序圖，說明兩組降壓單元均操作 於「定電流模式」的各元件波形時序； 圖5及圖6是波形時序圖，說明兩組降壓單元操作於 不同模式各元件的波形時序： 圖7及圖8是波形時序圖，說明兩組降壓單元均操作 於「定電壓模式」的波形時序； 、 圖9是一波形時序圖，說明兩植降壓單元於交錯式控 制且降壓單元均操作於「定電流模式」；及 圖是一波形時序圖，說明兩組降壓單元於非交錯式 控制且降壓單元均操作於「定電流模式」。 12 1376082 【主要元件符號說明】 100.......交錯式充電裝置 11 .........升壓模組 12 .........降壓模組 121、122降壓單元 13 .........切換電路 131 ' 132 ' 133 .........開關驅動器 14 ......類比/數位轉換模組 15 .........數位訊號處理器 21、22 ··電池 301〜306步驟The constant voltage mode is charged at 4.2V, and when it is 3*9V, it will continue to be in the constant current mode. When the batteries 21 and 22 reach 3.9V, they will all be charged, so the whole charging process will stop. Regardless of which charging mode the two batteries are in, the charging current 岣 will be in an interleaved control. II. The measured junctions Figure 3 and Figure 4 show that the two sets of bucking units 12 and 122 operate in the "constant current mode". Timing diagram of each component waveform. Fig. 3 shows the driving voltage 乂(4), the output voltage v01 and the inductor current 1li of the power switch & of the booster module U. At this time, the DC value of the output voltage is 6.16V, and the DC value of the inductor current iL] is 3 44A. ... Figure 4 shows the power switch 1 of the buck module 12 and the driving voltage of the driving voltage 'η fv buckle and the two-phase output inductor current ^ and iLS. At this time, the DC value of the output inductor ^1L2 is 丨· 〇4Α, the output inductor current 匕3 has a DC value of 1.04A, and the power switches Sz and 1 are interleaved. Figures 5 and 6 are waveform timing diagrams of the two sets of buck units 121, 122 operating in different modes. Figure 5 shows the driving voltage 丨, output voltage v01 and inductor current iLi of the power switch I of the boost module ,. At this time, the DC value of the output voltage v(1) is 6.17V ’. The input DC current has a DC value of 3. Figure 6 shows the driving voltages Vgs2 and Vgs3 of the power switches 82 and S3 of the buck module 12 and the two-phase output inductor currents iL2 and iL3'. At this time, the battery 22 has reached the mode switching voltage of 3 9V set by us. The constant voltage is 8 1376082, and the DC value of the inductor current lL3 is A, and the battery is in the 疋 current mode. The DC value of the inductor current k is i〇6A. Fig. 7 and Fig. 8 are waveform timing charts of the operation of each of the two types of step-down units 121 and 122 in the "constant voltage mode". 7 is a driving voltage V (four), an output voltage ν01, and an inductive current & iu of the power switch Si of the boosting module 11. At this time, the output voltage v(1) "DC value is 6.22V, and the DC value of the inductor current iu is 3 i9A. 8 is the power switch core of the buck module 12 and the driving voltage of the &, 2 and Vgs3 waveforms, and the two-phase output inductor currents iLZ and iu. At this time, the DC value of the inductor power ^1l2 is 0.973A, and the inductor current iL3 The DC value is 〇946a. It can be seen from the foregoing FIG. 3, FIG. 5 and FIG. 7 that the output voltage VG1 of the boosting module u is between 6.16V and 6.22V, so that the boosting module u can be stably obtained under the voltage feedback control. The output voltage. As can be seen from FIG. 4, FIG. 6 and FIG. 8 , the two sets of step-down units 121 and 122 are interleaved switching control, and in the “constant current mode”, the step-down units 121 and 122 can control the charging current to be close to each other. In ία. UI·With or without interleaved control voltage turbulence tK _ Figure 9 is the input current (or boost) when the two sets of buck units 121 and 122 are interleaved and the buck units 121 and 122 are operating in the “constant current mode”. The output current of the module 11 is 〇1, the driving voltage vg5l of the power switch h of the buck converter, and the waveforms of the two-phase inductor currents Ζ·Ι2 and Zi3. The input current ^ root mean square value of the buck unit 121, 122 of the interleaved switching control is calculated: 9 1376082 ^Urms - ^/(/pk X-ID)2 + 7〇c2 = y[(2.04-1.08)xV〇 2 2 +1.082 «1.1622(A) (1) Figure 10 shows the input currents of the two sets of step-down units 121 and 122 when the synchronous (non-interleaved) control voltage reduction units 121 and 122 operate in the "constant current mode". (or the output current of the booster module 11). 1. The driving voltage of the power switch S2 of the buck converter and the waveform of the two-phase inductor current. The group of buck units 121 and 122 without interleaved synchronous control Input current Μ rms value calculation: = 2x7 〇 62 « 1.5748 (A) (2) The input current of the step-down unit I!! '122 with interleaved control can be known from equations (1) and (2) The rms value of the chopping wave is indeed lower than that without the interleaved synchronous control, that is, the voltage chopping of the interleaved control used in the present invention is low, thereby prolonging the life of the output capacitor of the boost conversion, reducing the line and The loss of components IV. Conclusion In summary, the interleaved control charging method and device of the present invention adopts an interleaved digital control method. It has the following effects, so it can achieve the purpose of the present invention. 1 · Operation parameter formatting: In the case of digital components, the data converter is used to convert the signals into digital data, and the configuration parameters are set by the data memory. Negative shell, through the digital controller allows designers to freely choose the best processing method under different conditions, the control loop will adapt to different states with different operating modes and different transfer functions. 10 Rain 2. Communication. The communication interface allows the host or system level processor to monitor ^•source supply' as a programmable function or other digital job entry point. In addition to supporting program settings, the system can also record remotely to monitor the temperature/electricity of the circuit. 3⁄4 pressure and other parameters' so predictable faults to enhance system reliability, avoid system downtime and provide intelligent fault management functions. 3. 3. Programmable ability · Programmable ability to modify parameter settings through software 'not only promotes platform-based Application design method can also speed up the time to market. 'Product differentiation is not in the hardware circuit of the restricted analog controller. The use of digital controllers can integrate many of the functions that would otherwise be required from external parts. The S-station can complete complex designs with fewer parts, reducing production costs and increasing reliability. 4. Accuracy: Digital Controller The accuracy is far more than the analog control. In the analog control design, the tolerance value of the component should be considered. The parameter control of the digital controller is to use the software mode. The parameters and compensation values are stored in the hidden body. Accurate control ability can also adjust the design closer to the theoretical upper limit to achieve higher performance. 5. Cost. The allowable error value of the current sensing threshold value is often required to exceed the specification. In addition, the ten easy to cause the largest error; digital control can be self-calibrated by software to eliminate these errors, so that the circuit does not have to use the super specification to cope with the maximum error & error. This can make the circuit parts smaller, more compact, and cost. Also lower β 6. Reduce input chopping: Compared with the synchronous control mode, the present invention adopts the wrong and wrong control mode, which can reduce the input chopping to prolong the service life and reduce the loss of lines and components. 1376082 The present invention is intended to be only a preferred embodiment of the present invention, and it is not intended to limit the scope of the present invention, that is, the simple equivalent changes and modifications made by the scope of the invention and the description of the invention are still in the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a system block diagram illustrating a preferred embodiment of an interleaved charging device of the present invention; FIG. 2 is a flow chart illustrating a control method for interleaved charging of the present invention. Preferred Embodiments; FIG. 3 and FIG. 4 are waveform timing diagrams illustrating that both sets of buck units operate in the "constant current mode" component waveforms. Figure 5 and Figure 6 are waveform timing diagrams showing the waveform timing of the two sets of buck units operating in different modes: Figure 7 and Figure 8 are waveform timing diagrams showing that both sets of buck units operate in "regulated voltage mode". Waveform timing; Figure 9 is a waveform timing diagram illustrating the two-ply buck unit in interleaved control and the buck unit operating in "constant current mode"; and the figure is a waveform timing diagram illustrating two sets of bucks The unit is in non-interlaced control and the buck unit operates in "constant current mode". 12 1376082 [Description of main component symbols] 100.......Interlaced charging device 11 .........Boost module 12 .........Buck module 121, 122 buck unit 13 ... ... switching circuit 131 ' 132 ' 133 ... ... switch driver 14 ... analog / digital conversion module 15 .... ..... digital signal processor 21, 22 · · battery 301 ~ 306 steps
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