1375389 六、發明說明： 【發明所屬之技術領域】 本發明係有關於她式電源之，特別是關於切 之待機功耗降低手段。 【先前技術】 切換式電源係利用由-供應電壓供電之PWM控制器產生一間 ，信號’以驅動-功率開關而將電能從輸人轉換至輸出。在起動 ^間丄該供應㈣储-低準位逐漸上升，*在該供應電壓未超 ，，界電壓’稱為咖_GN電壓之前，該閘控信號不會被產 =iLUVL0係Under voltage Lock 0ut欠電壓鎖住之縮寫。 ^了起動期間，除非遇到過載情況或該供應電壓低於—低臨界電 =爯為UVLO—OFF電壓，該閘控信號會不斷被送出。請參照圖i， :曰不-切換式電源之典型應用架構。如圖i所示，該切換式電 源PWM控制器l(U、一主變壓器1〇2、一輸出整 凡103、一瞧電晶體104、電阻1〇5〜⑽、 一^ 助繞組108以及-二極體109。 电谷⑼輔 田、在該架構中’該簡控制器⑼，由-供應電壓Vcc供電，係 測信號vcs和一回授信號vfb產生-閘控信號V。， 係一輸出電壓輸v〇ut相對於一參考電壓而產 -主102具有一主側及一二次側，其中該主側係耦接 ⑽m ti!N ’而該二次側則_至該輸出整流及紐單元 =3 ’以將電赫該主側轉移至該二次侧。該麵電晶體1〇4且 綱源極，其中該細_接關控信號/， ^ 至該主麵11 102之主侧而該雜職接至該電阻 ^工中充作Μ。該電阻器105係祕於該源極和一參考地之 間，以承餘主側電流路徑之電流而產生—€域測信號¥以。 3 1375389 該電阻106、電容1〇7、輔助繞組⑽以及二極體1〇9 產生該供應電壓Vcc，其中該電阻⑽係連接於該主輸 和該電容107之間，該電容m具有連接至該電阻1〇6 ^ 板和連接參考地之第二嫌’該辅職組⑽係連接於綠 考地和該二極體⑽之陽極之間，以及該二極體⑽ ^連 接至該電容107之第一極板。 蚀係連1375389 VI. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to her type of power supply, and more particularly to a means for reducing standby power consumption. [Prior Art] A switched power supply utilizes a PWM controller powered by a supply voltage to generate a signal 'to drive-power switch to convert electrical energy from input to output. During the start-up, the supply (4) storage-low level gradually rises, * before the supply voltage is not exceeded, and the boundary voltage is called the coffee_GN voltage, the gate control signal will not be produced = iLUVL0 is the Under voltage lock 0ut Abbreviation for undervoltage lock. ^ During the start-up, unless an overload condition is encountered or the supply voltage is lower than - low critical voltage = 爯 is the UVLO-OFF voltage, the gate control signal is continuously sent out. Please refer to Figure i, 典型 not-switched power supply typical application architecture. As shown in FIG. 1, the switching power supply PWM controller 1 (U, a main transformer 1〇2, an output 103, a transistor 104, a resistor 1〇5~(10), a help winding 108, and Diode 109. Electric Valley (9) auxiliary field, in the architecture 'the simple controller (9), powered by the - supply voltage Vcc, the measured signal vcs and a feedback signal vfb generated - gate control signal V., an output The voltage input v〇ut is generated relative to a reference voltage - the main 102 has a main side and a secondary side, wherein the main side is coupled to (10) m ti! N ' and the secondary side is _ to the output rectification Unit = 3 ' to transfer the main side of the galvanic to the secondary side. The surface transistor is 1 〇 4 and the source is the source, wherein the fine 接 is connected to the control signal /, ^ to the main side of the main surface 11 102 The multiplexer is connected to the resistor, and the resistor 105 is secreted between the source and a reference ground, and is generated by the current of the main-side current path. 3 1375389 The resistor 106, the capacitor 1〇7, the auxiliary winding (10) and the diode 1〇9 generate the supply voltage Vcc, wherein the resistor (10) is connected to the main input and the capacitor 107 The capacitor m has a second connection to the resistor 1〇6^ board and the connection reference ground. The auxiliary group (10) is connected between the green test ground and the anode of the diode (10), and the diode The body (10) is connected to the first plate of the capacitor 107.
該供應電壓Vcc之產生方式為：在起動期間，該電容贿 該主輸人盤V㈣電阻1G6充電而使該第—極板上之該 壓Vcc逐漸增加。當該供應電壓Vcc達到該刚控制器 刪―ON電壓時，該顺控制器而即開始遞送該閘控信號μ 開、關該NM0S電晶體1〇4而將電能自該主變壓器搬之主 =二次侧及關魏組.補助繞組⑽之魏接著經該二極 =109整流、該電容1()7驗而形成具有一直流準位之該供 壓 Vcc 〇 雜應電壓Vcc之該直流準位與該切換式電源之負載相關性 為：在負載^超過該切換式電源之額定值時，該直流準位會隨 增加而提高；若貞載超職切料鶴之該歡值，—過載保 •，制會被致此以迫使賴控信號Vg處於一低電位而關閉該麵s電 曰曰體104，使電能不再被遞送至該辅助繞組1〇8，其結果是，該電 容107上之電荷被抽離以供應該觸控制器1〇1，而使該供應^壓 Vcc之電壓隨時間遞減。當該供應電壓Vcc下降至一⑽l〇_〇行電 屢時’該PWM控制H 101將停止運作而該電容器1〇7將獲得該主 ，入_ ^流經該電阻106之電荷，而使該供應輕—上升。 若負載仍然超過該額定值，該供應電壓Vcc將會在該_-〇FF電 壓和該UVL0—0N電壓之間不斷上升和下降。 因該電阻106之功耗在該觸控制器處於一待機模式時係該 切換式電源之主要功耗，該電阻刷之電阻值乃被極大化設計， 以降低該切換式電源之待機功耗。然而，由於該電阻1〇6之電阻 4 1375389 值必須小於一最大值，以符合一切換式電源其起動時間之規格， 例如最多1秒鐘，故降低切換式電源之待機功耗有其困難。 習知一解決方案係在PWM控制器内設定一較低之UVL〇_〇N電 壓，以便該電阻106可採用較大的電阻值而不會違反切換式電源 應用之起動時間規格。該供應電壓Vcc係經由該電阻對該電 谷107充電而產生’而較低的uyL〇—〇N電塵可以降低該供應電壓 Vcc達到該UVLO—ON電壓所需的時間，故該電阻1〇6即可採較大之 ，阻值以降低待機雜。然而，當該圆控制器丨進入操作狀 J ’該較低之UVL0—0N電壓可能會導致該顺〇s電晶體1〇4損壞。 /、原因在於：當發生過載保護，在一較低之UVL〇_〇N電壓下， 電壓VCC準位之一較低間控信號Vc準位乃被用以ί =所1G4 ’以流過—大電流，而由該較低閘控信號Vc 電晶體1料通電阻將使該嶋電 因此’有必要提供-個能夠降低待 =切換式電源解決方案。有繁於此瓶頸，;關 新穎的切換式電源待機功耗降低方法及裝置， 起動期間和摔作期問谐遮m a m /、力效係藉由在 【發明内ir 同-0n電壓而達成。 機功耗之方法，苴且有& 八種用以降低切換式電源待 以產生一選ί信號具對一供應輕執行-遲滞比較， 其中該遲滯比較:該$俨；::有-第-狀態及-第二狀態， 壓與該供應電壓比較，在‘急時係以-高臨界電 選擇域處於該第二狀態時則以一低 5 1375389 臨界賴與該供應電壓比較；以及依闕擇錢歧一肌請 電麼，其中當該選擇信號處於該第一狀態時，制腳〇N電壓係 為一第一準位，當該選擇信號處於該第二狀態時，該UVLO 0N電 壓則為一第二準位。 一 $ 為達成上述目的，本發明進—步提供了—種用以降低切換式 電源待機雜之裝置，其具有：—施密特觸發器，用以對一供岸 電壓執打-遲滞比較，以產生一選擇信號，該選擇信號具有一第 -狀態及-第二狀態’其巾該遲滯味在該選擇慨處於該第一 狀，時係以-高臨界電壓與該供應電壓比較，在該選擇信號處於 ，第二狀態時則以一低臨界電壓與該供應電壓比較；以及一切換 單兀，用以依該選擇信號決定一 UVLO—ON電壓，且中當該選擇俨 號處於該第一狀態時，該UVL0_0N電壓係為一第二準位°，當該^ 擇信號處於該第二狀態時，該UVL0_0N電壓則為一第二準' 為使貴審查委員能進-步瞭解本發明之結構、特徵及盆目 的，茲附以圖式及較佳具體實施例之詳細說明如后。 八 【實施方式】 請參照圖2’其繪不本發明-較佳實施例實現之待機功耗降低 裝置之電路圖。如圖2所示，該電路具有一比較器2〇1、電阻2〇2 〜203、一反相器204、開關210、220、一比較器23〇以及電阻 〜232。 在該電路中，該比較器201和該等電阻2〇2〜2〇3係用以實現 一施密特觸發器，以依一供應電壓Vcc和一參考電壓Vref產生一 擇信號Sl-_。該比較器201具有連接至該供應電壓Vcc之一負衿 入端’連接至-臨界電壓之-正輸入端，及用以產生該選擇作^ Sl-pu)之一輸出端。當該選擇信號&—1^處在一高準位時，該正^乂 端獲得一臨界電壓v™，其係為該高準位與該參考電壓之二聂 加電壓，而當該選擇彳虎Sl-uvlo處在一低準位時，該正輸入 -臨界電壓v™’其係為該低準位與該參考賴疊加電^ 6 1375389 該反相器204係用以使該選擇信號Sl-uvl〇反相以產生一互補選 擇信號Sh-kvu)。該等開關210、220係用以在該選擇信號及該 互補選擇信號SlMJVU)之控制下分別將一低電壓Vl-uvlq、一高電壓yH_UVL〇 耦接至該比較器230。 該比較器230、該等電阻231〜232係用以實現一施密特觸發 器，以依一供應電壓Vcc及一擇自該低電壓或該高電壓 之電壓產生一指示信號UVL0。該低電壓Vl-uvlo係用以在該指示信號 UVL0處在一高準位時產生一低UVL0—0N電壓，及在該指示信號 UVL0處在一低準位時產生一低UVL0—0FF電壓。該高電壓\^_係 鲁 用以在該指示信號UVL0處在該高準位時產生一高UVL〇—〇N電壓， 及在該指示信號UVL0處在該低準位時產生一高uvLO—OFF電壓。 其中該低UVL0_0N電壓和該低UVL0_0FF電壓構成一第一遲滞帶， 而該高UVL0—0N電壓和該高UVL0_0FF電壓構成一第二遲滯帶。 該供應電壓Vcc在該切換式電源處於不同階段時之波形乃示 於圖3。在圖3中’ V™係為該低UVLO—ON電壓；Vthi係為該低 UVL0一OFF電壓；V™係為該高UVLO—〇N電壓；而Vt„2係為該高 UVL0_0FF電壓。當該切換式電源處於期間，該供應電壓Vcc係 由-電流經-電阻對-電容充電而逐漸升高，且在t。期間結束時 達到該V™3。在期間，由於該供應電壓Vcc係由一低準位上升， 該比較S 201輸出端所送出之該選擇信號s_乃處在該高準位， 從而使該比較器201正輸入端獲得臨界電壓Vth3，並使該開關21〇 閉合、δ亥開關220斷開以選擇該低電壓vluvl〇而在該比較器2洲正 輸入端產生由該低UVL0—0N電壓V™和該低UVL〇—〇FF電壓Vm组成 之該第一遲滞帶。 在七期間，該比較g 20!輸出端所送出之該選擇信號& _乃 變至該低準位’從而使該比較器201正輸入端獲得臨界電壓^， 並使該開關210斷開、該開關220閉合以選擇該高電壓v_而在 該比較H 230正輸入端產生由該高〇N電壓L和該高 7 UVL0J)FF電壓-組成之該第二遲滞帶。此外，該供應電壓Vcc 在七期間之電壓下降係由-主側功率開關之暫時導通造成。 在t2期間，該供應電壓的Vcc係由一辅助繞組獲得電能，且 當七期間結束時’該供應電壓vcc係高於Vtr4。 t3期間係對應於該切換式電源之待機模式，其中該供應電壓 Vcc和V™的電壓差距很小。 t4期間侧應於該切換式電源之_重賴式，其巾該供應電 堡Vcc和V™的電壓差距係大於七期間所具者。 在1：5綱發生-過齡護，使該主側開關此關。該供應 v座Vex接著隨時間下降直到其到辆第二遲滯帶之下界電壓 v™2，而使該PWM控制器停止操作。 b期間5亥切換式電源仍然處於過載，因此，當該供應電壓 過過該電阻之充電電流造成)達到V™4時，該切換式電源之 ，=將再次_該主侧功率_，而使該供應電壓被來回保 寻在該第一遲滯帶之上、下界電壓中。The supply voltage Vcc is generated by charging the main input panel V (four) resistor 1G6 during startup to cause the voltage Vcc on the first plate to gradually increase. When the supply voltage Vcc reaches the ON voltage of the controller, the controller starts to deliver the gate signal μ to turn on and off the NMOS transistor 1〇4 and transfer the power from the main transformer to the main = The secondary side and the Guanwei group. The Wei of the auxiliary winding (10) is then rectified by the diode = 109, and the capacitor 1 () 7 is used to form the DC standard of the voltage Vcc which has a constant current level. The load correlation between the bit and the switched power supply is: when the load exceeds the rated value of the switched power supply, the DC level will increase with an increase; if the load exceeds the value of the over-cut cutting crane, The overload protection system is caused to force the control signal Vg to be at a low potential to turn off the surface of the electrical body 104 so that the electrical energy is no longer delivered to the auxiliary winding 1〇8, and as a result, the capacitance The charge on 107 is extracted to supply the touch controller 1〇1, and the voltage of the supply voltage Vcc is decreased with time. When the supply voltage Vcc drops to one (10) l 〇 〇 电 ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' Supply light - rising. If the load still exceeds the rated value, the supply voltage Vcc will continuously rise and fall between the _-〇FF voltage and the UVL0-0N voltage. Since the power consumption of the resistor 106 is the main power consumption of the switching power supply when the touch controller is in a standby mode, the resistance value of the resistor brush is maximally designed to reduce the standby power consumption of the switched power supply. However, since the resistance of the resistor 1〇6 4 1375389 must be less than a maximum value to meet the specification of the starting time of a switched power supply, for example, up to 1 second, it is difficult to reduce the standby power consumption of the switched power supply. A conventional solution is to set a lower UVL 〇 〇 N voltage in the PWM controller so that the resistor 106 can take a larger resistance value without violating the startup time specification of the switched power supply application. The supply voltage Vcc charges the electric valley 107 via the resistor to generate 'the lower uyL〇-〇N electric dust can reduce the time required for the supply voltage Vcc to reach the UVLO-ON voltage, so the resistor 1〇 6 can be larger, the resistance value to reduce standby noise. However, when the circular controller 丨 enters the operational state J', the lower UVL0-0N voltage may cause the smooth s transistor 1〇4 to be damaged. /, the reason is: when overload protection occurs, at a lower UVL 〇 〇 〇 N voltage, one of the voltage VCC levels lower the control signal Vc level is used to ί = 1G4 ' to flow through - The high current, while the lower gate control signal Vc transistor 1 material through-resistance will make the power supply so it is necessary to provide a solution that can reduce the switching power supply. There are many bottlenecks in this bottleneck; the novel switching power supply standby power consumption reduction method and device, during the start-up period and during the fall-off period, the harmonic effect is achieved by the same voltage as -0n in the invention. The method of power consumption, and there are eight types to reduce the switching power supply to generate a selection signal to a supply light execution-hysteresis comparison, wherein the hysteresis comparison: the $俨;:: yes - a first state and a second state, wherein the voltage is compared with the supply voltage, and when the emergency mode is in the second state, the voltage is compared with the supply voltage by a low 5 1375389 threshold;阙 钱 钱 一 一 肌 , , , , , , , , , , , 钱 钱 钱 钱 钱 钱 钱 钱 钱 钱 钱 钱 钱 钱 钱 钱 钱 钱 钱 钱 钱 钱 钱 钱 钱 钱 钱 钱 钱 钱 钱 钱 钱Then it is a second level. In order to achieve the above object, the present invention further provides a device for reducing the switching power supply standby, which has: - Schmitt trigger for performing a shore voltage-hysteresis comparison And generating a selection signal having a first state and a second state, wherein the hysteresis taste is in the first state, and the high threshold voltage is compared with the supply voltage. The selection signal is in a second state, and is compared with the supply voltage by a low threshold voltage; and a switching unit is used to determine a UVLO-ON voltage according to the selection signal, and wherein the selection nickname is at the In a state, the UVL0_0N voltage is a second level °, and when the selection signal is in the second state, the UVL0_0N voltage is a second standard 'to enable the reviewing committee to further understand the present invention. The structure, features, and objects of the present invention are attached to the drawings and detailed description of the preferred embodiments. [Embodiment] Referring to Fig. 2', a circuit diagram of a standby power consumption reducing apparatus realized by the present invention - a preferred embodiment will be described. As shown in FIG. 2, the circuit has a comparator 2〇1, resistors 2〇2 to 203, an inverter 204, switches 210 and 220, a comparator 23A, and resistors 232. In the circuit, the comparator 201 and the resistors 2〇2~2〇3 are used to implement a Schmitt trigger to generate a select signal S1-- according to a supply voltage Vcc and a reference voltage Vref. The comparator 201 has an output connected to a positive input terminal of the supply voltage Vcc connected to the -threshold voltage, and an output terminal for generating the selection. When the selection signal & -1 is at a high level, the positive terminal obtains a threshold voltage vTM, which is the high level and the reference voltage of the two Nie plus voltage, and when the selection When the S-UVlo is at a low level, the positive input-threshold voltage vTM' is the low level and the reference sub-electrode ^ 6 1375389. The inverter 204 is used to make the selection signal Sl-uvl〇 is inverted to generate a complementary selection signal Sh-kvu). The switches 210 and 220 are configured to couple a low voltage V1-uvlq and a high voltage yH_UVL〇 to the comparator 230 under the control of the selection signal and the complementary selection signal S1MJVU). The comparator 230 and the resistors 231 232 are configured to implement a Schmitt trigger to generate an indication signal UVL0 according to a supply voltage Vcc and a voltage selected from the low voltage or the high voltage. The low voltage Vl-uvlo is used to generate a low UVL0-0N voltage when the indication signal UVL0 is at a high level, and a low UVL0-0FF voltage when the indication signal UVL0 is at a low level. The high voltage is used to generate a high UVL〇-〇N voltage when the indication signal UVL0 is at the high level, and a high uvLO when the indication signal UVL0 is at the low level. OFF voltage. The low UVL0_0N voltage and the low UVL0_0FF voltage form a first hysteresis band, and the high UVL0-0N voltage and the high UVL0_0FF voltage form a second hysteresis band. The waveform of the supply voltage Vcc when the switching power supply is at different stages is shown in Fig. 3. In Figure 3, 'VTM is the low UVLO-ON voltage; Vthi is the low UVL0-OFF voltage; VTM is the high UVLO-〇N voltage; and Vt„2 is the high UVL0_0FF voltage. During the switching power supply period, the supply voltage Vcc is gradually increased by the current-resistance pair-capacitance charging, and reaches the VTM3 at the end of the period of t. During this period, since the supply voltage Vcc is A low level rises, the selection signal s_ sent by the output of the comparison S 201 is at the high level, so that the positive input voltage of the comparator 201 obtains the threshold voltage Vth3, and the switch 21 is closed. The delta switch 220 is turned off to select the low voltage vluvl, and the first hysteresis composed of the low UVL0-0N voltage VTM and the low UVL〇-〇FF voltage Vm is generated at the positive input terminal of the comparator 2 During the seventh period, the selection signal & _ sent by the output g 20! is changed to the low level ', so that the positive input terminal of the comparator 201 obtains the threshold voltage ^, and the switch 210 is turned off. Turning on, the switch 220 is closed to select the high voltage v_ and at the positive input end of the comparison H 230 is generated by the high The N voltage L and the high 7 UVL0J) FF voltage - the second hysteresis band of the composition. In addition, the voltage drop of the supply voltage Vcc during the seven period is caused by the temporary conduction of the -main side power switch. During t2, the The Vcc of the supply voltage is obtained by an auxiliary winding, and when the seven period ends, the supply voltage vcc is higher than Vtr4. The period of t3 corresponds to the standby mode of the switched power supply, wherein the supply voltages Vcc and VTM The voltage difference is very small. The period of t4 should be based on the switching power supply, and the voltage difference between the supply of Vcoll and VTM is greater than that of the seven periods. The main side switch is turned off. The supply v-mount Vex then drops with time until it reaches the second hysteresis band lower voltage vTM2, causing the PWM controller to stop operating. Still overloaded, therefore, when the supply voltage exceeds the charging current of the resistor and reaches VTM4, the switching power supply, = will again _ the primary side power _, and the supply voltage is guaranteed Above the first hysteresis band, in the lower boundary voltage .
請來^ ^路之賴，本發鴨-步提出-躺功耗降低方法。 待4示依本發明—較佳實施例之用崎低切換式電源 對—供核糊。如® 4所示，該流雜包括以下步驟： 狀態一:滯比較’以產生具有-第-狀態和-第二 電壓（步驟b) σ唬（步驟a)，以及依該選擇信號決定一 UVL0_0N -高^ j a ’當該選擇信號處於該第—狀態時’該遲滯比較係以 態時，亨=與該供應電比較，而當該選擇信號處於該第二狀 在=遲滞比較則以一低臨界電壓與該供應電壓比較。 係為-^ ^ ’當該選擇信號處於該第—狀態時，該UVLQ-0N電壓Please come to ^ ^路之赖, this hair duck-step proposed - lying power reduction method. In accordance with the present invention, the preferred embodiment uses a low-switching power supply pair for the core paste. As shown in Figure 4, the flow includes the following steps: State one: hysteresis comparison 'to produce a -first state and -second voltage (step b) σ唬 (step a), and a UVL0_0N is determined according to the selection signal - high ^ ja 'when the selection signal is in the first state, 'when the hysteresis comparison is in the state, hen = compared with the supply power, and when the selection signal is in the second state = lag is compared to one The low threshold voltage is compared to the supply voltage. Is -^ ^ ' when the selection signal is in the first state, the UVLQ-0N voltage
電壓則為一坌位而當該選擇信號處於該第二狀態時，該UVL0-0N 帶而該第：^二準位，其中，該第―準位係用以產生-第-遲滯 第一準位則用以產生一第二遲滯帶。 1375389 :帶帶實施，一可在起動期間採用一較低狐〇電壓遲 f帶而在之後切換至―正常麵電壓遲滞帶之切換式電』 出。本發明之料允許使驗大之充電電阻，而不會違反起動時 格或降低主側功率_之閘控信號電 f 確已克服了習知電路之缺·點。 ⑽尽赞月 於本較佳實施例，舉凡局部之變更或修飾而源 本為熟習該項技藝之人所易於推知者，俱不脫The voltage is a clamp, and when the select signal is in the second state, the UVL0-0N band and the second: the second level, wherein the first level is used to generate a first-lag retardation first The bit is used to generate a second hysteresis band. 1375389: Belt implementation, one can use a lower fox voltage delay band during start-up and then switch to the "normal surface voltage hysteresis band switching mode". The material of the present invention allows the verification of the large charging resistor without violating the starting time or lowering the main side power _ the gate control signal has indeed overcome the shortcomings of the conventional circuit. (10) Appreciation of the Month In the preferred embodiment, any change or modification of the subject is easily decimated by those who are familiar with the skill.
於習索;異 專利要件，”實亦在在符合發明之 二上處委貝明察’並析早曰賜予專利，俾嘉惠 【圖式簡單說明】 =!ΛΤ"，’其繪示—切換式電源之典型應用架構。 雜;低裝财發明—_實補魏之待機 正=====峨vee在起咖、 切換====她-崎雜用以降低 【主要元件符號說明】 PWM控制器ιοί 主變壓器102 輸出整流及濾波單元103 MMOS電晶體1〇4 電阻 105〜106、202〜203、231 〜232 電容107 辅助繞組108 9 1375389 二極體109 比較器201、230 反相器204 開關 210、220In the case of Xisuo; different patent requirements, "it is also in the second in line with the invention of the second section of the committee" and analyze the early patents, 俾嘉惠 [simple description of the schema] =! ΛΤ ", 'it shows - switch Typical application architecture of the power supply. Miscellaneous; low-loading invention - _ _ _ Wei Wei standby ===== 峨vee in the coffee, switch ==== her-is used to reduce [main component symbol description] PWM controller ιοί main transformer 102 output rectification and filtering unit 103 MMOS transistor 1〇4 resistors 105~106, 202~203, 231~232 capacitor 107 auxiliary winding 108 9 1375389 diode 109 comparator 201, 230 inverter 204 switches 210, 220