TWI375313B - Semiconductor package having marking layer - Google Patents

Semiconductor package having marking layer Download PDF

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Publication number
TWI375313B
TWI375313B TW97140035A TW97140035A TWI375313B TW I375313 B TWI375313 B TW I375313B TW 97140035 A TW97140035 A TW 97140035A TW 97140035 A TW97140035 A TW 97140035A TW I375313 B TWI375313 B TW I375313B
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Taiwan
Prior art keywords
sheet
compound
color
substrate
reflectance
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TW97140035A
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Chinese (zh)
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TW201017856A (en
Inventor
Kazuaki Ano
Wen Yu Lee
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Texas Instruments Inc
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Priority to TW97140035A priority Critical patent/TWI375313B/en
Publication of TW201017856A publication Critical patent/TW201017856A/en
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Publication of TWI375313B publication Critical patent/TWI375313B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

The symbolization of a semiconductor device (100) is incorporated in a thin sheet (130) attached to the top of the device, facing outwardly with its bare surface. The material of the sheet (about 1 to 10 &mgr; m thick) includes regions of a first optical reflectivity and a first color, and regions (133) of a second optical reflectivity and a second color, which differ from, and contrast with, the first reflectivity and color. Preferred choices for the sheet material include the compound o-cresol novolac epoxy and the compound bisphenol-A, more preferably with the chemical imidazole added to the film material. A preferred embodiment of the invention is a packaged device with a semiconductor chip a (101) connected to a substrate (102); the connection is achieved by bonding wires (111) forming an arch with a top 111a. The chip, the wire arches, and the substrate are embedded in an encapsulation material (120), which borders on the attached top sheet so that the arch tops touch the border (131).

Description

1375313 九、發明說明： 【發明所屬之技術領域】 裝置與製程之領域；且更特 用於提供可讀標記的可見標 之封裝的結構及製造方法。 本發明大體上係關於半導體 定言之’本發明係關於具有一 記層’而不致危及封裝完整性 【先前技術】 在將半導體晶片封裝成為完敕 疋整裝置之流程中，最終步驟 通常係該裝置之標號。此步騍1375313 IX. Description of the invention: [Technical field to which the invention pertains] The field of devices and processes; and more particularly to the structure and method of manufacture of a visible standard package that provides readable indicia. The present invention generally relates to semiconductors, 'the present invention relates to having a layer' without compromising package integrity. [Prior Art] In the process of packaging a semiconductor wafer into a finishing device, the final step is usually The label of the device. This step

驟6己錄使用者為該裝置之正福 識別及使用所需知道的資訊 制、 貝汛。實例包含裝置類型及模型、 製造商、主要性能特點及日期 … w期。代表性的標號要素包含數 子、字母、商標符號、標點您 ^ 付唬、箭頭及類似的可讀標 記。最受歡迎的標號技術俜利 一 T你利用墨水壓印大小為小至0.8 mm高度的字母及利用雷射 — 蜾大小為小至0.56 mm高度的 字母。 在上墨技術中，墨水與封裝頂面間存在色差，其使得標 就變得易f賣。對比色的墨水係沈積在封裝頂面上；舉例而 言’如白色墨水在黑色環氧樹脂模製封裝上。沈積的墨水 在封裝表面上形成堆積體或堆疊體，有別於封裝表面之平 丨減j、字母大小之限制特別係墨水邊界之模糊及使墨 水變髒之風險H墨水無法提供足夠好的解析度而為 小型封裝上墨標記給^優良的可讀性。 發在雷射劃線技術中’存在可見光之反射差異，其使得該 號鏈知易。貝。雷射劃線尤其有利於由塑膠化合物製成的 封裝’該封裝通常係藉由轉移模製技術予以製^在該模 135484.doc 1375313 製技術中，該組合物係經選擇以在聚合之後獲取一光亮表 面，因此該表面具有良好的可見光反射率。該雷射束在該 封裝樹脂中挖取一凹槽，其利用不足的光反射呈現受影響 區。該等凹槽之深度通常係大約3〇至5〇 μηΐβ減小字母大 小之一主要限制係碎片沿著該等雷射凹槽之邊緣的堆疊。 上墨技術與雷射劃線技術皆係用於半導體裝置之標號， 該等裝置具有藉由通常引起具有一頂部的引線跨度棋形物 的引線接合技術或藉由覆晶附接技術而電連接至該基板、 引線框或該封裝内其他部分的半導體晶片。 申請者意識到現在朝向更小及更薄的半導體組件之市場 趨勢現需要在該封裝表面與該引線拱形物頂端間且有-厚 度為一或更小的化合物之封裝。只要該等接合引線頂 端緊雄接近該封裝頂面，則存在該劃線雷射束一直挖取凹 槽穿過該薄型封裝材料以曝露該等接合引線棋形物頂端之 尚風險。當此損壞發生時，該 裒置成為無用。因此，將用 面中㈣t接合晶片之裝置標號併入該封裝化合物之該表 知方法可造成超薄裝置之無法接受的故障發生 【發明内容】 本發明藉由提供一外部可 物塊體上製作標號，標記材料而不在封裝化合 定以槎供A极从祕* 料之先予反射特性可經選擇設 在匕併的標號標記而不損壞該封裝組態。 種形式中，一標記層一 ’、 封裝半導體、 材料之形式提供在一 置封裝之曝露表面上。該薄片可被放置在- 135484.doc 叩 5313 模製物中，舉例而言，在添加未固化模製化合物之前的晶 片封裝時放置在一引線接合晶片之引線上；或爾後可添加 於該模製化合物之頂端上。該薄片材料係藉由局部能量的 選擇施加經處理而提供具有一第一光學反射率及第一色彩 之區域，與具有一第二光學反射率及第二色彩之其他區域Step 6 has recorded the user's information for the identification and use of the device. Examples include device type and model, manufacturer, main performance characteristics and date ... w period. Representative label elements include numbers, letters, trademark symbols, punctuation, 唬, arrows, and similar readable labels. The most popular labeling technology is a profit. You use ink to imprint letters as small as 0.8 mm in height and use lasers – letters that are as small as 0.56 mm in height. In the inking technique, there is a color difference between the ink and the top surface of the package, which makes the label easy to sell. Contrast inks are deposited on the top surface of the package; for example, white ink is on a black epoxy molded package. The deposited ink forms a stack or stack on the surface of the package, which is different from the flat surface of the package. The limitation of the letter size is especially the blurring of the ink boundary and the risk of making the ink dirty. H ink cannot provide sufficient analysis. The degree of ink is marked for small packages to give excellent readability. In the laser scribing technique, there is a difference in the reflection of visible light, which makes the chain easy. shell. Laser scribing is particularly advantageous for packages made of plastic compounds. The package is typically fabricated by transfer molding techniques in the technique of the mold 135484.doc 1375313, which is selected to be obtained after polymerization. A shiny surface, so the surface has good visible light reflectance. The laser beam picks up a recess in the encapsulating resin that utilizes insufficient light reflection to present the affected area. The depth of the grooves is typically about 3 〇 to 5 〇 μη ΐ β. One of the reductions in letter size primarily limits the stacking of fragments along the edges of the laser grooves. Both inking techniques and laser scribing techniques are used for the designation of semiconductor devices having electrical connections by wire bonding techniques that typically result in a lead span chessboard having a top or by flip chip attachment techniques. A semiconductor wafer to the substrate, leadframe, or other portion of the package. Applicants are aware that the current trend toward smaller and thinner semiconductor components now requires a package of compounds having a thickness of one or less between the package surface and the top of the lead arch. As long as the top ends of the bond wires are close to the top surface of the package, there is a risk that the line laser beam will dig through the thin package material to expose the top ends of the bond wires. When this damage occurs, the device becomes useless. Therefore, the known method of incorporating the device label of the (4)-t-bonded wafer into the package compound can cause an unacceptable failure of the ultra-thin device. SUMMARY OF THE INVENTION The present invention is made by providing an external block. The labeling, marking material, and the pre-reflecting characteristics of the A-pole from the package can be selected to be labeled with the label without damaging the package configuration. In one form, a marking layer, a packaged semiconductor, or a material is provided on the exposed surface of the package. The sheet can be placed in a mold of -135484.doc 叩 5313, for example, placed on a lead of a wire bond wafer during wafer packaging prior to the addition of the uncured molding compound; or can be added to the mold later On top of the compound. The sheet material is treated to provide an area having a first optical reflectivity and a first color, and a second area having a second optical reflectivity and a second color.

形成對比。具有該第二反射率之該等區域以字母、數字、 標點符m、商標或其他可用於裝置標E的符號的形式提供 可讀標記。用於薄片材料化合物之較佳選擇包含〇甲酚酚 醛環氧樹脂及雙酚A ^咪唑化學物可被有利地添加至該膜 材料。一實例薄片厚度係介於大約丨與⑺μπι間。 本發明之實施例包含具有一連接至一基板之半導體晶片 之封裝裝置。在一實施例中，該連接係藉由接合引線形成 -具有-頂端的拱形物而實現。該晶片、該等引線拱形物 及該基板係、嵌人-封裝材料中，其接壤該附接頂端薄片， 因此該等拱形物頂端接觸該邊界。forms a contrast. The regions having the second reflectivity provide readable indicia in the form of letters, numbers, punctuation marks m, trademarks, or other symbols that can be used for device E. A preferred choice for the compound of the sheet material comprises a cresol novolac aldehyde epoxy resin and a bisphenol A ^ imidazole chemistry which can be advantageously added to the membrane material. An example sheet thickness is between about 丨 and (7) μπι. Embodiments of the invention include a package having a semiconductor wafer coupled to a substrate. In one embodiment, the attachment is achieved by bonding the leads to form an arch having a top end. The wafer, the lead arches, and the substrate system, the inlaid-encapsulated material, border the attachment tip sheet such that the top ends of the arches contact the boundary.

在另一實施例中，該連接係藉由倒裝該晶片並將具有積 體電路之4晶片表面上的該等金屬釘附接至該基板而實 現β無積體電路之該晶片表面向外且包含具有用於該裝置 標號的具有對比光學反射率及色彩之該等區域的該附接薄 本發明之另一實施例係一種用於製造一設備之方法。— 片具有一第一光學反射率之材料係放置在一半導體裝置之 平坦表面i;因此該薄片接觸該裝置並以其曝露的裸露表 面月向S亥裝置。接著’該裝置及該薄片之溫度被提高—段 I35484.doc Ϊ375313 時間以凝固該薄片與該裝置間的接觸；實例溫度係介於大 約170與25(TC間且實例時間係介於大約3〇與3〇〇秒間。接 著，-諸如來自一雷射的脈衝能量束係聚焦在該裸露薄片 表面之-點上·，該脈衝能量係藉由該材料吸收，因此將該 點之該第-反射率改變成為一不同於且與該第一反射率形 成對比的第二反射率。聚焦能量脈衝之步驟係在相鄰點上In another embodiment, the connection is achieved by flipping the wafer and attaching the metal pins on the surface of the wafer having the integrated circuit to the substrate. And including another embodiment of the invention having such areas of contrasting optical reflectivity and color for the device number, another embodiment of the invention is a method for fabricating a device. — A sheet of material having a first optical reflectivity is placed on a flat surface i of a semiconductor device; thus the sheet contacts the device and is exposed to the exposed surface of the device. [The temperature of the device and the sheet is then increased - paragraph I35484.doc Ϊ 375313 time to solidify the contact between the sheet and the device; the example temperature system is between about 170 and 25 (TC and the instance time is between about 3 〇) And 3 seconds. Then, a pulse energy beam such as from a laser is focused on the point of the surface of the bare sheet, the pulse energy is absorbed by the material, so the first reflection of the point The rate change becomes a second reflectance different from and contrasting with the first reflectance. The step of focusing the energy pulse is at an adjacent point

重複以形成具有第二反射率之區域，纟等係可讀為該設備 之標號。 本發月之另實施例係一種用於製造一半導體裝置之方 法。複數個半導體晶片係、藉由拱形物接合引線連接至一基 板條；該等接形物到達頂端。該條係放置在—模製空腔之 底部上’因此該等引線拱形物係從該底部向上導向。一片 具有-第-光學反射率之材料係放置在該模製物之平坦蓋 子上’因此該薄片面向該空腔。該蓋子係放置在該空腔上 以閉合該空腔。該模製物及該條之溫度係被提高且該模製 物係藉由-封裝化合物予以填充。因此，該晶片及該等引 線拱形物係嵌入該化合物中且該薄片係附接至該化合物。 i模製物蓋子係從該薄片被提升，藉此該附接薄片之該裸 露表面為曝露。如所陳述，該薄片具有-第-光學反射率 ^色彩。接著，—脈衝能量束係聚焦在該裸露薄片表面之 -點上，·該脈衝能量係藉由該材料吸收，因此將該點之該 第反射率改變成為一不同於且與該第—反射率形成對比 的-反射率。聚焦能量脈衝之步驟係在相 形成具有第二反射率之區域，宜…重複以 埤具等組成該裝置標號。若需 135484.doc 1375313 要，焊'料體係附接至該基板條用⑨連接至外部分 板條係被分離成為具有半導體晶片之離散裝置f 且該基 本發明之—技術優點係該裝置頂面上的薄片使用在吸收 “雷射脈衝之後經受色彩及反射改變而非蒸發或賤射的 匕合物。0此’該封裝頂面保持平坦且無碎片及由凹槽引 起的損壞，在已知技財存有曝露表面近於弓丨線棋形物之 風險。 一技術優點係本發明保持該裝置頂面之平坦性，因為本 發明之該符號標記方法避免墨水之沈積，其通常將墨水材 料堆積在該表面上，及避免具㈣由雷射標記引起的碎片 之堆疊體的凹槽之鑽取。因此，完全保持半導體封裝之寶 貴薄度及堆疊之適當性。 本發明之另一技術優點係標號之該方法係適用於批次處 理或晶片級封裝。因此，該裝置分離步驟可實施為船運之 前的最終步驟。 當結合隨附圖式及附屬請求項中闡明的新穎特點考慮 時，由本發明之若干實施例呈現的技術進步將可見於以下 對本發明之較佳實施例之描述》 【實施方式】 圖1顯示一作為本發明之一實施例的大體上指定為100的 半導體裝置。一經裝配的半導體晶片101係封裝在一聚合 化合物120中。化合物120之頂面上係一薄片13〇，其較佳 地係由一聚合材料（見下文）製成’其附接至並鄰近接觸封 裝化合物120。薄片130具有一表面130a，其係裸露且大致 135484.doc 1375313 上平坦。如圖1中表明，該封裝化合物與薄片13〇共用—邊 界 131。 該薄片130之該聚合材料係經選擇以提供具有一第—光 學反射率及一第一色彩之薄片。當一諸如聚焦的雷射光之 脈衝的能量脈衝，或另一高強度光源的能量脈衝照射在薄 片130之一點133上時，該能量主要係作為熱能被該點之材 料吸收，提升該點之溫度。該聚合材料局部改變其化學組 態，因此該經修改材料具有一不同於該未經改變組態之該 第一光學反射率及色彩之第二反射率及色彩，造成反射率 及色彩上的可見對比β對反射率及色彩之改變的主要影響 係一類似經燃燒樹脂的分子干擾◦然而，藉由吸收能量脈 衝引起的反射率及色彩之改變實質上未改變薄片表面13〇& 之平坦性，因此，不致形成凹槽且無碎片藉由該等能量脈 衝之吸收而堆積。 當連續脈衝橫向移動時，形成複數個點133 ’其等可排 列成一陣列。此等點形成由具有該第一反射率及色彩之該 等（第一）區域圍繞的具有第二光學反射率及色彩之（第二） 區域。忒等第二區域宜組態該等字母、數字、標點符號、 商標、捋號等，其等為用以識別及描述產品特徵所需，舉 例而δ，關於裝置類型、型號、性能資訊及原產地與製造 曰期等方面。 用於薄片130之適當的材料包含〇_甲酚酚醛環氧樹脂化 口物及雙盼Α化合物。此外，咪唑化學分子可被添加至此 等化合物。此等化合物係可從（例如）日本Nippon Steel 135484.doc 12 1375313Repeating to form a region having a second reflectivity, such as a device, can be read as a label for the device. Another embodiment of the present month is a method for fabricating a semiconductor device. A plurality of semiconductor wafer systems are connected to a substrate strip by arched bond wires; the contacts reach the top end. The strip is placed on the bottom of the molded cavity so that the lead arches are directed upwardly from the bottom. A piece of material having a -to-optical reflectivity is placed on the flat cover of the molded article' so that the sheet faces the cavity. The lid is placed over the cavity to close the cavity. The temperature of the molding and the strip is increased and the molding is filled by a potting compound. Thus, the wafer and the lead arches are embedded in the compound and the sheet is attached to the compound. The i molding cover is lifted from the sheet whereby the exposed surface of the attachment sheet is exposed. As stated, the sheet has a -first optical reflectance ^ color. Then, the pulse energy beam is focused on the point of the surface of the bare sheet, and the pulse energy is absorbed by the material, so the first reflectance of the point is changed to be different from and the first reflectance Contrast - reflectivity. The step of focusing the energy pulse is such that the phase forms a region having a second reflectance, and the device label is preferably composed of a cookware or the like. If 135484.doc 1375313 is required, the soldering material system attached to the substrate strip 9 is connected to the outer portion of the strip to be separated into a discrete device f having a semiconductor wafer and the technical advantage of the basic invention is the top surface of the device The upper sheet uses a composition that undergoes a change in color and reflection after absorption of the "laser pulse, rather than evaporating or squirting. 0" This top surface of the package remains flat and free of debris and damage caused by the groove, known The technique has the risk of exposing the surface to the shape of the bow. A technical advantage is that the present invention maintains the flatness of the top surface of the device because the symbol marking method of the present invention avoids the deposition of ink, which typically involves ink materials. Depositing on the surface and avoiding the drilling of the recesses of the stack of fragments caused by the (4) laser marks. Therefore, the valuable thinness of the semiconductor package and the suitability of the stack are completely maintained. Another technical advantage of the present invention The method of labeling is suitable for batch processing or wafer level packaging. Therefore, the device separation step can be implemented as the final step before shipping. The technical advances presented by the several embodiments of the present invention will be apparent from the following description of the preferred embodiments of the present invention. FIG. 1 shows an embodiment of the present invention as an embodiment of the present invention. A semiconductor device generally designated 100. An assembled semiconductor wafer 101 is encapsulated in a polymeric compound 120. The top surface of compound 120 is a sheet 13 〇 which is preferably made of a polymeric material (see below). It is attached to and adjacent to the contact encapsulation compound 120. The wafer 130 has a surface 130a that is bare and flat on substantially 135484.doc 1375313. As indicated in Figure 1, the encapsulation compound is shared with the flake 13〇-boundary 131. The polymeric material of the sheet 130 is selected to provide a sheet having a first optical reflectance and a first color. When an energy pulse such as a pulse of focused laser light, or an energy pulse of another high intensity source At a point 133 of the sheet 130, the energy is primarily absorbed as heat energy by the material of the point, raising the temperature at that point. The part changes its chemical configuration, so the modified material has a second reflectance and color different from the first optical reflectivity and color of the unmodified configuration, resulting in a visible contrast of the reflectivity and color. The main influence of the change in reflectance and color is a molecular interference similar to that of a burned resin. However, the change in reflectance and color caused by the absorption of energy pulses does not substantially change the flatness of the sheet surface 13〇& No grooves are formed and no debris is accumulated by absorption of the energy pulses. When the continuous pulses move laterally, a plurality of dots 133' are formed which may be arranged in an array. The dots are formed by having the first reflectivity and The (second) region of the (first) region of color having a second optical reflectivity and color. The second area should be configured with such letters, numbers, punctuation marks, trademarks, apostrophes, etc., etc., which are used to identify and describe the characteristics of the product, for example, δ, regarding device type, model, performance information and original Origin and manufacturing cycle. Suitable materials for the sheet 130 include bismuth cresol novolac epoxy resin and bismuth oxime compound. In addition, imidazole chemical molecules can be added to such compounds. These compounds are available, for example, from Nippon Steel, Japan 135484.doc 12 1375313

Chemical Company Ltd.購得。薄片13〇之較佳厚度範圍係 介於大約1至10 μηι間。 如圖1顯不，半導體晶片1〇1具有一厚度i〇ia(介於大約 100至小於300 μη^β1)。該晶片係藉由一聚合附接材料 103，較佳為一基於環氧樹脂或基於聚醯亞胺的黏合劑而 接至-基板1G2。基板1()2較佳為—藉由諸如聚酿亞胺之 • 絕緣材料製成的薄（舉例而言，大約30至70 μιη)片或帶， •包含導電跡線102a。或者，基板102可為-具有金屬段 的引線框。為了至外部零件之連接，該絕緣基板ι〇2具有 附帶焊料體104之塾。 晶片101具有用於電連接之終端110。在圖lt，該等終 端係藉由接合引線⑴之跨度而連接至該等基板跡線 ，該等引線形成拱形物以避免與該半導體晶片之該等 邊緣的意外接觸。該等拱形物包含頂端仙。 引線111之該等拱形物、該晶片1〇1及具有該等跡線⑻a • &lt;該基板側係嵌人—聚合材料中，其形成該裝配晶片之封 裝120且亦為該基板⑽提供堅固性β當裝置⑽係藉由一 模製技術製&amp;時，該封裝材料較佳為一基於環氧樹脂的模 .冑化合物。該封裝材料與該基板厚度-起的高度達到厚度 市場及產时趨勢係保持盡可能小的厚度^ 2卜減小厚 度⑵之努力包含使晶片厚度i〇u保持為小及該等引線頂 WHa保持為低之需求。厚度i2i與薄片⑽之厚度一起形 成裝置厚度132»各与·哲,, β該等拱形物頂端Ilia接近該邊界131 較佳為如圖1中所表明接觸該邊界Ui時，最佳維持 I35484.doc -13- 1^75313 使厚度13 2保持為小之努力。 圖2繪示數字及字母的實例標號之放大的俯視圖。在此 實例令，該薄片之聚合化合物具有__黑色及__發亮反射。 該等符號係由點組成，其等已吸收雷射脈衝且因此將其等 色彩改變為橙色。—更近的檢查揭示該點具有一糙面反 射在此實例中’該等字母及數字之真實高度為大約〇5 mm 〇 圖3顯不用於一大體上標明為3〇〇的具有倒裝晶片3〇1之 半導體裝置的本發明之另一實施例。包含電活性成分的該 晶片表面30la具有終端303，其等係藉由金屬凸點3〇2連接 至該基板3 05之各自的接觸墊3〇4。金屬凸點3〇2可為通常 為基於錫的焊料球的回焊體，或由金屬或合金製成的凸 點，其在半導體裝配溫度下不回復流動。較佳的金屬包含 金、銅或其等之合金》該晶片與該基板間的間隙及該等接 觸點間的空間較佳地係藉由塑膠材料306(稱為側填滿化合 物）予以填充以便減輕該等接觸點上的熱機械應力。基板 305可具有經附接的焊料球3〇7以便提供附接至外部零件。 如圖3所描繪’該晶片表面301b係遠離該等金屬凸點且 為完全平坦。附接至平坦表面3011}的係一聚合化合物之薄 片3 3 0，其具有一化學組態為該化合物給予一色彩及—光 學反射率。薄片330係完全接觸表面30lb且具有一裸露並 大致上平坦的表面330a，其無凹痕或凹槽，且亦無外來材 料（諸如墨水或標記物質）之沈積。 薄片330包含若干具有一第一光學反射率及色彩之第_ 135484.doc ^/5313 區域331 ’及若干具有一第二光學反射率及色彩之第二區 域332。該第二反射率及色彩不同於且與該第一反射率及 色办形成對比。該等第二區域係由點組成，其等以一局部 改變的化學組態展示薄片330之化合物，導致與具有該未 改變化合物組態之該等點關於色彩及光學反射率之對比。 該色彩及反射率改變之一主要影響來自一類似燃燒樹脂之 刀子干擾。如以上敍述，該改變的化合物組態較佳地係由 聚焦此量之脈衝引起，例如照射在薄片330之區域332之 一點上的聚焦雷射光。該能量脈衝係作為暫態熱能被該點 之材料吸收，提升該點之臨時溫度。或者，可使用一熱能 脈衝。 圖4至6描繪根據本發明之另一實施例的該裝置製造之步 驟。在圖4中，401表示一片具有一第一光學反射率及色彩 之材料，且402表示一條經裝配及封裝的半導體裝置。較 佳地，該薄片401係介於大約1與丨〇 μιη間厚且係由一選自 一包含〇-甲酚酚醛環氧樹脂化合物及雙酚Α化合物，更佳 地包含咪嗤化學分子之基的聚合化合物組成。該半導體裝 置條402包含基板條412，其在圖4中係顯示為具有金屬接 觸墊412b的由一絕緣材料（例如聚醯亞胺，與導電跡線整 合）製成的帶412a。或者’基板條412可為一金屬引線框。 在圖4中所繪示的該較佳實施例中，安裝在基板條412上 的該等半導體晶片420係藉由接合引線421連接至該基板。 該專接合引線42 1之引線跨度形成包含一頂端422之棋形 物。晶片420及引線421係嵌入封裝化合物430中，其具有 135484.doc 15 1375313 一大致上平坦的表面431。較佳地，封裝化合物43〇係一基 於環氧樹脂的模製化合物。該封裝化合物厚度與基板 之厚度一起決定裝置條4〇2之總厚度403。以上強調市場趨 勢更青睞小厚度403。因此，較佳的係使該等引線拱形物 保持為低並使该等棋形物頂端422極接近化合物43〇之表面 431。表面431上的薄片401之附接容許該等拱形物422實際 上接觸表面431·本發明之一技術優點。 圖5繪示將薄片401放置在該封裝化合物43〇之該平坦表 面431上的製程步驟，薄片4〇1係接觸該化合物表面431， 而該薄片之該裸露表面背向化合物43〇且成為新的裝置表 面501。將薄片4〇1附接至該裝配條4〇2上之步驟之後，將 該組合裝置之溫度提升一段時間以凝固該薄片與該裝配條 間的接觸。.较佳地，該提升的溫度係在完全聚合該封裝化 合物430所需的溫度範圍内，該封裝化合物可在圖$之該製 紅步驟之初僅被部分聚合。一適當的溫度範圍係介於1 與180°C間；一適當的時間係介於1〇與6〇秒間。 圖6描繪將一脈衝能量束6〇1聚焦在該裸露薄片表面5〇ι 之點610上的製程步驟。一較佳的能量束係一1至3 w YAG雷射（1G24 nm) ; _替代能量源為紫外光。該脈衝能量 係由該薄片材料吸收；#改變其化學組態，類似於熱處理 或燃燒樹脂。亦可存在一包含於此改變中的輕微的體膨 脹《該點之該原始第-反射率及色彩被改變至一不同於該 第-反射率及色彩的第二反射率及色彩，導致一可見對 比。 135484.doc 16- 1375313 如圖6中所表明，聚焦一脈衝能量束之製程步驟係在薄 片材料之相鄰點610上重複，以便形成具有該第二反射率 及色毛之第一區域。此等第二區域可經排列使得其等組成 如字母及數字的符號，傳達關於該裝置之資訊，例如裝置 類型、型號、性能資訊及製造之起源與時&amp;卜所有此等資 訊係併入該標記薄片40丨中。 圖6中進步表明的係將焊料體620附接至該基板條之製 程步驟，其等提供連接至外部零件。作為最終步驟，該完 成的裝置條可被分離成為包含半導體條之離散裝置。一較 佳的分離方法係沿著切割線63〇鋸切。 圖7及8描繪根據本發明之另一實施例的該裝置製造之步 驟。在圖7中，一模製空腔之部分係藉由描繪該鋼底部模 製部分701及該鋼模製蓋子7〇2而顯示。在該模製空腔之底 部上已放置一具有金屬墊711之基板條71〇，其上已裝配複 數個具有金屬終端720a之半導體晶片72〇。該等晶片終端 720a已藉由從該等終端至該等墊之拱形物接合引線721連 接至該等基板墊7n，藉此該等拱形物到達頂端722。當該 條7 10已被放置在該模製空腔之該底部70 1上時，該等引線 拱形物722係從該空腔底部向上導向。 圖7中進一步繪示將一表示為4〇1之薄片平坦地放置在該 模製蓋子上的製程步驟。較佳地，該薄片4〇1係介於大約1 與1 〇 μιη間厚且係由一選自一包含〇_曱酚酚醛環氧樹脂化 合物及雙酚Α化合物，更佳地包含咪唑化學分子之基的聚 合化合物予以組成。薄片401之該化合物係稱為第一聚合 135484.doc •17- 1375313 化。物，以便區分其與用以填充該模製空腔之第二聚合化 合物；見下文。該第一化合物具有一(第一)光學反射率及 色彩。當放置在該蓋子702上時，薄片4〇1面向該模製空 腔。 、二 在圖8繪示的下一製程步驟中，具有該薄片4〇ι之該模製 蓋子702係降低至該模製空腔上，較佳地係直至薄片4〇'丨接 觸該等裝配晶片720之該等拱形物頂端722。接著，該模製 空腔係藉由一第二聚合化合物43〇填充，因此該等晶片 及該等引線拱形物72丨、722係嵌入該第二化合物中且該第 二化合物430接觸該薄片401。較佳地，封裝化合物4^係 一基於環氧樹脂的模製化合物，為了適當的黏性，其需要 一大約175°C的模製溫度。 當該模製冷卻且該封裝化合物43〇之該聚合製程開始 時，薄片401與化合物430間的接觸凝固。因此，薄片4〇1 附接至化合物430 ’该等引線之該等拱形物頂端722可接觸 薄片4〇1與化合物430間的邊界。由此，可自該薄片提升模 製蓋子702，曝露該薄片之裸露表面。 下一製程步驟係類似於圖6中所顯示的該步驟。一脈衝 能量束係聚焦在該裸露薄片表面之一點上。一較佳的能量 束係一 ！至3 W YAG雷射（1024 nm); 一替代能量源為紫外 光。該脈衝能置係由該溥,片材料吸收；其改變其化學組 態’類似於熱處理或燃燒樹脂。亦可存在一包含於此改變 中的輕微的體膨脹。δ玄點之S亥原始第一反射率及色彩被改 變至一不同於該第一反射率及色彩的第二反射率及色彩， 135484.doc 1375313 導致一可見對比β 聚焦-脈衝能量束之製程步驟係在薄片材料之相鄰點上 重複以便t成具有該第二反射率及色彩之第二區域。此 等第二區域可經排列使得其等組成如字母及數字元的符 傳達關於該裝置之資訊’例如裝置類型、型號、性能 另訊及製造之起源與時間。 焊料體可附接至該基板條：其等提供連接料部零件。 或者’該基板之該等接㈣可用於至外部零件之壓強接 觸。作為最終步驟’舉例而言，該完成的袭置條可藉由鑛 切破分離成為包含半導體條之離散裝置。 本發明適用於任何類型的半導體晶片、離散或積體電 路，且該半導體晶片之材料可包含石夕、石夕錯、碎化録或用 於積體電路製造的任何其他半導體或化合物材料。 本發明亦適用於裝置，其中一雷射脈衝可造成該標記薄 片之巴出，其中凸出高度係與該薄片厚度同級，且本發明 亦適用於-凸出寬度為該凸出高度的大約6至8倍的情況。 在任-情況下，-利用本發明實現的符號之大小可更小於 «0.5 _)藉由一習知的技術（切割凹槽為大約3〇至5〇㈣ 深）所實現的符號大小。 熟習此項技術者將瞭解存在許多其他可能的變更及實施 例係在所主張的本發明之範圍内。 【圖式簡單說明】 、，圓！顯示-具有-半導體晶片之薄型裝置之橫截面，該 半導體晶片係引線裝配在一基板上且藉由一平頂薄片封裝 I35484.doc 1375313 用於由嵌人區域組成的標號，其在吸收高強度能量脈衝之 後相對於周圍材料在色彩及光學反射率上形成對比。 圖2繪示一裝置上的薄片材料之放大俯視圖其中該材 料包含相對於周圍材料在色彩與光學反射率上形成對比的 耿入點之陣列以便形成該裝置標號。 圖3顯示一具有倒裝在一基板上的半導體晶片之主動表 面之裝置的示意性的橫截面，其中該被動晶片表面包含一 片材料用於該裝置標號，其係由在已吸收高強度能量脈衝 之後相對於該周圍材料在色彩及光學反射率上形成對比的 嵌入點組成。 圖4至6描繪·根據本發明之一實施例的該裝置製造之步 驟。 圖4顯示一基板條之示意性的橫截面，其包含藉由拱形 物引線接合連接至該基板並嵌入在一具有一平坦表面的封 裝化合物（舉例而言’模製化合物）中的晶片，其中該等拱 形物之頂端接壤該封裝表面。一片材料係經提供以附接至 該封裝表面。 圖5係圖4之該封裝基板條在將該薄片附接至該封裝表面 之後的一示意性的橫截面，其在該薄片與該封裝化合物間 形成一邊界。 圖6係圖5之該基板條在將焊料體附接至該基板之後的— 示意性的橫截面，其繪示用以改變該薄片材料中若干點的 光學反射率及色彩，造成一與該未改變的反射率及色彩形 成對比的改變的反射率及色彩之能量脈衝（舉例而言，雷 135484.doc -20- 1375313 射脈衝）。 圖7及8描繪根據本發明之另一實施例的該裝置製造之舟 驟。 / 圖7顯示-基板條之示意性的橫戴面，其包含藉由拱形 物引線接合連接至該基板之晶片，該條係定位在—模製空 腔之底部上。該模製蓋子具有—附接至並易於降低以接: 該模製之薄片。 圖8係圖7之該基板條在一起降低該模製蓋子與該薄片之 後的示意性的橫截面；在此實例中，f亥薄片接觸該等拱形 物頂端。該模製空腔已藉由模製化合物予以填充因此該 化合物係鄰近該薄片。 / 【主要元件符號說明】 100 半導體裝置 101 半導體晶片 101a 厚度 102 基板 102a 導電跡線 103 聚合附接材料 104 焊料體 110 終端 111 接合引線 111a 頂端 120 聚合化合物 121 厚度 135484.doc -21 - 1375313Purchased by Chemical Company Ltd. The preferred thickness range of the sheet 13 is between about 1 and 10 μηι. As shown in Fig. 1, the semiconductor wafer 101 has a thickness i 〇 ia (between about 100 and less than 300 μη^β1). The wafer is attached to the substrate 1G2 by a polymeric attachment material 103, preferably an epoxy based or polyimide based adhesive. The substrate 1() 2 is preferably a thin (for example, about 30 to 70 μm) sheet or tape made of an insulating material such as polyimide, and includes conductive traces 102a. Alternatively, substrate 102 can be a leadframe having a metal segment. The insulating substrate 〇2 has a defect with the solder body 104 for connection to an external component. Wafer 101 has a terminal 110 for electrical connection. In Figure lt, the terminals are connected to the substrate traces by the span of the bond wires (1) which form the arches to avoid accidental contact with the edges of the semiconductor wafer. The arches contain apex. The arches of the leads 111, the wafers 1〇1, and the traces (8)a•&lt;the substrate-side embedded human-polymerized material, which form the package 120 of the assembled wafer and also provide the substrate (10) Ruggedity β When the device (10) is made by a molding technique, the encapsulating material is preferably an epoxy resin-based mold compound. The height of the package material and the thickness of the substrate reaches the thickness market and the trend of the production time is kept as small as possible. 2 The effort to reduce the thickness (2) involves keeping the wafer thickness i〇u small and the lead tops WHa Keep the demand low. The thickness i2i together with the thickness of the sheet (10) forms a device thickness 132»each and zh,, and the arch tops Ilia are close to the boundary 131. Preferably, when the boundary Ui is contacted as indicated in Fig. 1, the I35484 is optimally maintained. .doc -13- 1^75313 Keep the thickness of 13 2 small. 2 is an enlarged top plan view of an example number of numbers and letters. In this example, the polymeric compound of the sheet has __black and __bright reflection. These symbols are composed of dots that have absorbed the laser pulse and thus change their color to orange. - A closer inspection reveals that the point has a matte reflection. In this example, the true height of the letters and numbers is approximately 〇5 mm. Figure 3 is not used for a flip-chip wafer generally designated 3 〇〇. Another embodiment of the invention of a semiconductor device of 3-1. The wafer surface 30la containing the electroactive component has a terminal 303 which is connected to the respective contact pads 3〇4 of the substrate 305 by metal bumps 3〇2. The metal bumps 3〇2 can be reflow bodies, typically tin-based solder balls, or bumps made of metal or alloy that do not return to flow at the semiconductor assembly temperature. Preferably, the metal comprises gold, copper or the like. The gap between the wafer and the substrate and the space between the contacts are preferably filled by a plastic material 306 (referred to as a side filled compound). Reduce thermo-mechanical stresses at these points of contact. Substrate 305 can have attached solder balls 3〇7 to provide attachment to external parts. As depicted in Figure 3, the wafer surface 301b is remote from the metal bumps and is completely flat. A sheet of polymeric compound, attached to flat surface 3011}, has a chemical configuration that imparts a color and optical reflectance to the compound. Sheet 330 is in full contact with surface 30lb and has a bare and generally flat surface 330a that is free of dents or grooves and that is free of deposition of foreign materials such as ink or marking materials. Sheet 330 includes a plurality of first 135484.doc ^/5313 regions 331 ' having a first optical reflectivity and color and a plurality of second regions 332 having a second optical reflectivity and color. The second reflectivity and color are different and contrasted with the first reflectivity and color. The second regions are comprised of dots which, in a partially modified chemical configuration, exhibit compounds of the sheet 330, resulting in a comparison of color and optical reflectivity with such points having the configuration of the unchanged compound. One of the changes in color and reflectivity primarily affects knife interference from a similar burning resin. As described above, the altered compound configuration is preferably caused by a pulse that focuses on this amount, such as focused laser light that illuminates at a point 332 of the region 330 of the sheet 330. The energy pulse is absorbed as transient thermal energy by the material of the point, raising the temporary temperature at that point. Alternatively, a thermal pulse can be used. 4 through 6 depict the steps of fabricating the device in accordance with another embodiment of the present invention. In Fig. 4, 401 denotes a piece of material having a first optical reflectivity and color, and 402 denotes an assembled and packaged semiconductor device. Preferably, the sheet 401 is between about 1 and 丨〇μιη thick and is selected from the group consisting of a cresol-cresol novolac epoxy resin compound and a bisphenol hydrazine compound, and more preferably contains a quinone chemical molecule. The composition of the polymeric compound of the group. The semiconductor device strip 402 includes a substrate strip 412, shown in Figure 4 as a strip 412a having a metal contact pad 412b made of an insulating material (e.g., polyimide, integrated with conductive traces). Alternatively, the substrate strip 412 can be a metal lead frame. In the preferred embodiment illustrated in Figure 4, the semiconductor wafers 420 mounted on the substrate strip 412 are attached to the substrate by bond wires 421. The lead span of the dedicated bond lead 42 1 forms a chevron that includes a top end 422. Wafer 420 and leads 421 are embedded in a potting compound 430 having a substantially flat surface 431 of 135484.doc 15 1375313. Preferably, the encapsulating compound 43 is a molding compound based on an epoxy resin. The thickness of the potting compound, together with the thickness of the substrate, determines the total thickness 403 of the strips 4〇2. The above emphasizes that the market trend favors a small thickness of 403. Accordingly, it is preferred that the lead arches be kept low and the top ends 422 of the chevrons are in close proximity to the surface 431 of the compound 43. The attachment of the sheet 401 on the surface 431 allows the arches 422 to actually contact the surface 431. One of the technical advantages of the present invention. FIG. 5 illustrates a process of placing a sheet 401 on the flat surface 431 of the potting compound 43. The sheet 4〇1 contacts the surface 431 of the compound, and the exposed surface of the sheet faces away from the compound 43 and becomes new. Device surface 501. After the step of attaching the sheet 4〇1 to the fitting strip 4〇2, the temperature of the combining device is raised for a period of time to solidify the contact between the sheet and the fitting strip. Preferably, the elevated temperature is within the temperature range required to completely polymerize the encapsulating compound 430, and the encapsulating compound is only partially polymerized at the beginning of the red forming step of Figure 00. A suitable temperature range is between 1 and 180 ° C; an appropriate time period is between 1 and 6 sec. Figure 6 depicts a process step of focusing a pulsed energy beam 6〇1 at a point 610 of the exposed sheet surface 5〇. A preferred energy beam is a 1 to 3 w YAG laser (1G24 nm); the _ alternative energy source is ultraviolet light. The pulse energy is absorbed by the sheet material; #change its chemical configuration, similar to heat treatment or combustion of the resin. There may also be a slight body expansion included in the change "the original first reflectance and color of the point is changed to a second reflectance and color different from the first reflectance and color, resulting in a visible Compared. 135484.doc 16- 1375313 As shown in Figure 6, the process of focusing a pulsed energy beam is repeated at an adjacent point 610 of the sheet material to form a first region having the second reflectivity and color. The second regions may be arranged such that they are composed of symbols such as letters and numbers, conveying information about the device, such as device type, model, performance information, and origin and timing of manufacture &amp; The marking sheet 40 is in the center. The improvement shown in Figure 6 illustrates the process of attaching the solder body 620 to the substrate strip, which provides connection to the external component. As a final step, the finished device strip can be separated into discrete devices comprising semiconductor strips. A preferred separation method is sawing along the cutting line 63. Figures 7 and 8 depict the steps of fabricating the device in accordance with another embodiment of the present invention. In Fig. 7, a portion of a molded cavity is shown by depicting the steel bottom molding portion 701 and the steel molded cover 7〇2. A substrate strip 71 having a metal pad 711 having a plurality of semiconductor wafers 72 having metal terminals 720a mounted thereon is placed on the bottom of the molding cavity. The wafer terminals 720a have been connected to the substrate pads 7n by arching bond wires 721 from the terminals to the pads, whereby the arches reach the top end 722. When the strip 7 10 has been placed on the bottom 70 1 of the molding cavity, the lead arches 722 are directed upward from the bottom of the cavity. Further illustrated in Fig. 7 is a process step of flatly placing a sheet designated as 4〇1 on the molded lid. Preferably, the sheet 4〇1 is thick between about 1 and 1 〇μηη and is selected from a cerium-containing phenolic phenolic epoxy resin compound and a bisphenol hydrazine compound, and more preferably contains an imidazole chemical molecule. The base of the polymeric compound is composed. This compound of sheet 401 is referred to as the first polymerization 135484.doc • 17-1375313. To distinguish between it and the second polymeric compound used to fill the molding cavity; see below. The first compound has a (first) optical reflectivity and color. When placed on the cover 702, the sheet 4〇 faces the molding cavity. 2, in the next process step illustrated in FIG. 8, the molded cover 702 having the sheet 4〇 is lowered onto the molding cavity, preferably until the sheet 4〇'丨 contacts the assembly. The arched ends 722 of the wafer 720. Then, the molding cavity is filled by a second polymer compound 43, so that the wafers and the lead arches 72, 722 are embedded in the second compound and the second compound 430 is in contact with the sheet. 401. Preferably, the encapsulating compound 4 is an epoxy resin based molding compound which requires a molding temperature of about 175 ° C for proper adhesion. When the molding is cooled and the encapsulating compound 43 is started, the contact between the sheet 401 and the compound 430 is solidified. Thus, the tabs 722 attached to the compound 430' of the leads 722 of the leads can contact the boundary between the sheet 4〇1 and the compound 430. Thus, the cover 702 can be lifted from the sheet to expose the exposed surface of the sheet. The next process step is similar to the step shown in Figure 6. A pulsed energy beam is focused at a point on the surface of the bare sheet. A better energy beam system! Up to 3 W YAG laser (1024 nm); an alternative energy source is UV light. The pulse can be absorbed by the crucible, the sheet material; it changes its chemical composition 'similar to heat treatment or combustion of the resin. There may also be a slight body expansion included in this change. The original first reflectance and color of the δ Xuan point are changed to a second reflectance and color different from the first reflectance and color, 135484.doc 1375313 results in a visible contrast β focus-pulse energy beam process The step is repeated at adjacent points of the sheet material to form a second region having the second reflectivity and color. The second regions may be arranged such that their constituents such as letters and digits convey information about the device&apos; such as device type, model, performance, and origin and time of manufacture. A solder body can be attached to the substrate strip: it provides a connecting part part. Alternatively, the connections (4) of the substrate can be used for pressure contact to external parts. As a final step&apos;, for example, the finished shooter can be separated into discrete devices comprising semiconductor strips by mine shearing. The invention is applicable to any type of semiconductor wafer, discrete or integrated circuit, and the material of the semiconductor wafer may comprise any other semiconductor or compound material used in the fabrication of integrated circuits. The invention is also applicable to a device in which a laser pulse causes the marking sheet to be ejected, wherein the projection height is of the same level as the thickness of the sheet, and the invention is also applicable to - the projection width is about 6 of the projection height Up to 8 times the situation. In any case, the size of the symbol implemented with the present invention may be less than <0.5 _) by a conventional technique (the cutting groove is about 3 〇 to 5 〇 (4) deep). Those skilled in the art will recognize that many other possible variations and embodiments are within the scope of the claimed invention. [Simple description of the picture],, round! Display - a cross section of a thin device having a semiconductor wafer, the semiconductor wafer is mounted on a substrate and packaged by a flat top sheet I35484.doc 1375313 for markings consisting of embedded regions, which absorb high intensity energy The pulse is contrasted with the surrounding material in terms of color and optical reflectivity. 2 is an enlarged plan view of a sheet material on a device wherein the material comprises an array of indentation points that are contrasted in color and optical reflectivity with respect to surrounding material to form the device designation. 3 shows a schematic cross section of a device having an active surface of a semiconductor wafer flip-chip mounted on a substrate, wherein the passive wafer surface comprises a piece of material for the device designation, which is pulsed at a high intensity energy that has been absorbed A contrasting embedding point composition is then formed on the color and optical reflectivity relative to the surrounding material. 4 through 6 depict the steps of fabricating the device in accordance with an embodiment of the present invention. 4 shows a schematic cross section of a substrate strip comprising a wafer bonded to the substrate by an arch wire and embedded in a potting compound (eg, a 'molding compound) having a flat surface, Wherein the top end of the arches borders the surface of the package. A piece of material is provided to attach to the surface of the package. Figure 5 is a schematic cross section of the package substrate strip of Figure 4 after attaching the sheet to the surface of the package, forming a boundary between the sheet and the potting compound. Figure 6 is a schematic cross-sectional view of the substrate strip of Figure 5 after attaching the solder body to the substrate, illustrating the optical reflectivity and color used to change points in the sheet material, resulting in The unaltered reflectivity and color contrast contrast to the altered reflectance and color energy pulses (for example, Ray 135484.doc -20-1375313 shot pulse). Figures 7 and 8 depict a boat for the manufacture of the device in accordance with another embodiment of the present invention. / Figure 7 shows a schematic cross-face of a substrate strip comprising a wafer bonded to the substrate by an arch wire, the strip being positioned on the bottom of the molded cavity. The molded cover has - attached to and is easily lowered to: the molded sheet. Figure 8 is a schematic cross-sectional view of the substrate strip of Figure 7 after the molded lid and the sheet are lowered; in this example, the sheet is in contact with the top end of the arch. The molded cavity has been filled with a molding compound so that the compound is adjacent to the sheet. / [Main component symbol description] 100 Semiconductor device 101 Semiconductor wafer 101a Thickness 102 Substrate 102a Conductive trace 103 Polymeric attachment material 104 Solder body 110 Terminal 111 Bonding lead 111a Top 120 Polymer compound 121 Thickness 135484.doc -21 - 1375313

130 薄片 130a 薄片表面 13 1 邊界 132 裝置厚度 133 點 300 半導體裝置 301 倒裝晶片 301a 晶片表面 301b 晶片表面 302 金屬凸點 303 終端 304 接觸墊 305 基板 306 塑膠材料 307 焊料球 330 薄片 330a 薄片表面 331 第一區域 332 第二區域 401 薄片 402 半導體裝置條 403 裝置之總厚度 412 基板條 412a 帶 135484.doc -22- 1375313130 sheet 130a sheet surface 13 1 border 132 device thickness 133 point 300 semiconductor device 301 flip chip 301a wafer surface 301b wafer surface 302 metal bump 303 terminal 304 contact pad 305 substrate 306 plastic material 307 solder ball 330 sheet 330a sheet surface 331 A region 332 second region 401 sheet 402 semiconductor device strip 403 total thickness of the device 412 substrate strip 412a with 135484.doc -22- 1375313

412b 金屬接觸墊 420 半導體晶片 421 接合引線 422 頂端 430 封裝化合物 431 表面 501 新的裝置表面 601 點 610 相鄰點 620 焊料體 630 切割線 701 鋼底部模製部分 702 鋼模製蓋子 710 基板條 711 金屬墊 720 半導體晶片 720a 金屬終端 721 接合引線 722 頂端 I35484.doc -23-412b Metal Contact Pad 420 Semiconductor Wafer 421 Bonding Lead 422 Top 430 Package Compound 431 Surface 501 New Device Surface 601 Point 610 Adjacent Point 620 Solder Body 630 Cutting Line 701 Steel Bottom Molded Portion 702 Steel Molded Cover 710 Substrate Strip 711 Metal Pad 720 Semiconductor Wafer 720a Metal Terminal 721 Bonding Lead 722 Top I35484.doc -23-

Claims (1)

1. 第097140035號專利申請案 ㈣月5曰修正 申請專利範圍·· ♦文尹請專利範圍替換本(101年8月) 一基板； -種半導體封裝設備，其包括： 1 ~— 板之一半？，其具有藉由複數個接合線連接至該基 -封裝材料、封=接合線具有包含頂部的棋形，· 該複數個拱形以及該基板：囊：該晶片、該等接合線之 被封襄之㈣導體裝置之—平坦表面面該封裝材料並形成 咳平薄片’其係附接至被封裝之該半導體裝置之 »十一表面，該聚合物薄片具有一 薄片包含若干具有一第一：面，該聚合物 予反射率之第一區域及若干 =第二反射率之第二區域；其中該第二反射率不同 =第-反射率且與其形成對比，其中該等第二區域在 -有從該聚合物薄片增加或損失任何材料的情形下已經 歷過一分子干擾以製造該等第二區域； 其中該等接合線之該複數個拱形之頂部接觸被封裝之 該半導體裝置之該平坦表面’其中該平坦表面與該被附 接之該聚合物薄片毗鄰。 2，如請求項1之設儀，其中該半導體晶片具有若干金屬釘 接附至該基板，其中在該等金屬釘相對之被封裝之該半 導體裝置之一表面係被封裝之該半導體裝置之該平坦表 面。 3.如請求W之設備，其中該等第二區域組成傳達關於該 裝置之資訊的若干符號。 135484-10108l7.doc 1375313 月求項1之执備，其中該薄片具有介於大約1至10从m間 的厚度。 5.如請求項！之設備，其中該薄片係由一選自—由。·甲㈣ 醛環氧樹脂及雙酚A組成之群的聚合化合物所製成。 6_如請求項5之設備，其中該聚合化合物進—步包含化學 分子咪。坐。 7. 如請求項6之設備，其中該聚合化合物操作以在吸收一 光能或熱能之脈衝之後將該第一光學反射率改變至該第 二光學反射率。 ^ 8. 如請求項5之設備，其中該等第一區進一步具有一第一 色彩以及該等第二區1有一笫-由必甘 ^ 弟一色如，其中該第二色彩 不同於該[色彩，且其中該聚合化合物進—步操作以 在吸收一光能或熱能之脈衝之後改變該第—色彩成該第 二色彩。 / 以 9· -種用於製造-半導體封裝設備之方法，其包括以 驟： 將一片具有一第一光學反射率之材料放置在一半導體 裝置之-平坦表面上’藉此該薄片接觸該裝置且該薄片 之一裸露表面背向該裝置； 將該裝置及該薄片之溫度提升一段時間以凝固該薄片 與該裝置間的接觸； 將一脈衝能量束聚焦在該裸露薄片表面之一點上使得 該脈衝能量被該材料吸收，因此將該點之—第—反射率 改變至一不同於該第一反射率之第二反射率；及 135484-1010817.doc 1375313 以形成若 在若干相鄰點上重複聚焦能量脈衝之該步驟 干具有該第二反射率之區域。 項9之方法，其具有介於大約…一間 U.如：求項9之方法，其中該薄片係由-選自-由。·甲酚酚 越垓氧樹脂及雙酚A組成之群的聚合化合物所製成。 12.如明求項U之方法，其十該聚合化合物進一步包含化學 分子咪唑。 ^ G 3化予 13. -種用於製造一半導體裝置之方法，其包括以下步驟·· 藉由換形接合引線將複數個半導體晶片連接至一基板 條’該等换形物到達頂端； 將該條放置在一模製空腔之底部上，因此該等引線拱 形物係從該底部向上導向； ，將4纟有一帛學反射率之材料放置在該模之該 平坦蓋子上，因此該薄片面向該空腔； 將該蓋子放置在該空腔上以閉合該空腔； 提升該模及該條之溫度； 利用一封裝化合物填充該模空腔，因此將該等晶片及 該等引線拱形物嵌入該化合物中並將該薄片附接至該化 合物； 自该薄月提升該模蓋子，因此曝露該附接薄片之裸露 表面； 將一脈衝能量束聚焦在該裸露薄片表面之一點上使得 該脈衝能量被該材料吸收，因此將該點之該第一反射率 135484-10108l7.doc 1375313 14. 改變至一不同於該第一反射率之第二反射率丨及 在若干相鄰點上重複聚焦能量脈衝之步驟以形 具有第二反射率之區域。 如。月求項13之方法，其進一步包含以下步驟. 將若干焊料體附接至該基板條用於至各外部零件之連 接；及 15. 將該基板條分離成為若干具有丰逡 句干導體晶片之離散 〇 -種用於製造一半導體裝置之方法，其包括以下步驟. 將複數個半導體晶片裝配在-基板條上，該等晶片1 有若干金屬終端且該基板具有若干金屬墊； 八 藉由從該等終端至該等塾之若干棋形物接合引線㈣ 等終端連接至該等墊，該等拱形物到達頂端； 將該條放置在一模空腔之麻# u 腔之底部上，因此該等引線拱形 物係從該底部向上導向； 將一第-聚合化合物之-薄片平坦放置在該模蓋子 上’因此該薄片面向該空腔，該化合物具有一光學反射 率； *將具有該薄片之該模蓋子降低至該模空腔上，直至該 薄片接觸該等裝配晶片之該等拱形物頂端·， 利用第_聚合化合物填充該模空腔，因此該等晶片 及該等引線拱形物係嵌人該第二化合物中且該第二化合 物接觸該薄片； 在聚合該第二化合物時凝固該薄片與該第二化合物間 置 裝 135484-1010817.doc 1375313 該第一化合物； 因此曝露該薄片 的接觸，因此將該薄片附接至 之裸露表 自該薄片提升該模蓋子， 面； ，-脈衝能量束聚焦在該裸露薄片表面之— 6亥脈衝能量被該第-化合物吸收，因此將該點之該第： 反射：改變至一不同於該第一反射率之第二反射率^ 在若干相鄰點上重福炉隹 董複聚焦旎罝脈衝之步驟以形成若干 ，、有第二反射率之區域；及 置將該基板條分離成為若干具有半導體晶片之離散裝 16, 一種半導體封裝設備，其包含： 具有模製複合物之一平坦表面的一半導體裝置； 一聚合㈣片’其黏附至該平坦表面且係與該平坦表 面共同擴張的； 在該平坦表面上可見的複數個區域，其在沒有從該薄 片增加或損失任何材料的情形下已經歷過一分子干擾以 留下若干印記；以及 半導體晶片，其利用一接合線連接至一基板，其該 從該模製複合物被曝露並接觸該聚合物薄片。 17. 如請求項16之設備，其中該複數個區域具有由該分子干 擾所製造的截然不同的反射率。 18·如請求項16之設備，其中該複數個區域具有由該分子干 擾所製造的截然不同的色彩。 135484-1010817.doc1. Patent Application No. 097140035 (IV) Month 5曰 Amendment of Patent Application Scope ♦ Wen Yin Please Replace the Patent Scope (August 101) A substrate; - A semiconductor packaging device, including: 1 ~ - one half of the board ? And having a plurality of bonding wires connected to the base-package material, the sealing wire has a chevron shape including a top portion, the plurality of arches, and the substrate: the capsule: the wafer, the bonding wires are sealed (4) the flat surface of the conductor device, the encapsulating material and forming a cough sheet, which is attached to the surface of the packaged semiconductor device, the polymer sheet having a sheet containing a plurality of first: a first region of the polymer pre-reflectance and a second region having a plurality of second reflectances; wherein the second reflectance is different = the first reflectance and in contrast thereto, wherein the second regions are in- One molecule of interference has been experienced to create the second regions from the addition or loss of any material of the polymer sheet; wherein the top portions of the plurality of arches of the bond wires contact the flat of the packaged semiconductor device The surface 'where the flat surface is adjacent to the attached polymer sheet. 2. The apparatus of claim 1, wherein the semiconductor wafer has a plurality of metal pins attached to the substrate, wherein the semiconductor device is packaged on a surface of the semiconductor device opposite to the packaged semiconductor device Flat surface. 3. A device as claimed in claim W, wherein the second regions constitute a number of symbols that convey information about the device. 135484-10108l7.doc 1375313 The preparation of claim 1, wherein the sheet has a thickness of between about 1 and 10 from m. 5. As requested! Apparatus wherein the sheet is selected from the group consisting of. - A (tetra) aldehyde epoxy resin and a mixture of bisphenol A polymerized compounds. 6) The apparatus of claim 5, wherein the polymeric compound further comprises a chemical molecule. sit. 7. The device of claim 6 wherein the polymeric compound is operative to change the first optical reflectance to the second optical reflectivity after absorbing a pulse of light energy or thermal energy. ^ 8. The device of claim 5, wherein the first regions further have a first color and the second regions 1 have a color-by-color, wherein the second color is different from the [color And wherein the polymeric compound is further operated to change the first color to the second color after absorbing a pulse of light energy or thermal energy. / </ RTI> a method for manufacturing a semiconductor package device, comprising: placing a piece of material having a first optical reflectivity on a flat surface of a semiconductor device 'by which the sheet contacts the device And a bare surface of the sheet faces away from the device; raising the temperature of the device and the sheet for a period of time to solidify contact between the sheet and the device; focusing a pulsed energy beam at a point on the surface of the bare sheet such that The pulse energy is absorbed by the material, thereby changing the -first reflectance of the point to a second reflectance different from the first reflectivity; and 135484-1010817.doc 1375313 to form if repeated at several adjacent points This step of focusing the energy pulse drys the region of the second reflectivity. The method of item 9, which has a method of about U., such as: Item 9, wherein the sheet is selected from - from -. · Cresol A phenolic resin is prepared by polymerizing a compound of a group consisting of oxime resin and bisphenol A. 12. The method of claim U, wherein the polymeric compound further comprises a chemical molecule imidazole. ^ G3化13. A method for fabricating a semiconductor device, comprising the steps of: connecting a plurality of semiconductor wafers to a substrate strip by a shape-changing bonding wire to the top of the substrate; The strip is placed on the bottom of a molded cavity such that the lead arches are oriented upwardly from the bottom; and a material having a drop reflectivity is placed on the flat cover of the mold, thus a sheet facing the cavity; the lid being placed over the cavity to close the cavity; raising the temperature of the mold and the strip; filling the mold cavity with a potting compound, thereby arching the wafer and the lead Forming the compound into the compound and attaching the sheet to the compound; lifting the mold cover from the thin month, thereby exposing the exposed surface of the attachment sheet; focusing a pulsed energy beam on one of the surfaces of the bare sheet The pulse energy is absorbed by the material, so the first reflectivity of the point 135484-10108l7.doc 1375313 14. is changed to a second reflectance 不同于 different from the first reflectance and Repeat steps focused pulses of energy to form the ortho-point region having a second reflectivity. Such as. The method of claim 13, further comprising the steps of: attaching a plurality of solder bodies to the substrate strip for connection to respective external parts; and 15. separating the substrate strip into a plurality of wafers having a stem-dry conductor A method for fabricating a semiconductor device comprising the steps of: assembling a plurality of semiconductor wafers on a substrate strip having a plurality of metal terminations and having a plurality of metal pads; The terminals are connected to the pads, such as a plurality of chess piece bonding leads (4), to reach the top end; the strip is placed on the bottom of the cavity of the cavity The lead arches are oriented upwardly from the bottom; a sheet of a first polymeric compound is placed flat on the mold cover 'so that the sheet faces the cavity, the compound has an optical reflectivity; * will have The mold cover of the sheet is lowered onto the mold cavity until the sheet contacts the top end of the arches of the assembled wafers, and the mold cavity is filled with the _polymer compound, so the wafers And the lead arches are embedded in the second compound and the second compound contacts the sheet; when the second compound is polymerized, the sheet is solidified and the second compound is placed 135484-1010817.doc 1375313 a compound; thus exposing the contact of the sheet, thereby attaching the sheet to the bare meter, lifting the mold cover from the sheet; a pulse energy beam focused on the surface of the bare sheet - 6 - absorption of the compound, thus the first: the reflection: a second reflectance different from the first reflectance ^ at a number of adjacent points to form a step of focusing on the pulse a plurality of regions having a second reflectivity; and separating the substrate strip into a plurality of discrete packages 16 having a semiconductor wafer, the semiconductor packaging device comprising: a semiconductor device having a flat surface of one of the molded composites; a polymeric (four) sheet that adheres to the flat surface and is coextensive with the flat surface; a plurality of regions visible on the flat surface, There has been no molecular interference to leave a number of imprints without adding or losing any material from the sheet; and a semiconductor wafer that is attached to a substrate using a bond wire that is exposed and contacted from the mold compound The polymer sheet. 17. The device of claim 16, wherein the plurality of regions have distinct reflectivities created by the interference of the molecules. 18. The device of claim 16, wherein the plurality of regions have distinct colors produced by the interference of the molecules. 135484-1010817.doc
TW97140035A 2008-10-17 2008-10-17 Semiconductor package having marking layer TWI375313B (en)

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