TWI372347B - Method of making a semiconductor device by balancing shallow trench isolation stress and optical proximity effects - Google Patents

Method of making a semiconductor device by balancing shallow trench isolation stress and optical proximity effects

Info

Publication number
TWI372347B
TWI372347B TW094139974A TW94139974A TWI372347B TW I372347 B TWI372347 B TW I372347B TW 094139974 A TW094139974 A TW 094139974A TW 94139974 A TW94139974 A TW 94139974A TW I372347 B TWI372347 B TW I372347B
Authority
TW
Taiwan
Prior art keywords
balancing
making
semiconductor device
trench isolation
shallow trench
Prior art date
Application number
TW094139974A
Other languages
English (en)
Other versions
TW200622740A (en
Inventor
James D Chlipala
Shahriar Moinian
Original Assignee
Agere Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agere Systems Inc filed Critical Agere Systems Inc
Publication of TW200622740A publication Critical patent/TW200622740A/zh
Application granted granted Critical
Publication of TWI372347B publication Critical patent/TWI372347B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Theoretical Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Geometry (AREA)
  • Evolutionary Computation (AREA)
  • Manufacturing & Machinery (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Element Separation (AREA)
TW094139974A 2004-11-18 2005-11-14 Method of making a semiconductor device by balancing shallow trench isolation stress and optical proximity effects TWI372347B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/992,031 US7174532B2 (en) 2004-11-18 2004-11-18 Method of making a semiconductor device by balancing shallow trench isolation stress and optical proximity effects

Publications (2)

Publication Number Publication Date
TW200622740A TW200622740A (en) 2006-07-01
TWI372347B true TWI372347B (en) 2012-09-11

Family

ID=36387953

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094139974A TWI372347B (en) 2004-11-18 2005-11-14 Method of making a semiconductor device by balancing shallow trench isolation stress and optical proximity effects

Country Status (4)

Country Link
US (1) US7174532B2 (zh)
JP (1) JP5378636B2 (zh)
KR (1) KR101097710B1 (zh)
TW (1) TWI372347B (zh)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7824933B2 (en) * 2005-03-08 2010-11-02 International Business Machines Corporation Method of determining n-well scattering effects on FETs
KR100628247B1 (ko) * 2005-09-13 2006-09-27 동부일렉트로닉스 주식회사 반도체 소자
US7600207B2 (en) * 2006-02-27 2009-10-06 Synopsys, Inc. Stress-managed revision of integrated circuit layouts
US7767515B2 (en) * 2006-02-27 2010-08-03 Synopsys, Inc. Managing integrated circuit stress using stress adjustment trenches
US7484198B2 (en) * 2006-02-27 2009-01-27 Synopsys, Inc. Managing integrated circuit stress using dummy diffusion regions
JP5096719B2 (ja) * 2006-09-27 2012-12-12 パナソニック株式会社 回路シミュレーション方法及び回路シミュレーション装置
US7761278B2 (en) * 2007-02-12 2010-07-20 International Business Machines Corporation Semiconductor device stress modeling methodology
US7949985B2 (en) * 2007-06-01 2011-05-24 Synopsys, Inc. Method for compensation of process-induced performance variation in a MOSFET integrated circuit
JP2009026829A (ja) * 2007-07-17 2009-02-05 Nec Electronics Corp 半導体集積回路の設計方法及びマスクデータ作成プログラム
US7895548B2 (en) * 2007-10-26 2011-02-22 Synopsys, Inc. Filler cells for design optimization in a place-and-route system
US9472423B2 (en) * 2007-10-30 2016-10-18 Synopsys, Inc. Method for suppressing lattice defects in a semiconductor substrate
US8572519B2 (en) * 2010-04-12 2013-10-29 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for reducing implant topography reflection effect
JP5530804B2 (ja) * 2010-05-17 2014-06-25 パナソニック株式会社 半導体装置、半導体装置製造用マスク及び光近接効果補正方法
CN102436132B (zh) * 2011-09-08 2017-05-10 上海华力微电子有限公司 一种根据不同衬底进行光学临近修正的方法
US8928110B2 (en) * 2011-09-09 2015-01-06 United Microelectronics Corp. Dummy cell pattern for improving device thermal uniformity
JP2024039422A (ja) * 2022-09-09 2024-03-22 株式会社デンソー 特性予測システム

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2845303B2 (ja) * 1991-08-23 1999-01-13 株式会社 半導体エネルギー研究所 半導体装置とその作製方法
JP3311244B2 (ja) * 1996-07-15 2002-08-05 株式会社東芝 基本セルライブラリ及びその形成方法
JP2003179157A (ja) * 2001-12-10 2003-06-27 Nec Corp Ｍｏｓ型半導体装置
JP2004055826A (ja) 2002-07-19 2004-02-19 Renesas Technology Corp 半導体装置の製造方法

Also Published As

Publication number Publication date
KR20060055414A (ko) 2006-05-23
KR101097710B1 (ko) 2011-12-23
US7174532B2 (en) 2007-02-06
JP2006148116A (ja) 2006-06-08
TW200622740A (en) 2006-07-01
JP5378636B2 (ja) 2013-12-25
US20060107243A1 (en) 2006-05-18

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