TWI366132B - System and method for monitoring an address range and processor core comprising a monitoring unit - Google Patents

System and method for monitoring an address range and processor core comprising a monitoring unit

Info

Publication number
TWI366132B
TWI366132B TW094133303A TW94133303A TWI366132B TW I366132 B TWI366132 B TW I366132B TW 094133303 A TW094133303 A TW 094133303A TW 94133303 A TW94133303 A TW 94133303A TW I366132 B TWI366132 B TW I366132B
Authority
TW
Taiwan
Prior art keywords
monitoring
processor core
address range
monitoring unit
unit
Prior art date
Application number
TW094133303A
Other languages
English (en)
Other versions
TW200627271A (en
Inventor
Michael T Clark
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of TW200627271A publication Critical patent/TW200627271A/zh
Application granted granted Critical
Publication of TWI366132B publication Critical patent/TWI366132B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30083—Power or thermal control instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30087—Synchronisation or serialisation instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3889—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute
    • G06F9/3891—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute organised in groups of units sharing resources, e.g. clusters

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Debugging And Monitoring (AREA)
TW094133303A 2004-10-01 2005-09-26 System and method for monitoring an address range and processor core comprising a monitoring unit TWI366132B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/956,685 US7257679B2 (en) 2004-10-01 2004-10-01 Sharing monitored cache lines across multiple cores

Publications (2)

Publication Number Publication Date
TW200627271A TW200627271A (en) 2006-08-01
TWI366132B true TWI366132B (en) 2012-06-11

Family

ID=35994769

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094133303A TWI366132B (en) 2004-10-01 2005-09-26 System and method for monitoring an address range and processor core comprising a monitoring unit

Country Status (8)

Country Link
US (1) US7257679B2 (zh)
EP (1) EP1807754B1 (zh)
JP (1) JP4982375B2 (zh)
KR (1) KR101216190B1 (zh)
CN (1) CN101036116B (zh)
DE (1) DE602005020960D1 (zh)
TW (1) TWI366132B (zh)
WO (1) WO2006039162A2 (zh)

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TWI656444B (zh) * 2015-11-13 2019-04-11 日電平臺股份有限公司 Scope external reference detecting device, method and recording medium

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US7502948B2 (en) * 2004-12-30 2009-03-10 Intel Corporation Method, system, and apparatus for selecting a maximum operation point based on number of active cores and performance level of each of the active cores
US7484053B2 (en) * 2005-05-16 2009-01-27 Texas Instruments Incorporated Cross-referencing cache line addresses with corresponding names
US7444474B2 (en) * 2005-05-16 2008-10-28 Texas Instruments Incorporated Determining the presence of a virtual address in a cache
US8281083B2 (en) 2005-06-30 2012-10-02 Intel Corporation Device, system and method of generating an execution instruction based on a memory-access instruction
US9003421B2 (en) * 2005-11-28 2015-04-07 Intel Corporation Acceleration threads on idle OS-visible thread execution units
US20070271450A1 (en) * 2006-05-17 2007-11-22 Doshi Kshitij A Method and system for enhanced thread synchronization and coordination
US9710384B2 (en) 2008-01-04 2017-07-18 Micron Technology, Inc. Microprocessor architecture having alternative memory access paths
US8561037B2 (en) * 2007-08-29 2013-10-15 Convey Computer Compiler for generating an executable comprising instructions for a plurality of different instruction sets
US8122229B2 (en) * 2007-09-12 2012-02-21 Convey Computer Dispatch mechanism for dispatching instructions from a host processor to a co-processor
US8156307B2 (en) * 2007-08-20 2012-04-10 Convey Computer Multi-processor system having at least one processor that comprises a dynamically reconfigurable instruction set
US9015399B2 (en) 2007-08-20 2015-04-21 Convey Computer Multiple data channel memory module architecture
US8095735B2 (en) 2008-08-05 2012-01-10 Convey Computer Memory interleave for heterogeneous computing
US20090106755A1 (en) * 2007-10-19 2009-04-23 Sundeep Chandhoke Programmable Controller with Multiple Processors Using Scanning and Data Acquisition Architectures
US9336051B2 (en) * 2007-10-19 2016-05-10 National Instruments Corporation Programmable controller with multiple processors using a scanning architecture
US20090309243A1 (en) * 2008-06-11 2009-12-17 Nvidia Corporation Multi-core integrated circuits having asymmetric performance between cores
US8205066B2 (en) * 2008-10-31 2012-06-19 Convey Computer Dynamically configured coprocessor for different extended instruction set personality specific to application program with shared memory storing instructions invisibly dispatched from host processor
US20100115233A1 (en) * 2008-10-31 2010-05-06 Convey Computer Dynamically-selectable vector register partitioning
US8156275B2 (en) * 2009-05-13 2012-04-10 Apple Inc. Power managed lock optimization
US8364862B2 (en) * 2009-06-11 2013-01-29 Intel Corporation Delegating a poll operation to another device
US8423745B1 (en) 2009-11-16 2013-04-16 Convey Computer Systems and methods for mapping a neighborhood of data to general registers of a processing element
US8631256B2 (en) 2010-12-22 2014-01-14 Via Technologies, Inc. Distributed management of a shared power source to a multi-core microprocessor
US8635476B2 (en) * 2010-12-22 2014-01-21 Via Technologies, Inc. Decentralized power management distributed among multiple processor cores
US8972707B2 (en) 2010-12-22 2015-03-03 Via Technologies, Inc. Multi-core processor with core selectively disabled by kill instruction of system software and resettable only via external pin
CN103955265B (zh) * 2010-12-22 2017-04-12 威盛电子股份有限公司 配置在多重处理器核心之间的分散式电源管理
US8637212B2 (en) 2010-12-22 2014-01-28 Via Technologies, Inc. Reticle set modification to produce multi-core dies
US8782451B2 (en) * 2010-12-22 2014-07-15 Via Technologies, Inc. Power state synchronization in a multi-core processor
US8930676B2 (en) 2010-12-22 2015-01-06 Via Technologies, Inc. Master core discovering enabled cores in microprocessor comprising plural multi-core dies
US9460038B2 (en) 2010-12-22 2016-10-04 Via Technologies, Inc. Multi-core microprocessor internal bypass bus
US8819349B2 (en) * 2011-07-08 2014-08-26 Facebook, Inc. Invoking operating system functionality without the use of system calls
US8713262B2 (en) 2011-09-02 2014-04-29 Nvidia Corporation Managing a spinlock indicative of exclusive access to a system resource
US8868843B2 (en) 2011-11-30 2014-10-21 Advanced Micro Devices, Inc. Hardware filter for tracking block presence in large caches
CN106909444B (zh) 2011-12-22 2021-01-12 英特尔公司 用于指定应用线程性能状态的指令的指令处理装置及相关方法
WO2013147887A1 (en) 2012-03-30 2013-10-03 Intel Corporation Context switching mechanism for a processing core having a general purpose cpu core and a tightly coupled accelerator
US10430190B2 (en) 2012-06-07 2019-10-01 Micron Technology, Inc. Systems and methods for selectively controlling multithreaded execution of executable code segments
US9218288B2 (en) * 2012-06-15 2015-12-22 International Business Machines Corporation Monitoring a value in storage without repeated storage access
US9792112B2 (en) 2013-08-28 2017-10-17 Via Technologies, Inc. Propagation of microcode patches to multiple cores in multicore microprocessor
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US9535488B2 (en) 2013-08-28 2017-01-03 Via Technologies, Inc. Multi-core microprocessor that dynamically designates one of its processing cores as the bootstrap processor
US10394678B2 (en) 2016-12-29 2019-08-27 Intel Corporation Wait and poll instructions for monitoring a plurality of addresses
CN108009121B (zh) * 2017-12-21 2021-12-07 中国电子科技集团公司第四十七研究所 面向应用的动态多核配置方法
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US11237960B2 (en) 2019-05-21 2022-02-01 Arm Limited Method and apparatus for asynchronous memory write-back in a data processing system
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI656444B (zh) * 2015-11-13 2019-04-11 日電平臺股份有限公司 Scope external reference detecting device, method and recording medium

Also Published As

Publication number Publication date
TW200627271A (en) 2006-08-01
JP4982375B2 (ja) 2012-07-25
EP1807754B1 (en) 2010-04-28
WO2006039162A2 (en) 2006-04-13
DE602005020960D1 (de) 2010-06-10
EP1807754A2 (en) 2007-07-18
KR20070057906A (ko) 2007-06-07
WO2006039162A3 (en) 2007-03-15
KR101216190B1 (ko) 2012-12-28
US20060075060A1 (en) 2006-04-06
US7257679B2 (en) 2007-08-14
CN101036116A (zh) 2007-09-12
CN101036116B (zh) 2010-08-11
JP2008515096A (ja) 2008-05-08

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